From nobody Wed Oct 8 23:44:12 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28B572C3245; Mon, 23 Jun 2025 16:07:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750694881; cv=none; b=m/jEi8/NXw9sfEJmgDuLM8egsPBOtsgiqmWhahSEdUTrp8GkSX7Q3e1y4jIFWoMJC0Zm9iS7Prt1GDfcZ1U5ejpcQ/BOwH38Vw0FaV2z3tlu7vXYwXqA1KXLgeX2fjtffEAYDZ8wYcLiHrfqkSzLL6b3FoDql5DrkQdf1yELBrs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750694881; c=relaxed/simple; bh=LAtHIDsXc48M+4SNF2evd23d5+2WZS3MzWRndXBDn7c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JnWE84LjZugcc0tTLjNjgr+hyeED+7+bGKuxDQNu6IXD+1tWtACzRq9MjpdVL9dghRZAtl3TVCoXQ2yT3/hRgjspcbsZCGhSj0v0+sqowugI0mnDZLt6rVzrE6Ywpo+oyqsoq2y9ndMnqLbJAZSuK0kTuiXSkFQ6Tbbm00taKAQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=SaB0zpAH; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="SaB0zpAH" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1750694878; bh=LAtHIDsXc48M+4SNF2evd23d5+2WZS3MzWRndXBDn7c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SaB0zpAHjXwCGcMTaY4yKSJkhwbsYNN+QC6lQXd0qEINs3aPwKdC8+EugvoX3hzlq 3OUzwmZZxTvvoSqVwZYy09nSEJYvKMToPzJ58ikI46LFNMO2/hziBfrwxoSZCljo9z V0umNgidaM6cVS4GYIz41lFQlzWyjL/AcpfWiRYiWv/MTIulK72WfOXj5jKiL+czuG P89Z9sZbvN/4PbRvlXY2xhUhBSBtpS+gkou5omQar5r//iUAtCA6ogeOn006Ur0guq WMCQe8/65QrsOKEKebY/rVx1k6edtBoA0QfgCkkM4oWSb6TP0V03cOh6F9OWOMJCSI CDEkXG+SA5oWQ== Received: from trenzalore.hitronhub.home (unknown [23.233.251.139]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: detlev) by bali.collaboradmins.com (Postfix) with ESMTPSA id 12DAC17E35D3; Mon, 23 Jun 2025 18:07:54 +0200 (CEST) From: Detlev Casanova To: linux-kernel@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Sebastian Reichel , Cristian Ciocaltea , Alexey Charkov , Dragan Simic , Jianfeng Liu , Nicolas Frattaroli , Kever Yang , Detlev Casanova , Andy Yan , Frank Wang , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Ezequiel Garcia , Mauro Carvalho Chehab , Hans Verkuil , Ricardo Ribalda , Hans de Goede , Yunke Cao , linux-media@vger.kernel.org, kernel@collabora.com Subject: [PATCH 4/8] arm64: dts: rockchip: Add the vdpu383 Video Decoder on rk3576 Date: Mon, 23 Jun 2025 12:07:18 -0400 Message-ID: <20250623160722.55938-5-detlev.casanova@collabora.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250623160722.55938-1-detlev.casanova@collabora.com> References: <20250623160722.55938-1-detlev.casanova@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the vdpu383 Video Decoder variant to the RK3576 device tree. Also allow using the dedicated SRAM as a pool. Signed-off-by: Detlev Casanova --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 36 ++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts= /rockchip/rk3576.dtsi index b1ac23035dd78..26896ac22cedf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1139,6 +1139,41 @@ gpu: gpu@27800000 { status =3D "disabled"; }; =20 + vdec: video-codec@27b00000 { + compatible =3D "rockchip,rk3576-vdec"; + reg =3D <0x0 0x27b00100 0x0 0x500>, + <0x0 0x27b00000 0x0 0x100>, + <0x0 0x27b00600 0x0 0x100>; + reg-names =3D "function", "link", "cache"; + interrupts =3D ; + clocks =3D <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC>, + <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_CORE>, + <&cru CLK_RKVDEC_HEVC_CA>; + clock-names =3D "axi", "ahb", "cabac", "core", "hevc_cabac"; + assigned-clocks =3D <&cru ACLK_RKVDEC_ROOT>, <&cru CLK_RKVDEC_CORE>, + <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_HEVC_CA>; + assigned-clock-rates =3D <600000000>, <600000000>, + <500000000>, <1000000000>; + iommus =3D <&vdec_mmu>; + power-domains =3D <&power RK3576_PD_VDEC>; + resets =3D <&cru SRST_A_RKVDEC_BIU>, <&cru SRST_H_RKVDEC_BIU>, + <&cru SRST_H_RKVDEC>, <&cru SRST_RKVDEC_CORE>, + <&cru SRST_RKVDEC_HEVC_CA>; + reset-names =3D "axi", "ahb", "cabac", "core", "hevc_cabac"; + sram =3D <&rkvdec_sram>; + }; + + vdec_mmu: iommu@27b00800 { + compatible =3D "rockchip,rk3576-iommu", "rockchip,rk3568-iommu"; + reg =3D <0x0 0x27b00800 0x0 0x40>, <0x0 0x27b00900 0x0 0x40>; + interrupts =3D ; + clocks =3D <&cru CLK_RKVDEC_CORE>, <&cru HCLK_RKVDEC>; + clock-names =3D "aclk", "iface"; + power-domains =3D <&power RK3576_PD_VDEC>; + rockchip,disable-mmu-reset; + #iommu-cells =3D <0>; + }; + vop: vop@27d00000 { compatible =3D "rockchip,rk3576-vop"; reg =3D <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>; @@ -2412,6 +2447,7 @@ sram: sram@3ff88000 { /* start address and size should be 4k align */ rkvdec_sram: rkvdec-sram@0 { reg =3D <0x0 0x78000>; + pool; }; }; =20 --=20 2.50.0