From nobody Wed Oct 8 23:45:03 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 747C22C08B1; Mon, 23 Jun 2025 16:07:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750694878; cv=none; b=E/C/zPt2cx9wdL8MnOleT3d/AxB2aWhV/x7PC56dek8mdDWfp9UUcF7xOMPD3ZcavCDCadzmzLBFpKWC76hLkMOGYGB5V4NiZaPBLGVZbmwzcS6V2vSAVfKjzS+3WC26rcAh2/1VgXoIWx2Msb0mVKgfJC2hTMSgm/IiXH94dWI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750694878; c=relaxed/simple; bh=zt/DaCss2i5ulknRW3sJNkFnzwFerUvIICmaqy3KydU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oD2yMUxXMaAKxQhl4XqeDjzFUPF4LH/wRhbaCyvIruA4XIeV6dV66j9DIkIKyBQhaaBbUWTT8Pnki2WH8GMAuNvj2rQdSdMRdAmKwS42LD9TrUyywEaCF/lkciIagS/PEiuRZlb8TeYLGTwYYwtwOQoQazt8EsaJXfElPjRA2o0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=gvKMbe3b; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="gvKMbe3b" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1750694874; bh=zt/DaCss2i5ulknRW3sJNkFnzwFerUvIICmaqy3KydU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gvKMbe3b4XE3UscHhE6pkbYBUhJlem382157apB5Hu7W52ybOAb4wdwyvJPSCtS5R KV1SJCmsRmtga1KWke6xeJCvC1NXXw6Ve4j1y++g1CnqVsBg4bnsKvShEEcfKQUuSu NTvjvaP/Bn2eg29kdKMeRRYG+YRLZkF0cCjvWCdJ8bpFZ6IznZlqNVm5Evtq5FGeX3 zNHbKZue9Nj0hAsw+afPUrOWAnqRSkz+WipJBf/pbtjJzYkPzH+KUDaSvSnMxd8fYB zOlElfRbwAcjnXfXoyPVmyFr8z+PRHKQg+ckeyH3hD2w/pvRUplGSe24waD42StvZ4 zLvfMt3E+ODYA== Received: from trenzalore.hitronhub.home (unknown [23.233.251.139]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: detlev) by bali.collaboradmins.com (Postfix) with ESMTPSA id 70AEB17E1580; Mon, 23 Jun 2025 18:07:51 +0200 (CEST) From: Detlev Casanova To: linux-kernel@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Sebastian Reichel , Cristian Ciocaltea , Alexey Charkov , Dragan Simic , Jianfeng Liu , Nicolas Frattaroli , Kever Yang , Detlev Casanova , Andy Yan , Frank Wang , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Ezequiel Garcia , Mauro Carvalho Chehab , Hans Verkuil , Ricardo Ribalda , Hans de Goede , Yunke Cao , linux-media@vger.kernel.org, kernel@collabora.com Subject: [PATCH 3/8] arm64: dts: rockchip: Add the vdpu381 Video Decoders on RK3588 Date: Mon, 23 Jun 2025 12:07:17 -0400 Message-ID: <20250623160722.55938-4-detlev.casanova@collabora.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250623160722.55938-1-detlev.casanova@collabora.com> References: <20250623160722.55938-1-detlev.casanova@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the vdpu381 Video Decoders to the rk3588-base devicetree. The RK3588 based SoCs all embed 2 vdpu381 decoders. This also adds the dedicated IOMMU controllers. Signed-off-by: Detlev Casanova --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3588-base.dtsi index 70f03e68ba550..c1eaff86d5b73 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1252,6 +1252,70 @@ vepu121_3_mmu: iommu@fdbac800 { #iommu-cells =3D <0>; }; =20 + vdec0: video-codec@fdc38000 { + compatible =3D "rockchip,rk3588-vdec"; + reg =3D <0x0 0xfdc38100 0x0 0x500>, + <0x0 0xfdc38000 0x0 0x100>, + <0x0 0xfdc38600 0x0 0x100>; + reg-names =3D "function", "link", "cache"; + interrupts =3D ; + clocks =3D <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_C= A>, + <&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>; + clock-names =3D "axi", "ahb", "cabac", "core", "hevc_cabac"; + assigned-clocks =3D <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>, + <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>; + assigned-clock-rates =3D <800000000>, <600000000>, + <600000000>, <1000000000>; + iommus =3D <&vdec0_mmu>; + power-domains =3D <&power RK3588_PD_RKVDEC0>; + resets =3D <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVD= EC0_CA>, + <&cru SRST_RKVDEC0_CORE>, <&cru SRST_RKVDEC0_HEVC_CA>; + reset-names =3D "axi", "ahb", "cabac", "core", "hevc_cabac"; + sram =3D <&vdec0_sram>; + }; + + vdec0_mmu: iommu@fdc38700 { + compatible =3D "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg =3D <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>; + interrupts =3D ; + clocks =3D <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>; + clock-names =3D "aclk", "iface"; + power-domains =3D <&power RK3588_PD_RKVDEC0>; + #iommu-cells =3D <0>; + }; + + vdec1: video-codec@fdc40000 { + compatible =3D "rockchip,rk3588-vdec"; + reg =3D <0x0 0xfdc40100 0x0 0x500>, + <0x0 0xfdc40000 0x0 0x100>, + <0x0 0xfdc40600 0x0 0x100>; + reg-names =3D "function", "link", "cache"; + interrupts =3D ; + clocks =3D <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_C= A>, + <&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>; + clock-names =3D "axi", "ahb", "cabac", "core", "hevc_cabac"; + assigned-clocks =3D <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>, + <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>; + assigned-clock-rates =3D <800000000>, <600000000>, + <600000000>, <1000000000>; + iommus =3D <&vdec1_mmu>; + power-domains =3D <&power RK3588_PD_RKVDEC1>; + resets =3D <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVD= EC1_CA>, + <&cru SRST_RKVDEC1_CORE>, <&cru SRST_RKVDEC1_HEVC_CA>; + reset-names =3D "axi", "ahb", "cabac", "core", "hevc_cabac"; + sram =3D <&vdec1_sram>; + }; + + vdec1_mmu: iommu@fdc40700 { + compatible =3D "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg =3D <0x0 0xfdc40700 0x0 0x40>, <0x0 0xfdc40740 0x0 0x40>; + interrupts =3D ; + clocks =3D <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>; + clock-names =3D "aclk", "iface"; + power-domains =3D <&power RK3588_PD_RKVDEC1>; + #iommu-cells =3D <0>; + }; + av1d: video-codec@fdc70000 { compatible =3D "rockchip,rk3588-av1-vpu"; reg =3D <0x0 0xfdc70000 0x0 0x800>; @@ -3093,6 +3157,16 @@ system_sram2: sram@ff001000 { ranges =3D <0x0 0x0 0xff001000 0xef000>; #address-cells =3D <1>; #size-cells =3D <1>; + + vdec0_sram: codec-sram@0 { + reg =3D <0x0 0x78000>; + pool; + }; + + vdec1_sram: codec-sram@78000 { + reg =3D <0x78000 0x77000>; + pool; + }; }; =20 pinctrl: pinctrl { --=20 2.50.0