From nobody Thu Oct 9 00:34:39 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF8662566DF; Mon, 23 Jun 2025 14:13:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750688027; cv=none; b=e61JoQYq6ZJMYugcwQbwbBvuXOhp4defB+6PyIRAsOmw2vPqBPVNF6Rxb6/WssdJE2UWw4TYJcv2gaHwZ7QBoYf7w/TnvlDNVG+Q3u8iwqJKNeKLc9qB9uGEiKcIpRT1XQnARm66NlWGv988BHvyeXmURQO6bOkSm7g69HqvbQc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750688027; c=relaxed/simple; bh=tk+iYmrmEwtQVHbf9jO25J5baC4U41y1SMRB0MHbKqw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WbxRkInbW/vrKWiDvYkHwSSCIMTajISQxv7alIMI3hTJF1qOChcKOek/2risrEZ0FP4JYQWgmDpSZif/7kyCoGOHtgQercubgFA4TJ3hD1KCw3iSTK4dxNa1P6v5RfD9vOCHpvQVi1PSVz3O/KgsXuUa46Na1lVG9XndfhbDCR4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=StueOXpH; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="StueOXpH" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 55NEDfXP1572848; Mon, 23 Jun 2025 09:13:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1750688021; bh=HBO5CcGznAwIN9/5B2PE/8D6YEy4TOPnjiqgMTrUWDI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=StueOXpHNQaE00rRvhj734lNU3Lxn03jzgWzvCmgFWcNdbs2XUv6htG9576+W4gEn IGAXQV9zTh7zYuHAy7o46/gckIHZ6ejEt+p2yWtEQvkNttJpFqPn4P9sfpoMHQKgHk VGmuymaOjuigJ6gN7gZlYks4C9MQ9UKusbX0Shuo= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 55NEDf8u574429 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 23 Jun 2025 09:13:41 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 23 Jun 2025 09:13:41 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 23 Jun 2025 09:13:41 -0500 Received: from localhost (ula0502350.dhcp.ti.com [172.24.227.38]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 55NEDe783987722; Mon, 23 Jun 2025 09:13:41 -0500 From: Paresh Bhagat To: , , CC: , , , , , , , , , , , Subject: [PATCHv4 6/6] arm64: dts: ti: Add eMMC support for AM62D Date: Mon, 23 Jun 2025 19:42:53 +0530 Message-ID: <20250623141253.3519546-7-p-bhagat@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250623141253.3519546-1-p-bhagat@ti.com> References: <20250623141253.3519546-1-p-bhagat@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Add the necessary device tree node for eMMC controller along with the required pinmux configuration. Signed-off-by: Paresh Bhagat --- arch/arm64/boot/dts/ti/k3-am62d2-evm.dts | 27 ++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts= /ti/k3-am62d2-evm.dts index c98e4c98c956..5ceecdd68b3f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts @@ -20,6 +20,7 @@ aliases { serial0 =3D &wkup_uart0; serial1 =3D &mcu_uart0; serial2 =3D &main_uart0; + mmc0 =3D &sdhci0; mmc1 =3D &sdhci1; rtc0 =3D &wkup_rtc0; ethernet0 =3D &cpsw_port1; @@ -226,6 +227,22 @@ AM62DX_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (M20) GPM= C0_CSn3.I2C2_SDA */ >; }; =20 + main_mmc0_pins_default: main-mmc0-default-pins { + pinctrl-single,pins =3D < + AM62DX_IOPAD(0x0220, PIN_INPUT_PULLUP, 0) /* (Y6) MMC0_CMD */ + AM62DX_IOPAD(0x0218, PIN_OUTPUT, 0) /* (AB7) MMC0_CLK */ + AM62DX_IOPAD(0x0214, PIN_INPUT_PULLUP, 0) /* (AA6) MMC0_DAT0 */ + AM62DX_IOPAD(0x0210, PIN_INPUT_PULLUP, 0) /* (AB6) MMC0_DAT1 */ + AM62DX_IOPAD(0x020c, PIN_INPUT_PULLUP, 0) /* (Y7) MMC0_DAT2 */ + AM62DX_IOPAD(0x0208, PIN_INPUT_PULLUP, 0) /* (AA7) MMC0_DAT3 */ + AM62DX_IOPAD(0x0204, PIN_INPUT_PULLUP, 0) /* (Y8) MMC0_DAT4 */ + AM62DX_IOPAD(0x0200, PIN_INPUT_PULLUP, 0) /* (W7) MMC0_DAT5 */ + AM62DX_IOPAD(0x01fc, PIN_INPUT_PULLUP, 0) /* (W9) MMC0_DAT6 */ + AM62DX_IOPAD(0x01f8, PIN_INPUT_PULLUP, 0) /* (AB8) MMC0_DAT7 */ + >; + bootph-all; + }; + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins =3D < AM62DX_IOPAD(0x023c, PIN_INPUT, 0) /* (C21) MMC1_CMD */ @@ -397,6 +414,16 @@ &main_i2c2 { clock-frequency =3D <400000>; }; =20 +&sdhci0 { + /* eMMC */ + bootph-all; + status =3D "okay"; + non-removable; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_mmc0_pins_default>; + disable-wp; +}; + &sdhci1 { /* SD/MMC */ status =3D "okay"; --=20 2.34.1