From nobody Thu Oct 9 00:34:39 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F3998230996; Mon, 23 Jun 2025 14:13:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750688017; cv=none; b=R7LQ1AEUkgW3VC98bbcSUVeO72/+qb7BK9TrxQNmHV/DubjW0w74GBti+ipRtUkIuHz5vz/kyJ5LW7gOmYUHuDERI8XJ12teX146X1dx6JiXWHPHHqV2UcpuodbHkgdrjxmV0Tcf1wYZZabp3Ix2caJg+g89ACERp5ajIkiq/cw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750688017; c=relaxed/simple; bh=1A9CY0H/kYTojtxll//4SQPbJ+jWznvduyifJPT4qpI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=aY7JvjlqS+q20XoaYAwehuPm63OlFS6vZK39URGOogoJNGj03KdEl461+OXKaVXHsW4ZABomg9PY7meW2rks5Xb6l200Ni8r++y7s2YnVSwUQ2mBQUYtNBjZM6Fn+HsxG3A9oIGHrgdYNMt4Y6YjAS3HM5oDSqK/LqI0Nxx58qE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=VHH2vr2K; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="VHH2vr2K" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTP id 55NEDVsT1275276; Mon, 23 Jun 2025 09:13:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1750688011; bh=2nB2XrYs3/yr4cfRNXfAXTu6rjkWvNQLgoMjODS48vE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=VHH2vr2K13yXGeek753eT9FmMH4mWs4Yb3l9FyE05tu+RrFei3ianogO8670W8byJ iJbOzNe5sAcmyuKXoNeOG9tALOnndb+3jSh+DcaItJ0LLmo0J87kXz87vXpfk5PsGS +jPdToKsUV2QyV1qKacO7qNxmFNXxLuZqWlKQU2Q= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 55NEDU6I3541181 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 23 Jun 2025 09:13:31 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 23 Jun 2025 09:13:30 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 23 Jun 2025 09:13:30 -0500 Received: from localhost (ula0502350.dhcp.ti.com [172.24.227.38]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 55NEDTaQ050299; Mon, 23 Jun 2025 09:13:30 -0500 From: Paresh Bhagat To: , , CC: , , , , , , , , , , , Subject: [PATCHv4 3/6] arm64: dts: ti: Add pinctrl entries for AM62D2 family of SoCs Date: Mon, 23 Jun 2025 19:42:50 +0530 Message-ID: <20250623141253.3519546-4-p-bhagat@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250623141253.3519546-1-p-bhagat@ti.com> References: <20250623141253.3519546-1-p-bhagat@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Update k3-pinctrl file to include pin definitions for AM62D2 family of SoCs. Signed-off-by: Paresh Bhagat --- arch/arm64/boot/dts/ti/k3-pinctrl.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k= 3-pinctrl.h index cac7cccc1112..0cf57179c974 100644 --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h @@ -63,6 +63,9 @@ #define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmod= e)) #define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (mux= mode)) =20 +#define AM62DX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmod= e)) +#define AM62DX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (mux= mode)) + #define AM62PX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmod= e)) #define AM62PX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (mux= mode)) =20 --=20 2.34.1