From nobody Thu Oct 9 00:34:39 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BAB43253951; Mon, 23 Jun 2025 14:13:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750688015; cv=none; b=PaAW3/WOQq5vkHHhiYFjpTJrrZ5BWTkwvuIh3OauKBrx/Wi/ohXVr9mzXtDRMab8NvzHa1IiYDCBZJthqSy+NU84mQVWz1wnPgte5p15g3ugA9TSh3qVA4qVHfgtXhNJTGuPzP6+muD8XDUrJFG+fgUcI145yWuGQpHOx7Ucjxg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750688015; c=relaxed/simple; bh=nnOyW0JW8EJEA8pgfn3slGtbrEbBbynzfUbyNYYae5o=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ayUP37oqGqQaICCFXO2pq06gIRc2X6oqYAxj9sWgN9Q4Jh3lfakRmfKZ9M+3QO4BAKarQ3fK5OcmS14dld3b34vjAbVFNDHX7DlOn4CFNvDwOCJF5tzBTZXAyFhXGxxFpzWS/psuxNQLi0RxipVAvxLYhhVBW/2PDh3l3mc89ek= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=Fnz5H5j2; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Fnz5H5j2" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 55NEDSp21572760; Mon, 23 Jun 2025 09:13:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1750688008; bh=sbYIPEArgEjkhtMURHidg8ZEr50Ni3vsZ4/42HdWJTs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Fnz5H5j2zI7SdKPtnPbkM9GCjc+F5svU5yBSka91Ffjq/Dv0CCEALDD8GeFxnGkkd H49Kb2SqkfhHAUm5AtFmcOkbLLY7Gggo1gh5qEXcLUTOv9BRdbjQzZGPkLJos4lCDI YTiqgsPMq329LJkwWKg6hMKTEfXgWc/sRcQYcueI= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 55NEDSKY574346 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 23 Jun 2025 09:13:28 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 23 Jun 2025 09:13:27 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 23 Jun 2025 09:13:27 -0500 Received: from localhost (ula0502350.dhcp.ti.com [172.24.227.38]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 55NEDQC4050246; Mon, 23 Jun 2025 09:13:27 -0500 From: Paresh Bhagat To: , , CC: , , , , , , , , , , , Subject: [PATCHv4 2/6] dt-bindings: arm: ti: Add bindings for AM62D2 SoC Date: Mon, 23 Jun 2025 19:42:49 +0530 Message-ID: <20250623141253.3519546-3-p-bhagat@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250623141253.3519546-1-p-bhagat@ti.com> References: <20250623141253.3519546-1-p-bhagat@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The AM62D2 SoC belongs to the K3 Multicore SoC architecture with DSP core targeted for applications needing high-performance Digital Signal Processing. It is used in applications like automotive audio systems, professional sound equipment, radar and radio for aerospace, sonar in marine devices, and ultrasound in medical imaging. It also supports precise signal analysis in test and measurement tools. Some highlights of AM62D2 SoC are: * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Dual/Single core variants are provided in the same package to allow HW compatible designs. * One Device manager Cortex-R5F for system power and resource management, and one Cortex-R5F for Functional Safety or general-purpose usage. * DSP with Matrix Multiplication Accelerator(MMA) (up to 2 TOPS) based on single core C7x. * 3x Multichannel Audio Serial Ports (McASP) Up to 4/6/16 Serial Data Pins which can Transmit and Receive Clocks up to 50MHz, with multi-channel I2S and TDM Audio inputs and outputs. * Integrated Giga-bit Ethernet switch supporting up to a total of two external ports with TSN capable to enable audio networking features such as, Ethernet Audio Video Bridging (eAVB) and Dante. * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, OSPI memory controller, 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. * Dedicated Centralized Hardware Security Module with support for secure boot, debug security and crypto acceleration and trusted execution environment. * One 32 bit DDR Subsystem that supports LPDDR4, DDR4 memory types. * Low power mode support: Partial IO support for CAN/GPIO/UART wakeup. This SoC is of part K3 AM62x family, which includes the AM62A and AM62P variants. While the AM62A and AM62D are largely similar, the AM62D is specifically targeted for general-purpose DSP applications, whereas the AM62A focuses on edge AI workloads. A key distinction is that the AM62D does not include multimedia components such as the video encoder/decoder, MJPEG encoder, Vision Processing Accelerator (VPAC) for image signal processing, or the display subsystem. Additionally, the AM62D has a different pin configuration compared to the AM62A, which impacts embedded software development. This adds dt bindings for TI's AM62D2 family of devices. More details about the SoCs can be found in the Technical Reference Manual: https://www.ti.com/lit/pdf/sprujd4 Signed-off-by: Paresh Bhagat --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentati= on/devicetree/bindings/arm/ti/k3.yaml index bf6003d8fb76..e80c653fa438 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -25,6 +25,12 @@ properties: - ti,am62a7-sk - const: ti,am62a7 =20 + - description: K3 AM62D2 SoC and Boards + items: + - enum: + - ti,am62d2-evm + - const: ti,am62d2 + - description: K3 AM62A7 SoC PHYTEC phyBOARD-Lyra items: - const: phytec,am62a7-phyboard-lyra-rdk --=20 2.34.1