From nobody Wed Oct 8 23:48:13 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0F2424EAAA for ; Mon, 23 Jun 2025 12:03:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750680202; cv=none; b=htZ2nmMGLozX16ddhGZr+nIjwgrwf+pYP74AQWPGk4Ut1ix19mqpBroBl3sBAdYa/iAEsrsK2nDf/J+sBktFZGuPjxWcvQYjlYiBINjp9yP+vTknU39vyAoVDHueKB88xi6nJxqkkh0jhmlQKRK6sa+aPrFU6rnk792s8iqTndw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750680202; c=relaxed/simple; bh=tOpD5LTV/P8tm/1UAfOVh6bSUSeBFltYVVD8Ct+QpFM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PIThLRMcK63OASPJyI/lPd4swVYAylpxCMQcln+V3jKTqlrKytZTa4kjADT4ngaer2FFaSxGXZ6HTxir274oThoG2SqlHWyCSnjo6W1PYTX4YWhYDGK59cFjUDuBnCLB1HTUL4VAe5KUuVpCUxDM8R4mgXdBezsU/3TrY88Ufag= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=BPXElbYC; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="BPXElbYC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1750680199; bh=tOpD5LTV/P8tm/1UAfOVh6bSUSeBFltYVVD8Ct+QpFM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BPXElbYC3D6vKdJHilYWDaXvnIxCXG/COLTXYBdOwULJ+hNDORKb4FIgpddGRpDwX G4gMXKXSMZKCANDv1FP45YLB5LljbXixmNAY4MjBIEdpAsKPSW3aTIf0XKqx8dpF9Z bsktZbufErjX3MZOPqYvOZWpb+Eq/+FlMPefUFFnMKBR8yoHisN8zgiCLita9zI36G UNGlL480/C50S3vhdawEvIk/cs6G4Z48/do0+Qs2q85T1nc9Hl1D/O/0JmLoSdixEB E+NHGAkXRUPfQCrpOL1axLY6MVUcKdlt3NPBouzbQkVA3suCVjTkHNK8FZa5SisHru XdvCDRxe4QRrw== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id C3B1C17E0EC0; Mon, 23 Jun 2025 14:03:18 +0200 (CEST) From: AngeloGioacchino Del Regno To: chunfeng.yun@mediatek.com Cc: vkoul@kernel.org, kishon@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v1 1/2] phy: mediatek: tphy: Clarify and add kerneldoc to mtk_phy_pdata Date: Mon, 23 Jun 2025 14:03:14 +0200 Message-ID: <20250623120315.109881-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250623120315.109881-1-angelogioacchino.delregno@collabora.com> References: <20250623120315.109881-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As struct mtk_phy_pdata was almost fully documented, transfer the comments into kerneldoc on top. While at it, also rewrite the comments to both improve the writing writing and the actual information in the documentation, and add a description for the `version` member of the structure. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Neil Armstrong --- drivers/phy/mediatek/phy-mtk-tphy.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy= -mtk-tphy.c index 644a34bd2b0b..858824b4476e 100644 --- a/drivers/phy/mediatek/phy-mtk-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-tphy.c @@ -277,19 +277,19 @@ enum mtk_phy_version { MTK_PHY_V3, }; =20 +/** + * mtk_phy_pdata - SoC specific platform data + * @avoid_rx_sen_degradation: Avoid TX Sensitivity level degradation (MT67= 95/8173 only) + * @sw_pll_48m_to_26m: Workaround for V3 IP (MT8195) - switch the 4= 8MHz PLL from + * fractional mode to integer to output 26MHz f= or U2PHY + * @sw_efuse_supported: Switches off eFuse auto-load from PHY and ap= plies values + * read from different nvmem (usually different= eFuse array) + * that is pointed at in the device tree node f= or this PHY + * @version: PHY IP Version + */ struct mtk_phy_pdata { - /* avoid RX sensitivity level degradation only for mt8173 */ bool avoid_rx_sen_degradation; - /* - * workaround only for mt8195, HW fix it for others of V3, - * u2phy should use integer mode instead of fractional mode of - * 48M PLL, fix it by switching PLL to 26M from default 48M - */ bool sw_pll_48m_to_26m; - /* - * Some SoCs (e.g. mt8195) drop a bit when use auto load efuse, - * support sw way, also support it for v2/v3 optionally. - */ bool sw_efuse_supported; enum mtk_phy_version version; }; --=20 2.49.0 From nobody Wed Oct 8 23:48:13 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD1C8246793 for ; Mon, 23 Jun 2025 12:03:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750680203; cv=none; b=oYABz28Ryadw8aoCDFlGMtsYkqGzvlYmfNHcQ8kiRDRqJK1t28KK5SqT27Y7wtBzcfbbB/dyByQfOkuXwlTpPKUiomi4S9YMLasDLVwtKavJFOLD6G8lE2df81yOGLVFrNJp6Rlr+Jbxb6ynPILpfmySU07ijBPJK+chJ/c9f7c= ARC-Message-Signature: i=1; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1750680200; bh=Kep1UgV29OPQ4w66WpWqd9vnrdD0pGwhoXX2kcCncG8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BUzmfupdU6G5IRchHGNXcuAebw5hxhpDacHOT/DWgyEzLViO9xtUWxUcQ+gP9b8uF ndeIDVomCTwt6eJ+5DcV/s10pqt3z38Hy4XUGciZ7PVOps0f3jazLLIwHIenfzt2r/ rtBLwhk2HcASt+uzC36u8Iii2WbuCPFfehLLp32R5HDZgZHleS0E6cF1iiCpdTHil1 eH5qfPRptEesQLj7FLzqou88V6ruGw4bXvT8ld4uNnSg0MqVjQ68ZctKMRtLaTDmsV 12svNUv9f9nuWa40CUPMRd/dKLDIYuwDuTrPNmdj4w+taFBIMo+X6Bxptg5PEbaU0h 6hHD95Wu/jwnw== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 9107417E10D5; Mon, 23 Jun 2025 14:03:19 +0200 (CEST) From: AngeloGioacchino Del Regno To: chunfeng.yun@mediatek.com Cc: vkoul@kernel.org, kishon@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v1 2/2] phy: mediatek: tphy: Cleanup and document slew calibration Date: Mon, 23 Jun 2025 14:03:15 +0200 Message-ID: <20250623120315.109881-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250623120315.109881-1-angelogioacchino.delregno@collabora.com> References: <20250623120315.109881-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" While it's true that, generally, the T-PHY V3 does not support the slew calibration process, some minor versions of it actually do, moreover, some SoCs may not support this even though the version of the PHY IP does. The reference clock and rate coefficient parameters are used only for slew calibration: move those to platform data, then document and change the checks in hs_slew_rate_calibrate() to perform the calibration only if: - EYE value was not supplied (pre-calculated calibration); and - Slew reference clock value is present (not zero); and - Slew coefficient is present (not zero). Moreover, change the probe function to always check if both the slew reference clock and coefficient properties are present and, if not, assign the value from platform data (which, as reminder, if not added means that it's zero!), instead of checking the PHY IP version. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Neil Armstrong --- drivers/phy/mediatek/phy-mtk-tphy.c | 45 +++++++++++++++++------------ 1 file changed, 27 insertions(+), 18 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy= -mtk-tphy.c index 858824b4476e..e5ce1255d735 100644 --- a/drivers/phy/mediatek/phy-mtk-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-tphy.c @@ -210,8 +210,6 @@ #define P2F_USB_FM_VALID BIT(0) #define P2F_RG_FRCK_EN BIT(8) =20 -#define U3P_REF_CLK 26 /* MHZ */ -#define U3P_SLEW_RATE_COEF 28 #define U3P_SR_COEF_DIVISOR 1000 #define U3P_FM_DET_CYCLE_CNT 1024 =20 @@ -285,12 +283,16 @@ enum mtk_phy_version { * @sw_efuse_supported: Switches off eFuse auto-load from PHY and ap= plies values * read from different nvmem (usually different= eFuse array) * that is pointed at in the device tree node f= or this PHY + * @slew_ref_clk_mhz: Default reference clock (in MHz) for slew ra= te calibration + * @slew_rate_coefficient: Coefficient for slew rate calibration * @version: PHY IP Version */ struct mtk_phy_pdata { bool avoid_rx_sen_degradation; bool sw_pll_48m_to_26m; bool sw_efuse_supported; + u8 slew_ref_clock_mhz; + u8 slew_rate_coefficient; enum mtk_phy_version version; }; =20 @@ -686,12 +688,14 @@ static void hs_slew_rate_calibrate(struct mtk_tphy *t= phy, int fm_out; u32 tmp; =20 - /* HW V3 doesn't support slew rate cal anymore */ - if (tphy->pdata->version =3D=3D MTK_PHY_V3) - return; - - /* use force value */ - if (instance->eye_src) + /* + * If a fixed HS slew rate (EYE) value was supplied, don't run the + * calibration sequence and prefer using that value instead; also, + * if there is no reference clock for slew calibration or there is + * no slew coefficient, this means that the slew rate calibration + * sequence is not supported. + */ + if (instance->eye_src || !tphy->src_ref_clk || !tphy->src_coef) return; =20 /* enable USB ring oscillator */ @@ -1516,12 +1520,16 @@ static const struct phy_ops mtk_tphy_ops =3D { =20 static const struct mtk_phy_pdata tphy_v1_pdata =3D { .avoid_rx_sen_degradation =3D false, + .slew_ref_clock_mhz =3D 26, + .slew_rate_coefficient =3D 28, .version =3D MTK_PHY_V1, }; =20 static const struct mtk_phy_pdata tphy_v2_pdata =3D { .avoid_rx_sen_degradation =3D false, .sw_efuse_supported =3D true, + .slew_ref_clock_mhz =3D 26, + .slew_rate_coefficient =3D 28, .version =3D MTK_PHY_V2, }; =20 @@ -1532,6 +1540,8 @@ static const struct mtk_phy_pdata tphy_v3_pdata =3D { =20 static const struct mtk_phy_pdata mt8173_pdata =3D { .avoid_rx_sen_degradation =3D true, + .slew_ref_clock_mhz =3D 26, + .slew_rate_coefficient =3D 28, .version =3D MTK_PHY_V1, }; =20 @@ -1561,7 +1571,7 @@ static int mtk_tphy_probe(struct platform_device *pde= v) struct resource *sif_res; struct mtk_tphy *tphy; struct resource res; - int port; + int port, ret; =20 tphy =3D devm_kzalloc(dev, sizeof(*tphy), GFP_KERNEL); if (!tphy) @@ -1591,15 +1601,14 @@ static int mtk_tphy_probe(struct platform_device *p= dev) } } =20 - if (tphy->pdata->version < MTK_PHY_V3) { - tphy->src_ref_clk =3D U3P_REF_CLK; - tphy->src_coef =3D U3P_SLEW_RATE_COEF; - /* update parameters of slew rate calibrate if exist */ - device_property_read_u32(dev, "mediatek,src-ref-clk-mhz", - &tphy->src_ref_clk); - device_property_read_u32(dev, "mediatek,src-coef", - &tphy->src_coef); - } + /* Optional properties for slew calibration variation */ + ret =3D device_property_read_u32(dev, "mediatek,src-ref-clk-mhz", &tphy->= src_ref_clk); + if (ret) + tphy->src_ref_clk =3D tphy->pdata->slew_ref_clock_mhz; + + ret =3D device_property_read_u32(dev, "mediatek,src-coef", &tphy->src_coe= f); + if (ret) + tphy->src_coef =3D tphy->pdata->slew_rate_coefficient; =20 port =3D 0; for_each_child_of_node_scoped(np, child_np) { --=20 2.49.0