From nobody Wed Oct 8 23:48:12 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2D89248F41; Mon, 23 Jun 2025 12:01:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750680087; cv=none; b=WUydXwaxJKHVRv9GumMiIwrPa/ZDph8lZqkZiREzUh+vZYd1lk8mLrw8Lvh0EZQTLKieVh5griWao3VXlBcCcHpwdwTpO3urssPoj9PyQDP3cyu3VRpZMZz/rBvbiWKCCDwJnkHGaQxjxxc8x82O9rwgekqm7kCplzuGoFImENI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750680087; c=relaxed/simple; bh=vL7vsZnHZXjhrnXm1+pOHRiqQJaLYZAMfyW8Ay4L6Ug=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NDS2BJ72v8QetL38IbgLzH9WBoY0XchEd6zbTkOrtNWMvBJidGerA9pYn651yq5Q7mBudDKyTVqRpMX+Vjq0dV/G7QAyLgo8/Ofl7QjQvQSZulom34Ogjsz5I6RkRjD53KqvJk4I+YZ4IrGYiC8+LuebEebN6S2bDpEx7FrXJOI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=R+nrE6pT; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="R+nrE6pT" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1750680083; bh=vL7vsZnHZXjhrnXm1+pOHRiqQJaLYZAMfyW8Ay4L6Ug=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=R+nrE6pTnZW3Qec8oxp/sYkd8N6AQksyP99/7xe66jIVWPB6+vD3CPyw5zJ+LCMWC 2DpRHq+OVAJs1OdyJBDq+d1HjXTPTR8mOaFslfe3q4W8JbFdVoU1SVUhZIRV3hlAYt XnFF/Cm30MTtDQeeQpIKAEs9HmT3jr8bjy2SqLIaXCdBwSQlhaW8sT+LSBgiCtQTh6 ogDiGa0qt3mP4A+urCPeVammDnVLwCHbuXxhdjcGHuai9yv+HDLSH9LVLQoWk0Th2d TUjDOFFDxn3B9iy7blvaNEEuD3GDwarTsn6qTb1Yi5Cswb32+N86J4069+GAqzTzjv He0XDdaljhutA== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 374A017E10D5; Mon, 23 Jun 2025 14:01:23 +0200 (CEST) From: AngeloGioacchino Del Regno To: ukleinek@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, john@phrozen.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com Subject: [PATCH v1 1/3] dt-bindings: pwm: mediatek,mt2712-pwm: Add support for MT6991/MT8196 Date: Mon, 23 Jun 2025 14:01:16 +0200 Message-ID: <20250623120118.109170-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250623120118.109170-1-angelogioacchino.delregno@collabora.com> References: <20250623120118.109170-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible strings for the MediaTek Dimensity 9400 MT6991 and for the MT8196 Chromebook SoC, having the same PWM IP v3.0.2. Signed-off-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml= b/Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml index d515c09e1021..fc31758a40b0 100644 --- a/Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml @@ -18,6 +18,7 @@ properties: - enum: - mediatek,mt2712-pwm - mediatek,mt6795-pwm + - mediatek,mt6991-pwm - mediatek,mt7622-pwm - mediatek,mt7623-pwm - mediatek,mt7628-pwm @@ -32,6 +33,10 @@ properties: - enum: - mediatek,mt8195-pwm - const: mediatek,mt8183-pwm + - items: + - enum: + - mediatek,mt8196-pwm + - const: mediatek,mt6991-pwm =20 reg: maxItems: 1 --=20 2.49.0 From nobody Wed Oct 8 23:48:12 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32918248F56; Mon, 23 Jun 2025 12:01:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750680088; cv=none; b=u2sqMnNIY8FuGkLc2Twst1yjnGOCdGbT5QRh3TE5Obed10aHBHUuDZJ5NGeW+sXp2D/mGZKEK2gJojJkPwFQwTo0mqa0Op1dwfyPnSiYwYXO7Vkhy8ZOx3rOa9VmsQvG7xWFJAHeG9T1zgZj5IF39aphnzJ0HssMWqoYPRElNvo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750680088; c=relaxed/simple; bh=jSa1CeNENoFw2VoytQdb/vKwJWtYXw3LRI1EfB29zsk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tU94inUH3Jh7D6sVqfyjPOyq83kQgNA/UPJAQNmPyJN1qZ077IyGG8Tw6I437+YKuqO7k9DvQbY3TnPd//pzPvZFWLpX4kBbv+VDWg742pcikvWl7FvsQb2dK5fiXtXipA8Myr85+2CK4UbKD8rh7hnscrh9eLscsn2MXJq0f90= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=Hz+rDVLF; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="Hz+rDVLF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1750680084; bh=jSa1CeNENoFw2VoytQdb/vKwJWtYXw3LRI1EfB29zsk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Hz+rDVLFYVk9aesmFoK7AUvOnSCgSNGelPgUL8KirXBzeGKQK7/JpbImOKHbqeWYo Qq4/+fNuG46SUyxlpO8zc0obuD6adi2PIdw3kNLsEojIVs/jowOIUANu6vAvX3/16/ VEH1KxQ0Z2Iq0vzIqEXCDLoVSjV+0gTCNlwbGSnhTQrY3p5YO2IUeQACD69olNEwtX Hlyib3bfzTt185zoixW9BnDXDSAOKX2C6Cp8mFrWOKgRzTMnhyZLHAWaoL00jJvVZI SmUjkSpS3kJ8Tc2PSZwKm3JQ0QmQmJTCogdeZTceX+efIdKjEKWXyRNfDWJMjU3rGB wQHn3WINjsOEA== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 10E8717E090E; Mon, 23 Jun 2025 14:01:24 +0200 (CEST) From: AngeloGioacchino Del Regno To: ukleinek@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, john@phrozen.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com Subject: [PATCH v1 2/3] pwm: pwm-mediatek: Pass PWM_CK_26M_SEL from platform data Date: Mon, 23 Jun 2025 14:01:17 +0200 Message-ID: <20250623120118.109170-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250623120118.109170-1-angelogioacchino.delregno@collabora.com> References: <20250623120118.109170-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for adding support for new SoCs, remove variable has_ck_26m_sel from pwm_mediatek_of_data and replace it with a u16 pwm_ck_26m_sel_reg, meant to hold the register offset for PWM_CK_26M_SEL. Also, since the reg offset is guaranteed to never be zero, the logic to check for "has_ck_26m_sel" is changed to check if the register offset in pwm_ck_26m_sel_reg is more than zero. Analogously, when writing, use the register offset from platform data instead of using the PWM_CK_26M_SEL definition. Signed-off-by: AngeloGioacchino Del Regno --- drivers/pwm/pwm-mediatek.c | 24 +++++++++--------------- 1 file changed, 9 insertions(+), 15 deletions(-) diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index 7eaab5831499..38e9e9dc91c6 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c @@ -36,7 +36,7 @@ struct pwm_mediatek_of_data { unsigned int num_pwms; bool pwm45_fixup; - bool has_ck_26m_sel; + u16 pwm_ck_26m_sel_reg; const unsigned int *reg_offset; }; =20 @@ -134,8 +134,8 @@ static int pwm_mediatek_config(struct pwm_chip *chip, s= truct pwm_device *pwm, return -EINVAL; =20 /* Make sure we use the bus clock and not the 26MHz clock */ - if (pc->soc->has_ck_26m_sel) - writel(0, pc->regs + PWM_CK_26M_SEL); + if (pc->soc->pwm_ck_26m_sel_reg) + writel(0, pc->regs + pc->soc->pwm_ck_26m_sel_reg); =20 /* Using resolution in picosecond gets accuracy higher */ resolution =3D (u64)NSEC_PER_SEC * 1000; @@ -291,84 +291,78 @@ static int pwm_mediatek_probe(struct platform_device = *pdev) static const struct pwm_mediatek_of_data mt2712_pwm_data =3D { .num_pwms =3D 8, .pwm45_fixup =3D false, - .has_ck_26m_sel =3D false, .reg_offset =3D mtk_pwm_reg_offset_v1, }; =20 static const struct pwm_mediatek_of_data mt6795_pwm_data =3D { .num_pwms =3D 7, .pwm45_fixup =3D false, - .has_ck_26m_sel =3D false, .reg_offset =3D mtk_pwm_reg_offset_v1, }; =20 static const struct pwm_mediatek_of_data mt7622_pwm_data =3D { .num_pwms =3D 6, .pwm45_fixup =3D false, - .has_ck_26m_sel =3D true, + .pwm_ck_26m_sel_reg =3D PWM_CK_26M_SEL, .reg_offset =3D mtk_pwm_reg_offset_v1, }; =20 static const struct pwm_mediatek_of_data mt7623_pwm_data =3D { .num_pwms =3D 5, .pwm45_fixup =3D true, - .has_ck_26m_sel =3D false, .reg_offset =3D mtk_pwm_reg_offset_v1, }; =20 static const struct pwm_mediatek_of_data mt7628_pwm_data =3D { .num_pwms =3D 4, .pwm45_fixup =3D true, - .has_ck_26m_sel =3D false, .reg_offset =3D mtk_pwm_reg_offset_v1, }; =20 static const struct pwm_mediatek_of_data mt7629_pwm_data =3D { .num_pwms =3D 1, .pwm45_fixup =3D false, - .has_ck_26m_sel =3D false, .reg_offset =3D mtk_pwm_reg_offset_v1, }; =20 static const struct pwm_mediatek_of_data mt7981_pwm_data =3D { .num_pwms =3D 3, .pwm45_fixup =3D false, - .has_ck_26m_sel =3D true, + .pwm_ck_26m_sel_reg =3D PWM_CK_26M_SEL, .reg_offset =3D mtk_pwm_reg_offset_v2, }; =20 static const struct pwm_mediatek_of_data mt7986_pwm_data =3D { .num_pwms =3D 2, .pwm45_fixup =3D false, - .has_ck_26m_sel =3D true, + .pwm_ck_26m_sel_reg =3D PWM_CK_26M_SEL, .reg_offset =3D mtk_pwm_reg_offset_v1, }; =20 static const struct pwm_mediatek_of_data mt7988_pwm_data =3D { .num_pwms =3D 8, .pwm45_fixup =3D false, - .has_ck_26m_sel =3D false, .reg_offset =3D mtk_pwm_reg_offset_v2, }; =20 static const struct pwm_mediatek_of_data mt8183_pwm_data =3D { .num_pwms =3D 4, .pwm45_fixup =3D false, - .has_ck_26m_sel =3D true, + .pwm_ck_26m_sel_reg =3D PWM_CK_26M_SEL, .reg_offset =3D mtk_pwm_reg_offset_v1, }; =20 static const struct pwm_mediatek_of_data mt8365_pwm_data =3D { .num_pwms =3D 3, .pwm45_fixup =3D false, - .has_ck_26m_sel =3D true, + .pwm_ck_26m_sel_reg =3D PWM_CK_26M_SEL, .reg_offset =3D mtk_pwm_reg_offset_v1, }; =20 static const struct pwm_mediatek_of_data mt8516_pwm_data =3D { .num_pwms =3D 5, .pwm45_fixup =3D false, - .has_ck_26m_sel =3D true, + .pwm_ck_26m_sel_reg =3D PWM_CK_26M_SEL, .reg_offset =3D mtk_pwm_reg_offset_v1, }; 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Mon, 23 Jun 2025 14:01:24 +0200 (CEST) From: AngeloGioacchino Del Regno To: ukleinek@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, john@phrozen.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com Subject: [PATCH v1 3/3] pwm: pwm-mediatek: Add support for PWM IP V3.0.2 in MT6991/MT8196 Date: Mon, 23 Jun 2025 14:01:18 +0200 Message-ID: <20250623120118.109170-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250623120118.109170-1-angelogioacchino.delregno@collabora.com> References: <20250623120118.109170-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the PWM IP version 3.0.2, found in MediaTek's Dimensity 9400 MT6991 and in the MT8196 Chromebook SoC: this needs a new register offset array and also a different offset for the PWM_CK_26M_SEL register. Signed-off-by: AngeloGioacchino Del Regno --- drivers/pwm/pwm-mediatek.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index 38e9e9dc91c6..1fbc84d47543 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c @@ -29,6 +29,7 @@ #define PWM45DWIDTH_FIXUP 0x30 #define PWMTHRES 0x30 #define PWM45THRES_FIXUP 0x34 +#define PWM_CK_26M_SEL_V3 0x74 #define PWM_CK_26M_SEL 0x210 =20 #define PWM_CLK_DIV_MAX 7 @@ -64,6 +65,11 @@ static const unsigned int mtk_pwm_reg_offset_v2[] =3D { 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240 }; =20 +/* PWM IP Version 3.0.2 */ +static const unsigned int mtk_pwm_reg_offset_v3[] =3D { + 0x0100, 0x0200, 0x0300, 0x0400, 0x0500, 0x0600, 0x0700, 0x0800 +}; + static inline struct pwm_mediatek_chip * to_pwm_mediatek_chip(struct pwm_chip *chip) { @@ -366,9 +372,17 @@ static const struct pwm_mediatek_of_data mt8516_pwm_da= ta =3D { .reg_offset =3D mtk_pwm_reg_offset_v1, }; =20 +static const struct pwm_mediatek_of_data mt6991_pwm_data =3D { + .num_pwms =3D 4, + .pwm45_fixup =3D false, + .pwm_ck_26m_sel_reg =3D PWM_CK_26M_SEL_V3, + .reg_offset =3D mtk_pwm_reg_offset_v3, +}; + static const struct of_device_id pwm_mediatek_of_match[] =3D { { .compatible =3D "mediatek,mt2712-pwm", .data =3D &mt2712_pwm_data }, { .compatible =3D "mediatek,mt6795-pwm", .data =3D &mt6795_pwm_data }, + { .compatible =3D "mediatek,mt6991-pwm", .data =3D &mt6991_pwm_data }, { .compatible =3D "mediatek,mt7622-pwm", .data =3D &mt7622_pwm_data }, { .compatible =3D "mediatek,mt7623-pwm", .data =3D &mt7623_pwm_data }, { .compatible =3D "mediatek,mt7628-pwm", .data =3D &mt7628_pwm_data }, --=20 2.49.0