From nobody Thu Oct 9 01:13:14 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BCC2D255F53; Mon, 23 Jun 2025 12:00:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750680055; cv=none; b=JVoka/xYvoG4tNG3FZ1OkkbNBLgvoeOER3pb9vHCwAidrSnq0lr99aTYt2Ke5QkMJPHYUJy3OZXVJ/Q3wH1HEKCXraljmH6vU+BVD7klIVWFt4/ufcGu976bHP5FWHP33fpo5RybN/84gGG+U5t/UD4kCzf7h4Zg1Jic1tv3jaE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750680055; c=relaxed/simple; bh=7i4gj4FLic9Db/zKjHzbibMfS0LjHs3CHldwZgnqQRM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mXE4jKM2CY/bLX9ppinw42HeVcizwZvHd2gDOLbf05tes3GYFJo/54s2FI9Pi04JsQhQY2DDb9+3cZwYm56yUTpJRyV88eeQsFfzs5uyIVhDIM4zScWr8WmMsHQefO6cDX3vmLkqnVukYuwarSSoEJrO5U7qhxI8qQVE69WQLG0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=eK1+ppPb; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="eK1+ppPb" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1750680052; bh=7i4gj4FLic9Db/zKjHzbibMfS0LjHs3CHldwZgnqQRM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eK1+ppPb3x94K3iNJno2UtDG+eL+a33xnoHqwao4b0D/2aGSazdFf6I/ldqKfxrz5 6cEBZReRY7QBLfaWzdYG3Y/ZbwO0PY11g6JU0qitLS/2WFzfom+QbuTIn7LrGTreHo 47W73vPrAnnPuu4ZwkMHJ+Q+h83Vvz/Fb6DPIPeFC6Rj7a64K63yu3R+a08FVZQKfO s2l4K7KZIZDEJmQMEBd+pGpTGev+fK+ZOp55MedawQH9ixipZ7uaO9zJV4OUdr0JKm Ei/Wvj2aTHFeRED4Gye0zVy4gP7MCJ8jedtHfAESU34tvL+QydLiENcETqeRjWUcfZ WhPwJ6spgaOmg== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 97E1417E0EC0; Mon, 23 Jun 2025 14:00:51 +0200 (CEST) From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, hsin-hsiung.wang@mediatek.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com Subject: [PATCH v1 1/5] dt-bindings: spmi: Add MediaTek MT8196 SPMI 2 Arbiter/Controllers Date: Mon, 23 Jun 2025 14:00:43 +0200 Message-ID: <20250623120047.108961-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250623120047.108961-1-angelogioacchino.delregno@collabora.com> References: <20250623120047.108961-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the MT8196 SPMI 2.0 Controller with a new schema. This is a MIPI SPMI 2.0 compliant IP, composed of a main arbiter and two SPMI master controllers with Request Capable Slave (RCS) support. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring (Arm) --- .../bindings/spmi/mediatek,mt8196-spmi.yaml | 138 ++++++++++++++++++ 1 file changed, 138 insertions(+) create mode 100644 Documentation/devicetree/bindings/spmi/mediatek,mt8196-= spmi.yaml diff --git a/Documentation/devicetree/bindings/spmi/mediatek,mt8196-spmi.ya= ml b/Documentation/devicetree/bindings/spmi/mediatek,mt8196-spmi.yaml new file mode 100644 index 000000000000..d7eb63e81a5c --- /dev/null +++ b/Documentation/devicetree/bindings/spmi/mediatek,mt8196-spmi.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spmi/mediatek,mt8196-spmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8196 SPMI 2.0 Controller + +maintainers: + - Hsin-Hsiung Wang + - AngeloGioacchino Del Regno + +description: + The MediaTek MT8196 SoC features a SPMI version 2.0 compliant controller, + with internal wrapping arbitration logic to allow for multiple on-chip + devices to control up to two SPMI buses. + The main arbiter also acts as an interrupt controller, arbitering also + the interrupts coming from SPMI-connected devices into each of the nested + interrupt controllers from any of the present SPMI buses. + +properties: + compatible: + oneOf: + - enum: + - mediatek,mt8196-spmi + - items: + - enum: + - mediatek,mt6991-spmi + - const: mediatek,mt8196-spmi + + ranges: true + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + +patternProperties: + "^spmi@[a-f0-9]+$": + type: object + $ref: /schemas/spmi/spmi.yaml + unevaluatedProperties: false + + properties: + reg: + items: + - description: controller interface registers + - description: spmi master controller registers + + reg-names: + items: + - const: pmif + - const: spmimst + + clocks: + items: + - description: controller interface system clock + - description: controller interface timer clock + - description: spmi controller master clock + + clock-names: + items: + - const: pmif_sys_ck + - const: pmif_tmr_ck + - const: spmimst_clk_mux + + interrupts: + maxItems: 1 + + interrupt-names: + const: rcs + + interrupt-controller: true + + "#interrupt-cells": + const: 3 + description: | + cell 1: slave ID for the requested interrupt (0-15) + cell 2: the requested peripheral interrupt (0-7) + cell 3: interrupt flags indicating level-sense information, + as defined in dt-bindings/interrupt-controller/irq.h + required: + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interrupt-controller + - "#interrupt-cells" + +required: + - compatible + - ranges + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +examples: + - | + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + spmi-arbiter@1c018000 { + compatible =3D "mediatek,mt8196-spmi"; + ranges =3D <0 0 0x1c018000 0x4900>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + spmi@0 { + reg =3D <0 0x900>, <0x4800 0x100>; + reg-names =3D "pmif", "spmimst"; + interrupts-extended =3D <&pio 292 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "rcs"; + interrupt-controller; + #interrupt-cells =3D <3>; + clocks =3D <&pmif_sys>, <&pmif_tmr>, <&spmi_mst>; + clock-names =3D "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; + }; + + spmi@2000 { + reg =3D <0x2000 0x900>, <0x4000 0x100>; + reg-names =3D "pmif", "spmimst"; + interrupts-extended =3D <&pio 291 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "rcs"; + interrupt-controller; + #interrupt-cells =3D <3>; + clocks =3D <&pmif_sys>, <&pmif_tmr>, <&spmi_mst>; + clock-names =3D "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; + }; + }; + }; +... --=20 2.49.0