From nobody Wed Oct 8 23:45:37 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33D2B24BC1A; Mon, 23 Jun 2025 12:00:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750680037; cv=none; b=pkkRelrqG/cIlWFdUYaQ/XBkqXUltMZsX4iLZT/VDLgEaQjWrfikbiyA5RH6zynn5AZWNhIxjdPJlF/MpcxWM8M/8J63uuY7QNkLELCYmVhUJF9w6q6YfbmExA1XUBWWBeEZTsaNrZiCZuY7EwqurMDHj2dV/pPu6lazDY6WNd0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750680037; c=relaxed/simple; bh=CZEgYbfBy7FB1rq1F534XxN+O0ZjjDodFZAWk6TJxVM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gfsdRbR5HuTHTsTiKgwRZUTJ7OLCS9cqxilW6hkqLzQVx7Z3ZSyXhFT92u3YuwR5BYD2LEPnMLVCziMgkoU1ifssY23f06EWSVyoYqtYNAcbOUtsn7/eXie06UTUPh6tJOMfEDcPyaLMdWp/NTrV0+webGH7JQnbeaV1aGQgAyA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=K6IXMrno; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="K6IXMrno" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1750680033; bh=CZEgYbfBy7FB1rq1F534XxN+O0ZjjDodFZAWk6TJxVM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=K6IXMrnots+VxqoED35PFiKhotry7PESAi9bWxLFA7wECQLtuHZ4I47xjfRE2H9m3 PqNb512qcE8XGkmN9k8KtjekgpZ2ya+f/yYM2MjsI71B4loE9GKIcQauNsBW9/APqR DdCFR9gXlUBbMFVeybJm1/aTUflm3xjCWIUGY6szaGaFGrGTq8TrNr19ODCZXzSNR+ pPgI4y7K+XcRRBlAO7CmJCSKtKYFfgh3fv8iRceMoeDfG8Agz3ryhivQqocKHPYB/e BL6Lu/kUijIo8dawgMdPQ7AQUqnMa9XCFkOcH2c9wIKskZeeIyBsTF/h/RIOb/thkL OOgj2qnEbC8Vg== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id BD6AB17E05BD; Mon, 23 Jun 2025 14:00:32 +0200 (CEST) From: AngeloGioacchino Del Regno To: jic23@kernel.org Cc: dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com Subject: [PATCH v1 1/5] dt-bindings: iio: adc: mt6359: Add bindings for MT6363 PMIC AuxADC Date: Mon, 23 Jun 2025 14:00:24 +0200 Message-ID: <20250623120028.108809-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250623120028.108809-1-angelogioacchino.delregno@collabora.com> References: <20250623120028.108809-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a compatible and channel bindings for MediaTek's MT6363 PMIC, featuring an Auxiliary ADC IP with 15 ADC channels used for both internal temperatures and voltages and for external voltage inputs. Signed-off-by: AngeloGioacchino Del Regno Acked-by: Rob Herring (Arm) Reviewed-by: N=C3=ADcolas F. R. A. Prado --- .../iio/adc/mediatek,mt6359-auxadc.yaml | 1 + .../iio/adc/mediatek,mt6363-auxadc.h | 24 +++++++++++++++++++ 2 files changed, 25 insertions(+) create mode 100644 include/dt-bindings/iio/adc/mediatek,mt6363-auxadc.h diff --git a/Documentation/devicetree/bindings/iio/adc/mediatek,mt6359-auxa= dc.yaml b/Documentation/devicetree/bindings/iio/adc/mediatek,mt6359-auxadc.= yaml index 6497c416094d..a94429477e46 100644 --- a/Documentation/devicetree/bindings/iio/adc/mediatek,mt6359-auxadc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/mediatek,mt6359-auxadc.yaml @@ -22,6 +22,7 @@ properties: - mediatek,mt6357-auxadc - mediatek,mt6358-auxadc - mediatek,mt6359-auxadc + - mediatek,mt6363-auxadc =20 "#io-channel-cells": const: 1 diff --git a/include/dt-bindings/iio/adc/mediatek,mt6363-auxadc.h b/include= /dt-bindings/iio/adc/mediatek,mt6363-auxadc.h new file mode 100644 index 000000000000..92d135477d0e --- /dev/null +++ b/include/dt-bindings/iio/adc/mediatek,mt6363-auxadc.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ + +#ifndef _DT_BINDINGS_MEDIATEK_MT6363_AUXADC_H +#define _DT_BINDINGS_MEDIATEK_MT6363_AUXADC_H + +/* ADC Channel Index */ +#define MT6363_AUXADC_BATADC 0 +#define MT6363_AUXADC_VCDT 1 +#define MT6363_AUXADC_BAT_TEMP 2 +#define MT6363_AUXADC_CHIP_TEMP 3 +#define MT6363_AUXADC_VSYSSNS 4 +#define MT6363_AUXADC_VTREF 5 +#define MT6363_AUXADC_VCORE_TEMP 6 +#define MT6363_AUXADC_VPROC_TEMP 7 +#define MT6363_AUXADC_VGPU_TEMP 8 +#define MT6363_AUXADC_VIN1 9 +#define MT6363_AUXADC_VIN2 10 +#define MT6363_AUXADC_VIN3 11 +#define MT6363_AUXADC_VIN4 12 +#define MT6363_AUXADC_VIN5 13 +#define MT6363_AUXADC_VIN6 14 +#define MT6363_AUXADC_VIN7 15 + +#endif --=20 2.49.0 From nobody Wed Oct 8 23:45:37 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3AB4124C060; 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Mon, 23 Jun 2025 14:00:33 +0200 (CEST) From: AngeloGioacchino Del Regno To: jic23@kernel.org Cc: dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com Subject: [PATCH v1 2/5] dt-bindings: iio: adc: mt6359: Add bindings for MT6373 PMIC AuxADC Date: Mon, 23 Jun 2025 14:00:25 +0200 Message-ID: <20250623120028.108809-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250623120028.108809-1-angelogioacchino.delregno@collabora.com> References: <20250623120028.108809-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a compatible and channel bindings for MediaTek's MT6373 PMIC, featuring an Auxiliary ADC IP with 15 ADC channels for external (SoC) temperatures and external voltage inputs. Signed-off-by: AngeloGioacchino Del Regno Acked-by: Rob Herring (Arm) Reviewed-by: N=C3=ADcolas F. R. A. Prado --- .../iio/adc/mediatek,mt6359-auxadc.yaml | 1 + .../iio/adc/mediatek,mt6373-auxadc.h | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 include/dt-bindings/iio/adc/mediatek,mt6373-auxadc.h diff --git a/Documentation/devicetree/bindings/iio/adc/mediatek,mt6359-auxa= dc.yaml b/Documentation/devicetree/bindings/iio/adc/mediatek,mt6359-auxadc.= yaml index a94429477e46..5d4ab701f51a 100644 --- a/Documentation/devicetree/bindings/iio/adc/mediatek,mt6359-auxadc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/mediatek,mt6359-auxadc.yaml @@ -23,6 +23,7 @@ properties: - mediatek,mt6358-auxadc - mediatek,mt6359-auxadc - mediatek,mt6363-auxadc + - mediatek,mt6373-auxadc =20 "#io-channel-cells": const: 1 diff --git a/include/dt-bindings/iio/adc/mediatek,mt6373-auxadc.h b/include= /dt-bindings/iio/adc/mediatek,mt6373-auxadc.h new file mode 100644 index 000000000000..17cab86d355e --- /dev/null +++ b/include/dt-bindings/iio/adc/mediatek,mt6373-auxadc.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ + +#ifndef _DT_BINDINGS_MEDIATEK_MT6373_AUXADC_H +#define _DT_BINDINGS_MEDIATEK_MT6373_AUXADC_H + +/* ADC Channel Index */ +#define MT6373_AUXADC_CHIP_TEMP 0 +#define MT6373_AUXADC_VCORE_TEMP 1 +#define MT6373_AUXADC_VPROC_TEMP 2 +#define MT6373_AUXADC_VGPU_TEMP 3 +#define MT6373_AUXADC_VIN1 4 +#define MT6373_AUXADC_VIN2 5 +#define MT6373_AUXADC_VIN3 6 +#define MT6373_AUXADC_VIN4 7 +#define MT6373_AUXADC_VIN5 8 +#define MT6373_AUXADC_VIN6 9 +#define MT6373_AUXADC_VIN7 10 + +#endif --=20 2.49.0 From nobody Wed Oct 8 23:45:37 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42F3024DCF2; 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Mon, 23 Jun 2025 14:00:34 +0200 (CEST) From: AngeloGioacchino Del Regno To: jic23@kernel.org Cc: dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com Subject: [PATCH v1 3/5] iio: adc: mt6359: Add ready register index and mask to channel data Date: Mon, 23 Jun 2025 14:00:26 +0200 Message-ID: <20250623120028.108809-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250623120028.108809-1-angelogioacchino.delregno@collabora.com> References: <20250623120028.108809-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for adding support for the AUXADC block found in the MT6363 PMIC, add the ready register index and mask to the mtk_pmic_auxadc_chan structure, populate those in the channel description for all of the already supported SoCs and make use of them in the .read_imp() callbacks. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado --- drivers/iio/adc/mt6359-auxadc.c | 118 ++++++++++++++++++-------------- 1 file changed, 65 insertions(+), 53 deletions(-) diff --git a/drivers/iio/adc/mt6359-auxadc.c b/drivers/iio/adc/mt6359-auxad= c.c index eecf88b05c6f..ae7b65f5f551 100644 --- a/drivers/iio/adc/mt6359-auxadc.c +++ b/drivers/iio/adc/mt6359-auxadc.c @@ -101,12 +101,16 @@ struct mt6359_auxadc { * struct mtk_pmic_auxadc_chan - PMIC AUXADC channel data * @req_idx: Request register number * @req_mask: Bitmask to activate a channel + * @rdy_idx: Readiness register number + * @rdy_mask: Bitmask to determine channel readiness * @num_samples: Number of AUXADC samples for averaging * @r_ratio: Resistance ratio fractional */ struct mtk_pmic_auxadc_chan { u8 req_idx; u16 req_mask; + u8 rdy_idx; + u16 rdy_mask; u16 num_samples; struct u8_fract r_ratio; }; @@ -130,13 +134,17 @@ struct mtk_pmic_auxadc_info { const u16 *regs; u16 sec_unlock_key; u8 imp_adc_num; - int (*read_imp)(struct mt6359_auxadc *adc_dev, int *vbat, int *ibat); + int (*read_imp)(struct mt6359_auxadc *adc_dev, + const struct iio_chan_spec *chan, int *vbat, int *ibat); }; =20 -#define MTK_PMIC_ADC_CHAN(_ch_idx, _req_idx, _req_bit, _samples, _rnum, _r= div) \ +#define MTK_PMIC_ADC_CHAN(_ch_idx, _req_idx, _req_bit, _rdy_idx, _rdy_bit,= \ + _samples, _rnum, _rdiv) \ [PMIC_AUXADC_CHAN_##_ch_idx] =3D { \ .req_idx =3D _req_idx, \ .req_mask =3D BIT(_req_bit), \ + .rdy_idx =3D _rdy_idx, \ + .rdy_mask =3D BIT(_rdy_bit), \ .num_samples =3D _samples, \ .r_ratio =3D { _rnum, _rdiv } \ } @@ -177,21 +185,21 @@ static const struct iio_chan_spec mt6357_auxadc_chann= els[] =3D { }; =20 static const struct mtk_pmic_auxadc_chan mt6357_auxadc_ch_desc[] =3D { - MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, 128, 3, 1), - MTK_PMIC_ADC_CHAN(ISENSE, PMIC_AUXADC_RQST0, 0, 128, 3, 1), - MTK_PMIC_ADC_CHAN(VCDT, PMIC_AUXADC_RQST0, 0, 8, 1, 1), - MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, 8, 1, 1), - MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, 8, 1, 1), - MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, 8, 1, 1), - MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, 128, 1, 1), - MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, 256, 1, 1), - MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, 16, 1, 1), - MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, 8, 1, 1), - MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 5, 8, 1, 1), - MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 6, 8, 1, 1), + MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 128,= 3, 1), + MTK_PMIC_ADC_CHAN(ISENSE, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 128,= 3, 1), + MTK_PMIC_ADC_CHAN(VCDT, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 8, 1, = 1), + MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, PMIC_AUXADC_IMP0, 8, 8,= 1, 1), + MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_IMP0, 8, 8= , 1, 1), + MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, PMIC_AUXADC_IMP0, 8, 8, 1= , 1), + MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, PMIC_AUXADC_IMP0, 8, 12= 8, 1, 1), + MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, PMIC_AUXADC_IMP0, 8, 2= 56, 1, 1), + MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, PMIC_AUXADC_IMP0, 8, = 16, 1, 1), + MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, PMIC_AUXADC_IMP0, 8, 8, 1,= 1), + MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 5, PMIC_AUXADC_IMP0, 8, = 8, 1, 1), + MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 6, PMIC_AUXADC_IMP0, 8, = 8, 1, 1), =20 /* Battery impedance channels */ - MTK_PMIC_ADC_CHAN(VBAT, 0, 0, 128, 3, 1), + MTK_PMIC_ADC_CHAN(VBAT, 0, 0, 0, 0, 128, 3, 1), }; =20 static const u16 mt6357_auxadc_regs[] =3D { @@ -224,22 +232,22 @@ static const struct iio_chan_spec mt6358_auxadc_chann= els[] =3D { }; =20 static const struct mtk_pmic_auxadc_chan mt6358_auxadc_ch_desc[] =3D { - MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, 128, 3, 1), - MTK_PMIC_ADC_CHAN(VCDT, PMIC_AUXADC_RQST0, 0, 8, 1, 1), - MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, 8, 2, 1), - MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, 8, 1, 1), - MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, 8, 1, 1), - MTK_PMIC_ADC_CHAN(VDCXO, PMIC_AUXADC_RQST0, 6, 8, 3, 2), - MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, 128, 1, 1), - MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, 256, 1, 1), - MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, 16, 1, 1), - MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, 8, 2, 1), - MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 8, 8, 1, 1), - MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 9, 8, 1, 1), - MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST1, 10, 8, 1, 1), + MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 128,= 3, 1), + MTK_PMIC_ADC_CHAN(VCDT, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 8, 1, = 1), + MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, PMIC_AUXADC_IMP0, 8, 8,= 2, 1), + MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_IMP0, 8, 8= , 1, 1), + MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, PMIC_AUXADC_IMP0, 8, 8, 1= , 1), + MTK_PMIC_ADC_CHAN(VDCXO, PMIC_AUXADC_RQST0, 6, PMIC_AUXADC_IMP0, 8, 8, 3,= 2), + MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, PMIC_AUXADC_IMP0, 8, 12= 8, 1, 1), + MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, PMIC_AUXADC_IMP0, 8, 2= 56, 1, 1), + MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, PMIC_AUXADC_IMP0, 8, = 16, 1, 1), + MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, PMIC_AUXADC_IMP0, 8, 8, 2,= 1), + MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 8, PMIC_AUXADC_IMP0, 8, = 8, 1, 1), + MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 9, PMIC_AUXADC_IMP0, 8, = 8, 1, 1), + MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST1, 10, PMIC_AUXADC_IMP0, 8, = 8, 1, 1), =20 /* Battery impedance channels */ - MTK_PMIC_ADC_CHAN(VBAT, 0, 0, 128, 7, 2), + MTK_PMIC_ADC_CHAN(VBAT, 0, 0, 0, 0, 128, 7, 2), }; =20 static const u16 mt6358_auxadc_regs[] =3D { @@ -272,22 +280,22 @@ static const struct iio_chan_spec mt6359_auxadc_chann= els[] =3D { }; =20 static const struct mtk_pmic_auxadc_chan mt6359_auxadc_ch_desc[] =3D { - MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, 128, 7, 2), - MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, 8, 5, 2), - MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, 8, 1, 1), - MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, 8, 1, 1), - MTK_PMIC_ADC_CHAN(VDCXO, PMIC_AUXADC_RQST0, 6, 8, 3, 2), - MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, 128, 1, 1), - MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, 256, 1, 1), - MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, 16, 1, 1), - MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, 8, 5, 2), - MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 8, 8, 1, 1), - MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 9, 8, 1, 1), - MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST1, 10, 8, 1, 1), + MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP1, 15, 128= , 7, 2), + MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, PMIC_AUXADC_IMP1, 15, 8= , 5, 2), + MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_IMP1, 15, = 8, 1, 1), + MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, PMIC_AUXADC_IMP1, 15 ,8, = 1, 1), + MTK_PMIC_ADC_CHAN(VDCXO, PMIC_AUXADC_RQST0, 6, PMIC_AUXADC_IMP1, 15, 8, 3= , 2), + MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, PMIC_AUXADC_IMP1, 15, 1= 28, 1, 1), + MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, PMIC_AUXADC_IMP1, 15, = 256, 1, 1), + MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, PMIC_AUXADC_IMP1, 15,= 16, 1, 1), + MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, PMIC_AUXADC_IMP1, 15, 8, 5= , 2), + MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 8, PMIC_AUXADC_IMP1, 15,= 8, 1, 1), + MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 9, PMIC_AUXADC_IMP1, 15,= 8, 1, 1), + MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST1, 10, PMIC_AUXADC_IMP1, 15,= 8, 1, 1), =20 /* Battery impedance channels */ - MTK_PMIC_ADC_CHAN(VBAT, 0, 0, 128, 7, 2), - MTK_PMIC_ADC_CHAN(IBAT, 0, 0, 128, 7, 2), + MTK_PMIC_ADC_CHAN(VBAT, 0, 0, 0, 0, 128, 7, 2), + MTK_PMIC_ADC_CHAN(IBAT, 0, 0, 0, 0, 128, 7, 2), }; =20 static const u16 mt6359_auxadc_regs[] =3D { @@ -313,9 +321,10 @@ static void mt6358_stop_imp_conv(struct mt6359_auxadc = *adc_dev) regmap_clear_bits(regmap, cinfo->regs[PMIC_AUXADC_DCM_CON], MT6358_DCM_CK= _SW_EN); } =20 -static int mt6358_start_imp_conv(struct mt6359_auxadc *adc_dev) +static int mt6358_start_imp_conv(struct mt6359_auxadc *adc_dev, const stru= ct iio_chan_spec *chan) { const struct mtk_pmic_auxadc_info *cinfo =3D adc_dev->chip_info; + const struct mtk_pmic_auxadc_chan *desc =3D &cinfo->desc[chan->scan_index= ]; struct regmap *regmap =3D adc_dev->regmap; u32 val; int ret; @@ -323,8 +332,8 @@ static int mt6358_start_imp_conv(struct mt6359_auxadc *= adc_dev) regmap_set_bits(regmap, cinfo->regs[PMIC_AUXADC_DCM_CON], MT6358_DCM_CK_S= W_EN); regmap_set_bits(regmap, cinfo->regs[PMIC_AUXADC_IMP1], MT6358_IMP1_AUTORE= PEAT_EN); =20 - ret =3D regmap_read_poll_timeout(adc_dev->regmap, cinfo->regs[PMIC_AUXADC= _IMP0], - val, val & MT6358_IMP0_IRQ_RDY, + ret =3D regmap_read_poll_timeout(regmap, cinfo->regs[desc->rdy_idx], + val, val & desc->rdy_mask, IMP_POLL_DELAY_US, AUXADC_TIMEOUT_US); if (ret) { mt6358_stop_imp_conv(adc_dev); @@ -334,7 +343,8 @@ static int mt6358_start_imp_conv(struct mt6359_auxadc *= adc_dev) return 0; } =20 -static int mt6358_read_imp(struct mt6359_auxadc *adc_dev, int *vbat, int *= ibat) +static int mt6358_read_imp(struct mt6359_auxadc *adc_dev, + const struct iio_chan_spec *chan, int *vbat, int *ibat) { const struct mtk_pmic_auxadc_info *cinfo =3D adc_dev->chip_info; struct regmap *regmap =3D adc_dev->regmap; @@ -342,7 +352,7 @@ static int mt6358_read_imp(struct mt6359_auxadc *adc_de= v, int *vbat, int *ibat) u32 val_v; int ret; =20 - ret =3D mt6358_start_imp_conv(adc_dev); + ret =3D mt6358_start_imp_conv(adc_dev, chan); if (ret) return ret; =20 @@ -359,17 +369,19 @@ static int mt6358_read_imp(struct mt6359_auxadc *adc_= dev, int *vbat, int *ibat) return 0; } =20 -static int mt6359_read_imp(struct mt6359_auxadc *adc_dev, int *vbat, int *= ibat) +static int mt6359_read_imp(struct mt6359_auxadc *adc_dev, + const struct iio_chan_spec *chan, int *vbat, int *ibat) { const struct mtk_pmic_auxadc_info *cinfo =3D adc_dev->chip_info; + const struct mtk_pmic_auxadc_chan *desc =3D &cinfo->desc[chan->scan_index= ]; struct regmap *regmap =3D adc_dev->regmap; u32 val, val_v, val_i; int ret; =20 /* Start conversion */ regmap_write(regmap, cinfo->regs[PMIC_AUXADC_IMP0], MT6359_IMP0_CONV_EN); - ret =3D regmap_read_poll_timeout(regmap, cinfo->regs[PMIC_AUXADC_IMP1], - val, val & MT6359_IMP1_IRQ_RDY, + ret =3D regmap_read_poll_timeout(regmap, cinfo->regs[desc->rdy_idx], + val, val & desc->rdy_mask, IMP_POLL_DELAY_US, AUXADC_TIMEOUT_US); =20 /* Stop conversion regardless of the result */ @@ -506,10 +518,10 @@ static int mt6359_auxadc_read_raw(struct iio_dev *ind= io_dev, scoped_guard(mutex, &adc_dev->lock) { switch (chan->scan_index) { case PMIC_AUXADC_CHAN_IBAT: - ret =3D adc_dev->chip_info->read_imp(adc_dev, NULL, val); + ret =3D adc_dev->chip_info->read_imp(adc_dev, chan, NULL, val); break; case PMIC_AUXADC_CHAN_VBAT: - ret =3D adc_dev->chip_info->read_imp(adc_dev, val, NULL); + ret =3D adc_dev->chip_info->read_imp(adc_dev, chan, val, NULL); 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Mon, 23 Jun 2025 14:00:35 +0200 (CEST) From: AngeloGioacchino Del Regno To: jic23@kernel.org Cc: dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com Subject: [PATCH v1 4/5] iio: adc: mt6359: Add support for MediaTek MT6363 PMIC AUXADC Date: Mon, 23 Jun 2025 14:00:27 +0200 Message-ID: <20250623120028.108809-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250623120028.108809-1-angelogioacchino.delregno@collabora.com> References: <20250623120028.108809-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MediaTek MT6363 is a PMIC found on MT8196/MT6991 board designs and communicates with the SoC over SPMI. This PMIC integrates an Auxiliary ADC (AUXADC) which has a grand total of 54 ADC channels: 49 PMIC-internal channels, 2 external NTC thermistor channels and 2 generic ADC channels (mapped to 7 PMIC ADC external inputs). To use a generic ADC channel it is necessary to enable one of the PMIC ADC inputs at a time and only then start the reading, so in this case it is possible to read only one external input for each generic ADC channel. Due to the lack of documentation, this implementation supports using only one generic ADC channel, hence supports reading only one external input at a time. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado --- drivers/iio/adc/mt6359-auxadc.c | 238 +++++++++++++++++++++++++++++--- 1 file changed, 217 insertions(+), 21 deletions(-) diff --git a/drivers/iio/adc/mt6359-auxadc.c b/drivers/iio/adc/mt6359-auxad= c.c index ae7b65f5f551..f49b0b6e78da 100644 --- a/drivers/iio/adc/mt6359-auxadc.c +++ b/drivers/iio/adc/mt6359-auxadc.c @@ -7,6 +7,7 @@ * Author: AngeloGioacchino Del Regno */ =20 +#include #include #include #include @@ -24,6 +25,7 @@ #include #include #include +#include =20 #define AUXADC_AVG_TIME_US 10 #define AUXADC_POLL_DELAY_US 100 @@ -46,6 +48,18 @@ #define MT6359_IMP0_CONV_EN BIT(0) #define MT6359_IMP1_IRQ_RDY BIT(15) =20 +#define MT6363_EXT_CHAN_MASK GENMASK(2, 0) +#define MT6363_EXT_PURES_MASK GENMASK(4, 3) + #define MT6363_PULLUP_RES_100K 0 + #define MT6363_PULLUP_RES_OPEN 3 + +#define MTK_AUXADC_HAS_FLAG(pdata, msk) ((pdata)->flags & (MTK_PMIC_AUXADC= _##msk)) + +enum mtk_pmic_auxadc_flags { + MTK_PMIC_AUXADC_IS_SPMI =3D BIT(0), + MTK_PMIC_AUXADC_NO_RESET =3D BIT(1), +}; + enum mtk_pmic_auxadc_regs { PMIC_AUXADC_ADC0, PMIC_AUXADC_DCM_CON, @@ -54,6 +68,8 @@ enum mtk_pmic_auxadc_regs { PMIC_AUXADC_IMP3, PMIC_AUXADC_RQST0, PMIC_AUXADC_RQST1, + PMIC_AUXADC_RQST3, + PMIC_AUXADC_SDMADC_CON0, PMIC_HK_TOP_WKEY, PMIC_HK_TOP_RST_CON0, PMIC_FGADC_R_CON0, @@ -75,7 +91,17 @@ enum mtk_pmic_auxadc_channels { PMIC_AUXADC_CHAN_TSX_TEMP, PMIC_AUXADC_CHAN_HPOFS_CAL, PMIC_AUXADC_CHAN_DCXO_TEMP, + PMIC_AUXADC_CHAN_VTREF, PMIC_AUXADC_CHAN_VBIF, + PMIC_AUXADC_CHAN_IMIX_R, + PMIC_AUXADC_CHAN_VSYSSNS, + PMIC_AUXADC_CHAN_VIN1, + PMIC_AUXADC_CHAN_VIN2, + PMIC_AUXADC_CHAN_VIN3, + PMIC_AUXADC_CHAN_VIN4, + PMIC_AUXADC_CHAN_VIN5, + PMIC_AUXADC_CHAN_VIN6, + PMIC_AUXADC_CHAN_VIN7, PMIC_AUXADC_CHAN_IBAT, PMIC_AUXADC_CHAN_VBAT, PMIC_AUXADC_CHAN_MAX @@ -103,6 +129,9 @@ struct mt6359_auxadc { * @req_mask: Bitmask to activate a channel * @rdy_idx: Readiness register number * @rdy_mask: Bitmask to determine channel readiness + * @ext_sel_idx: PMIC GPIO channel register number + * @ext_sel_ch: PMIC GPIO number + * @ext_sel_pu: PMIC GPIO channel pullup resistor selector * @num_samples: Number of AUXADC samples for averaging * @r_ratio: Resistance ratio fractional */ @@ -111,6 +140,9 @@ struct mtk_pmic_auxadc_chan { u16 req_mask; u8 rdy_idx; u16 rdy_mask; + s8 ext_sel_idx; + u8 ext_sel_ch; + u8 ext_sel_pu; u16 num_samples; struct u8_fract r_ratio; }; @@ -123,7 +155,9 @@ struct mtk_pmic_auxadc_chan { * @desc: PMIC AUXADC channel data * @regs: List of PMIC specific registers * @sec_unlock_key: Security unlock key for HK_TOP writes + * @vref_mv: AUXADC Reference Voltage (VREF) in millivolts * @imp_adc_num: ADC channel for battery impedance readings + * @flags: Feature flags * @read_imp: Callback to read impedance channels */ struct mtk_pmic_auxadc_info { @@ -133,22 +167,33 @@ struct mtk_pmic_auxadc_info { const struct mtk_pmic_auxadc_chan *desc; const u16 *regs; u16 sec_unlock_key; + u16 vref_mv; u8 imp_adc_num; + u8 flags; int (*read_imp)(struct mt6359_auxadc *adc_dev, const struct iio_chan_spec *chan, int *vbat, int *ibat); }; =20 -#define MTK_PMIC_ADC_CHAN(_ch_idx, _req_idx, _req_bit, _rdy_idx, _rdy_bit,= \ - _samples, _rnum, _rdiv) \ +#define MTK_PMIC_ADC_EXT_CHAN(_ch_idx, _req_idx, _req_bit, _rdy_idx, _rdy_= bit, \ + _ext_sel_idx, _ext_sel_ch, _ext_sel_pu, \ + _samples, _rnum, _rdiv) \ [PMIC_AUXADC_CHAN_##_ch_idx] =3D { \ .req_idx =3D _req_idx, \ .req_mask =3D BIT(_req_bit), \ .rdy_idx =3D _rdy_idx, \ .rdy_mask =3D BIT(_rdy_bit), \ + .ext_sel_idx =3D _ext_sel_idx, \ + .ext_sel_ch =3D _ext_sel_ch, \ + .ext_sel_pu =3D _ext_sel_pu, \ .num_samples =3D _samples, \ .r_ratio =3D { _rnum, _rdiv } \ } =20 +#define MTK_PMIC_ADC_CHAN(_ch_idx, _req_idx, _req_bit, _rdy_idx, _rdy_bit,= \ + _samples, _rnum, _rdiv) \ + MTK_PMIC_ADC_EXT_CHAN(_ch_idx, _req_idx, _req_bit, _rdy_idx, _rdy_bit, \ + -1, 0, 0, _samples, _rnum, _rdiv) + #define MTK_PMIC_IIO_CHAN(_model, _name, _ch_idx, _adc_idx, _nbits, _ch_ty= pe) \ { \ .type =3D _ch_type, \ @@ -310,6 +355,70 @@ static const u16 mt6359_auxadc_regs[] =3D { [PMIC_AUXADC_IMP3] =3D 0x120e, }; =20 +static const struct iio_chan_spec mt6363_auxadc_channels[] =3D { + MTK_PMIC_IIO_CHAN(MT6363, bat_adc, BATADC, 0, 15, IIO_RESISTANCE), + MTK_PMIC_IIO_CHAN(MT6363, cdt_v, VCDT, 2, 12, IIO_TEMP),/**/ + MTK_PMIC_IIO_CHAN(MT6363, batt_temp, BAT_TEMP, 3, 12, IIO_TEMP), + MTK_PMIC_IIO_CHAN(MT6363, chip_temp, CHIP_TEMP, 4, 12, IIO_TEMP), + MTK_PMIC_IIO_CHAN(MT6363, sys_sns_v, VSYSSNS, 6, 15, IIO_VOLTAGE), + MTK_PMIC_IIO_CHAN(MT6363, tref_v, VTREF, 11, 12, IIO_VOLTAGE), + MTK_PMIC_IIO_CHAN(MT6363, vcore_temp, VCORE_TEMP, 38, 12, IIO_TEMP), + MTK_PMIC_IIO_CHAN(MT6363, vproc_temp, VPROC_TEMP, 39, 12, IIO_TEMP), + MTK_PMIC_IIO_CHAN(MT6363, vgpu_temp, VGPU_TEMP, 40, 12, IIO_TEMP), + + /* For VIN, ADC12 holds the result depending on which GPIO was activated = */ + MTK_PMIC_IIO_CHAN(MT6363, in1_v, VIN1, 45, 15, IIO_VOLTAGE), + MTK_PMIC_IIO_CHAN(MT6363, in2_v, VIN2, 45, 15, IIO_VOLTAGE), + MTK_PMIC_IIO_CHAN(MT6363, in3_v, VIN3, 45, 15, IIO_VOLTAGE), + MTK_PMIC_IIO_CHAN(MT6363, in4_v, VIN4, 45, 15, IIO_VOLTAGE), + MTK_PMIC_IIO_CHAN(MT6363, in5_v, VIN5, 45, 15, IIO_VOLTAGE), + MTK_PMIC_IIO_CHAN(MT6363, in6_v, VIN6, 45, 15, IIO_VOLTAGE), + MTK_PMIC_IIO_CHAN(MT6363, in7_v, VIN7, 45, 15, IIO_VOLTAGE), +}; + +static const struct mtk_pmic_auxadc_chan mt6363_auxadc_ch_desc[] =3D { + MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_ADC0, 15, 64,= 4, 1), + MTK_PMIC_ADC_CHAN(VCDT, PMIC_AUXADC_RQST0, 2, PMIC_AUXADC_ADC0, 15, 32, 1= , 1), + MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, PMIC_AUXADC_ADC0, 15, 3= 2, 3, 2), + MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_ADC0, 15, = 32, 1, 1), + MTK_PMIC_ADC_CHAN(VSYSSNS, PMIC_AUXADC_RQST1, 6, PMIC_AUXADC_ADC0, 15, 64= , 3, 1), + MTK_PMIC_ADC_CHAN(VTREF, PMIC_AUXADC_RQST1, 3, PMIC_AUXADC_ADC0, 15, 32, = 3, 2), + MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST3, 0, PMIC_AUXADC_ADC0, 15,= 32, 1, 1), + MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST3, 1, PMIC_AUXADC_ADC0, 15,= 32, 1, 1), + MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST3, 2, PMIC_AUXADC_ADC0, 15, = 32, 1, 1), + + MTK_PMIC_ADC_EXT_CHAN(VIN1, + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, + PMIC_AUXADC_SDMADC_CON0, 1, MT6363_PULLUP_RES_100K, 32, 1, 1), + MTK_PMIC_ADC_EXT_CHAN(VIN2, + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, + PMIC_AUXADC_SDMADC_CON0, 2, MT6363_PULLUP_RES_100K, 32, 1, 1), + MTK_PMIC_ADC_EXT_CHAN(VIN3, + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, + PMIC_AUXADC_SDMADC_CON0, 3, MT6363_PULLUP_RES_100K, 32, 1, 1), + MTK_PMIC_ADC_EXT_CHAN(VIN4, + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, + PMIC_AUXADC_SDMADC_CON0, 4, MT6363_PULLUP_RES_100K, 32, 1, 1), + MTK_PMIC_ADC_EXT_CHAN(VIN5, + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, + PMIC_AUXADC_SDMADC_CON0, 5, MT6363_PULLUP_RES_100K, 32, 1, 1), + MTK_PMIC_ADC_EXT_CHAN(VIN6, + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, + PMIC_AUXADC_SDMADC_CON0, 6, MT6363_PULLUP_RES_100K, 32, 1, 1), + MTK_PMIC_ADC_EXT_CHAN(VIN7, + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, + PMIC_AUXADC_SDMADC_CON0, 7, MT6363_PULLUP_RES_100K, 32, 1, 1), +}; + +static const u16 mt6363_auxadc_regs[] =3D { + [PMIC_AUXADC_RQST0] =3D 0x1108, + [PMIC_AUXADC_RQST1] =3D 0x1109, + [PMIC_AUXADC_RQST3] =3D 0x110c, + [PMIC_AUXADC_ADC0] =3D 0x1088, + [PMIC_AUXADC_IMP0] =3D 0x1208, + [PMIC_AUXADC_IMP1] =3D 0x1209, +}; + static void mt6358_stop_imp_conv(struct mt6359_auxadc *adc_dev) { const struct mtk_pmic_auxadc_info *cinfo =3D adc_dev->chip_info; @@ -379,13 +488,13 @@ static int mt6359_read_imp(struct mt6359_auxadc *adc_= dev, int ret; =20 /* Start conversion */ - regmap_write(regmap, cinfo->regs[PMIC_AUXADC_IMP0], MT6359_IMP0_CONV_EN); + regmap_write(regmap, cinfo->regs[desc->req_idx], desc->req_mask); ret =3D regmap_read_poll_timeout(regmap, cinfo->regs[desc->rdy_idx], val, val & desc->rdy_mask, IMP_POLL_DELAY_US, AUXADC_TIMEOUT_US); =20 /* Stop conversion regardless of the result */ - regmap_write(regmap, cinfo->regs[PMIC_AUXADC_IMP0], 0); + regmap_write(regmap, cinfo->regs[desc->req_idx], 0); if (ret) return ret; =20 @@ -416,6 +525,7 @@ static const struct mtk_pmic_auxadc_info mt6357_chip_in= fo =3D { .regs =3D mt6357_auxadc_regs, .imp_adc_num =3D MT6357_IMP_ADC_NUM, .read_imp =3D mt6358_read_imp, + .vref_mv =3D 1800, }; =20 static const struct mtk_pmic_auxadc_info mt6358_chip_info =3D { @@ -426,6 +536,7 @@ static const struct mtk_pmic_auxadc_info mt6358_chip_in= fo =3D { .regs =3D mt6358_auxadc_regs, .imp_adc_num =3D MT6358_IMP_ADC_NUM, .read_imp =3D mt6358_read_imp, + .vref_mv =3D 1800, }; =20 static const struct mtk_pmic_auxadc_info mt6359_chip_info =3D { @@ -436,6 +547,17 @@ static const struct mtk_pmic_auxadc_info mt6359_chip_i= nfo =3D { .regs =3D mt6359_auxadc_regs, .sec_unlock_key =3D 0x6359, .read_imp =3D mt6359_read_imp, + .vref_mv =3D 1800, +}; + +static const struct mtk_pmic_auxadc_info mt6363_chip_info =3D { + .model_name =3D "MT6363", + .channels =3D mt6363_auxadc_channels, + .num_channels =3D ARRAY_SIZE(mt6363_auxadc_channels), + .desc =3D mt6363_auxadc_ch_desc, + .regs =3D mt6363_auxadc_regs, + .flags =3D MTK_PMIC_AUXADC_IS_SPMI | MTK_PMIC_AUXADC_NO_RESET, + .vref_mv =3D 1840, }; =20 static void mt6359_auxadc_reset(struct mt6359_auxadc *adc_dev) @@ -464,27 +586,74 @@ static int mt6359_auxadc_read_adc(struct mt6359_auxad= c *adc_dev, const struct mtk_pmic_auxadc_info *cinfo =3D adc_dev->chip_info; const struct mtk_pmic_auxadc_chan *desc =3D &cinfo->desc[chan->scan_index= ]; struct regmap *regmap =3D adc_dev->regmap; - u32 val; + u32 reg, rdy_mask, val, lval; + u8 ext_sel; int ret; =20 + if (desc->ext_sel_idx >=3D 0) { + ext_sel =3D FIELD_PREP(MT6363_EXT_PURES_MASK, desc->ext_sel_pu); + ext_sel |=3D FIELD_PREP(MT6363_EXT_CHAN_MASK, desc->ext_sel_ch); + + ret =3D regmap_update_bits(regmap, cinfo->regs[desc->ext_sel_idx], + MT6363_EXT_PURES_MASK | MT6363_EXT_CHAN_MASK, + ext_sel); + if (ret) + return ret; + } + /* Request to start sampling for ADC channel */ ret =3D regmap_write(regmap, cinfo->regs[desc->req_idx], desc->req_mask); if (ret) - return ret; + goto end; =20 /* Wait until all samples are averaged */ fsleep(desc->num_samples * AUXADC_AVG_TIME_US); =20 - ret =3D regmap_read_poll_timeout(regmap, - cinfo->regs[PMIC_AUXADC_ADC0] + (chan->address << 1), - val, val & PMIC_AUXADC_RDY_BIT, + reg =3D cinfo->regs[PMIC_AUXADC_ADC0] + (chan->address << 1); + rdy_mask =3D PMIC_AUXADC_RDY_BIT; + + /* + * Even though for both PWRAP and SPMI cases the ADC HW signals that + * the data is ready by setting AUXADC_RDY_BIT, for SPMI the register + * read is only 8 bits long: for this case, the check has to be done + * on the ADC(x)_H register (high bits) and the rdy_mask needs to be + * shifted to the right by the same 8 bits. + */ + if (MTK_AUXADC_HAS_FLAG(cinfo, IS_SPMI)) { + rdy_mask >>=3D 8; + reg +=3D 1; + } + + ret =3D regmap_read_poll_timeout(regmap, reg, val, val & rdy_mask, AUXADC_POLL_DELAY_US, AUXADC_TIMEOUT_US); - if (ret) - return ret; + if (ret) { + dev_dbg(adc_dev->dev, "ADC read timeout for chan %lu\n", chan->address); + goto end; + } + + if (MTK_AUXADC_HAS_FLAG(cinfo, IS_SPMI)) { + /* If the previous read succeeded, this can't fail */ + regmap_read(regmap, reg - 1, &lval); + val =3D (val << 8) | lval; + } =20 - /* Stop sampling */ +end: + /* Stop sampling unconditionally... */ regmap_write(regmap, cinfo->regs[desc->req_idx], 0); =20 + /* ...and deactivate the ADC GPIO if previously done */ + if (desc->ext_sel_idx >=3D 0) { + ext_sel =3D FIELD_PREP(MT6363_EXT_PURES_MASK, MT6363_PULLUP_RES_OPEN); + + regmap_update_bits(regmap, cinfo->regs[desc->ext_sel_idx], + MT6363_EXT_PURES_MASK, ext_sel); + } + + /* Check if we reached this point because of an error or regular flow */ + if (ret) + return ret; + + /* Everything went fine, give back the ADC reading */ *out =3D val & GENMASK(chan->scan_type.realbits - 1, 0); return 0; } @@ -505,7 +674,7 @@ static int mt6359_auxadc_read_raw(struct iio_dev *indio= _dev, int ret; =20 if (mask =3D=3D IIO_CHAN_INFO_SCALE) { - *val =3D desc->r_ratio.numerator * AUXADC_VOLT_FULL; + *val =3D desc->r_ratio.numerator * (u32)cinfo->vref_mv; =20 if (desc->r_ratio.denominator > 1) { *val2 =3D desc->r_ratio.denominator; @@ -518,9 +687,15 @@ static int mt6359_auxadc_read_raw(struct iio_dev *indi= o_dev, scoped_guard(mutex, &adc_dev->lock) { switch (chan->scan_index) { case PMIC_AUXADC_CHAN_IBAT: + if (!adc_dev->chip_info->read_imp) + return -EOPNOTSUPP; + ret =3D adc_dev->chip_info->read_imp(adc_dev, chan, NULL, val); break; case PMIC_AUXADC_CHAN_VBAT: + if (!adc_dev->chip_info->read_imp) + return -EOPNOTSUPP; + ret =3D adc_dev->chip_info->read_imp(adc_dev, chan, val, NULL); break; default: @@ -535,7 +710,8 @@ static int mt6359_auxadc_read_raw(struct iio_dev *indio= _dev, * AUXADC is stuck: perform a full reset to recover it. */ if (ret =3D=3D -ETIMEDOUT) { - if (adc_dev->timed_out) { + if (!MTK_AUXADC_HAS_FLAG(cinfo, NO_RESET) && + adc_dev->timed_out) { dev_warn(adc_dev->dev, "Resetting stuck ADC!\r\n"); mt6359_auxadc_reset(adc_dev); } @@ -555,15 +731,36 @@ static const struct iio_info mt6359_auxadc_iio_info = =3D { =20 static int mt6359_auxadc_probe(struct platform_device *pdev) { + const struct mtk_pmic_auxadc_info *chip_info; struct device *dev =3D &pdev->dev; - struct device *mt6397_mfd_dev =3D dev->parent; + struct device *mfd_dev =3D dev->parent; struct mt6359_auxadc *adc_dev; struct iio_dev *indio_dev; + struct device *regmap_dev; struct regmap *regmap; int ret; =20 + chip_info =3D device_get_match_data(dev); + if (!chip_info) + return -EINVAL; + /* + * The regmap for this device has to be acquired differently for + * SoC PMIC Wrapper and SPMI PMIC cases: + * + * If this is under SPMI, the regmap comes from the direct parent of + * this driver: this_device->parent(mfd). + * ... or ... + * If this is under the SoC PMIC Wrapper, the regmap comes from the + * parent of the MT6397 MFD: this_device->parent(mfd)->parent(pwrap) + */ + if (MTK_AUXADC_HAS_FLAG(chip_info, IS_SPMI)) + regmap_dev =3D mfd_dev; + else + regmap_dev =3D mfd_dev->parent; + + /* Regmap is from SoC PMIC Wrapper, parent of the mt6397 MFD */ - regmap =3D dev_get_regmap(mt6397_mfd_dev->parent, NULL); + regmap =3D dev_get_regmap(regmap_dev, NULL); if (!regmap) return dev_err_probe(dev, -ENODEV, "Failed to get regmap\n"); =20 @@ -574,14 +771,12 @@ static int mt6359_auxadc_probe(struct platform_device= *pdev) adc_dev =3D iio_priv(indio_dev); adc_dev->regmap =3D regmap; adc_dev->dev =3D dev; - - adc_dev->chip_info =3D device_get_match_data(dev); - if (!adc_dev->chip_info) - return -EINVAL; + adc_dev->chip_info =3D chip_info; =20 mutex_init(&adc_dev->lock); =20 - mt6359_auxadc_reset(adc_dev); + if (!MTK_AUXADC_HAS_FLAG(chip_info, NO_RESET)) + mt6359_auxadc_reset(adc_dev); =20 indio_dev->name =3D adc_dev->chip_info->model_name; indio_dev->info =3D &mt6359_auxadc_iio_info; @@ -600,6 +795,7 @@ static const struct of_device_id mt6359_auxadc_of_match= [] =3D { { .compatible =3D "mediatek,mt6357-auxadc", .data =3D &mt6357_chip_info }, { .compatible =3D "mediatek,mt6358-auxadc", .data =3D &mt6358_chip_info }, { .compatible =3D "mediatek,mt6359-auxadc", .data =3D &mt6359_chip_info }, + { .compatible =3D "mediatek,mt6363-auxadc", .data =3D &mt6363_chip_info }, { } }; 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Mon, 23 Jun 2025 14:00:36 +0200 (CEST) From: AngeloGioacchino Del Regno To: jic23@kernel.org Cc: dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com Subject: [PATCH v1 5/5] iio: adc: mt6359: Add support for MediaTek MT6373 PMIC AUXADC Date: Mon, 23 Jun 2025 14:00:28 +0200 Message-ID: <20250623120028.108809-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250623120028.108809-1-angelogioacchino.delregno@collabora.com> References: <20250623120028.108809-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MediaTek MT6373 is a PMIC found on MT8196/MT6991 board designs and communicates with the SoC over SPMI. This PMIC integrates an Auxiliary ADC (AUXADC) which has a grand total of 54 channels, of which usually only 9 are used as this is usually paired with MT6363 on the same board. For the Auxiliary ADC part, this reuses the same register layout as the MT6363 PMIC, but exposes only a subset of the ADC chans. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado --- drivers/iio/adc/mt6359-auxadc.c | 49 +++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/iio/adc/mt6359-auxadc.c b/drivers/iio/adc/mt6359-auxad= c.c index f49b0b6e78da..909586282c1e 100644 --- a/drivers/iio/adc/mt6359-auxadc.c +++ b/drivers/iio/adc/mt6359-auxadc.c @@ -51,6 +51,7 @@ #define MT6363_EXT_CHAN_MASK GENMASK(2, 0) #define MT6363_EXT_PURES_MASK GENMASK(4, 3) #define MT6363_PULLUP_RES_100K 0 + #define MT6363_PULLUP_RES_30K 1 #define MT6363_PULLUP_RES_OPEN 3 =20 #define MTK_AUXADC_HAS_FLAG(pdata, msk) ((pdata)->flags & (MTK_PMIC_AUXADC= _##msk)) @@ -419,6 +420,43 @@ static const u16 mt6363_auxadc_regs[] =3D { [PMIC_AUXADC_IMP1] =3D 0x1209, }; =20 +static const struct iio_chan_spec mt6373_auxadc_channels[] =3D { + MTK_PMIC_IIO_CHAN(MT6363, chip_temp, CHIP_TEMP, 4, 12, IIO_TEMP), + MTK_PMIC_IIO_CHAN(MT6363, vcore_temp, VCORE_TEMP, 38, 12, IIO_TEMP), + MTK_PMIC_IIO_CHAN(MT6363, vproc_temp, VPROC_TEMP, 39, 12, IIO_TEMP), + MTK_PMIC_IIO_CHAN(MT6363, vgpu_temp, VGPU_TEMP, 40, 12, IIO_TEMP), + + /* For VIN, ADC12 holds the result depending on which GPIO was activated = */ + MTK_PMIC_IIO_CHAN(MT6363, in1_v, VIN1, 45, 15, IIO_VOLTAGE), + MTK_PMIC_IIO_CHAN(MT6363, in2_v, VIN2, 45, 15, IIO_VOLTAGE), + MTK_PMIC_IIO_CHAN(MT6363, in3_v, VIN3, 45, 15, IIO_VOLTAGE), + MTK_PMIC_IIO_CHAN(MT6363, in4_v, VIN4, 45, 15, IIO_VOLTAGE), + MTK_PMIC_IIO_CHAN(MT6363, in5_v, VIN5, 45, 15, IIO_VOLTAGE), +}; + +static const struct mtk_pmic_auxadc_chan mt6373_auxadc_ch_desc[] =3D { + MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_ADC0, 15, = 32, 1, 1), + MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST3, 0, PMIC_AUXADC_ADC0, 15,= 32, 1, 1), + MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST3, 1, PMIC_AUXADC_ADC0, 15,= 32, 1, 1), + MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST3, 2, PMIC_AUXADC_ADC0, 15, = 32, 1, 1), + + MTK_PMIC_ADC_EXT_CHAN(VIN1, + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, + PMIC_AUXADC_SDMADC_CON0, 1, MT6363_PULLUP_RES_30K, 32, 1, 1), + MTK_PMIC_ADC_EXT_CHAN(VIN2, + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, + PMIC_AUXADC_SDMADC_CON0, 2, MT6363_PULLUP_RES_OPEN, 32, 1, 1), + MTK_PMIC_ADC_EXT_CHAN(VIN3, + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, + PMIC_AUXADC_SDMADC_CON0, 3, MT6363_PULLUP_RES_OPEN, 32, 1, 1), + MTK_PMIC_ADC_EXT_CHAN(VIN4, + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, + PMIC_AUXADC_SDMADC_CON0, 4, MT6363_PULLUP_RES_OPEN, 32, 1, 1), + MTK_PMIC_ADC_EXT_CHAN(VIN5, + PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15, + PMIC_AUXADC_SDMADC_CON0, 5, MT6363_PULLUP_RES_OPEN, 32, 1, 1), +}; + static void mt6358_stop_imp_conv(struct mt6359_auxadc *adc_dev) { const struct mtk_pmic_auxadc_info *cinfo =3D adc_dev->chip_info; @@ -560,6 +598,16 @@ static const struct mtk_pmic_auxadc_info mt6363_chip_i= nfo =3D { .vref_mv =3D 1840, }; =20 +static const struct mtk_pmic_auxadc_info mt6373_chip_info =3D { + .model_name =3D "MT6373", + .channels =3D mt6373_auxadc_channels, + .num_channels =3D ARRAY_SIZE(mt6373_auxadc_channels), + .desc =3D mt6373_auxadc_ch_desc, + .regs =3D mt6363_auxadc_regs, + .flags =3D MTK_PMIC_AUXADC_IS_SPMI | MTK_PMIC_AUXADC_NO_RESET, + .vref_mv =3D 1840, +}; + static void mt6359_auxadc_reset(struct mt6359_auxadc *adc_dev) { const struct mtk_pmic_auxadc_info *cinfo =3D adc_dev->chip_info; @@ -796,6 +844,7 @@ static const struct of_device_id mt6359_auxadc_of_match= [] =3D { { .compatible =3D "mediatek,mt6358-auxadc", .data =3D &mt6358_chip_info }, { .compatible =3D "mediatek,mt6359-auxadc", .data =3D &mt6359_chip_info }, { .compatible =3D "mediatek,mt6363-auxadc", .data =3D &mt6363_chip_info }, + { .compatible =3D "mediatek,mt6373-auxadc", .data =3D &mt6373_chip_info }, { } }; MODULE_DEVICE_TABLE(of, mt6359_auxadc_of_match); --=20 2.49.0