From nobody Thu Oct 9 01:13:35 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E19C247DE1; Mon, 23 Jun 2025 10:30:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750674640; cv=none; b=n8cxCdgaNRbMA/vXhEtGAKAyop5brikX56rMEkr/rlrCpH3B1IMwz61DG8qmQoD0vHwWuATgqSnyBm/gqqXyOQ4pauF07GWaX9cwGGGdCQClWitFx3MHpKavE7kzGOodnaeFw3Brt5DRuh5UKjDjj4ca74NmcdRxQN2eY4bvj/o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750674640; c=relaxed/simple; bh=Brkc+6GuvreWYNLPzilP9Zav00LSZiZlD76bJuKjzH4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=cYUh9DJtu2ZdXK71dHN6IFseYS4IHhZ5acmRAwhg6GccCpuRBe+sj2e3mSnJRacpY/2JdSfUR0g4bJ6B/HicJEru7ae4C03linFs1CDnq0l8xzt1f4N0LWJnlwq2SQ7lDcMCt9CmhkET/FDhBlCbMck1NGsqQQu0z6H/FVyjOnA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=UXIPWBvT; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="UXIPWBvT" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1750674636; bh=Brkc+6GuvreWYNLPzilP9Zav00LSZiZlD76bJuKjzH4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UXIPWBvTh5tjmXZcSzMncTy5ddfliH3e9B1J8SaEUkG86CB00oi4I54F9cs0awnSE yy/ata0HkOACut3hJFfHAYrT6tgRWfmmGRdu8DJLYfM+tQKaKlHAVPbpdScQIlSIfa LxWxNJ5/yE8k5yC/itdfKoByhn4MMtlCUyISG0CWCp+/TNn3hn+V/nVUMW3N5Z/jXA ZTuVxnkox5TjHosPEIecTa8MdbItqVNocm/KHxzpvcW0FCtbttrCrppspMzeI2OPY0 Efgm/2hTj0URr0fy3a1VdqrfoMgL8xTiyDtWcCNfv4O3X3SFVkJrSXYQZAZEgFIZml PpTwQHQvTIClw== Received: from laura.lan (unknown [IPv6:2001:b07:646b:e2:e046:b666:1d47:e832]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laura.nao) by bali.collaboradmins.com (Postfix) with ESMTPSA id 9EA2517E156D; Mon, 23 Jun 2025 12:30:35 +0200 (CEST) From: Laura Nao To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, richardcochran@gmail.com Cc: guangjie.song@mediatek.com, wenst@chromium.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, kernel@collabora.com, Laura Nao Subject: [PATCH 08/30] clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro Date: Mon, 23 Jun 2025 12:29:18 +0200 Message-Id: <20250623102940.214269-9-laura.nao@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250623102940.214269-1-laura.nao@collabora.com> References: <20250623102940.214269-1-laura.nao@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On MT8196, some clocks use one register for parent selection and gating, and a separate register for frequency division. Since composite clocks can combine a mux, divider, and gate in a single entity, add a macro to simplify registration of such clocks by combining parent selection, frequency scaling, and enable control into one definition. Signed-off-by: Laura Nao --- drivers/clk/mediatek/clk-mtk.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index e2cefd9bc5b8..3498505b616e 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -176,6 +176,25 @@ struct mtk_composite { .flags =3D 0, \ } =20 +#define MUX_DIV_GATE(_id, _name, _parents, \ + _mux_reg, _mux_shift, _mux_width, \ + _div_reg, _div_shift, _div_width, \ + _gate_reg, _gate_shift) { \ + .id =3D _id, \ + .name =3D _name, \ + .parent_names =3D _parents, \ + .num_parents =3D ARRAY_SIZE(_parents), \ + .mux_reg =3D _mux_reg, \ + .mux_shift =3D _mux_shift, \ + .mux_width =3D _mux_width, \ + .divider_reg =3D _div_reg, \ + .divider_shift =3D _div_shift, \ + .divider_width =3D _div_width, \ + .gate_reg =3D _gate_reg, \ + .gate_shift =3D _gate_shift, \ + .flags =3D CLK_SET_RATE_PARENT, \ + } + int mtk_clk_register_composites(struct device *dev, const struct mtk_composite *mcs, int num, void __iomem *base, spinlock_t *lock, --=20 2.39.5