From nobody Thu Oct 9 01:13:33 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54B3425CC47; Mon, 23 Jun 2025 10:31:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750674669; cv=none; b=D35TruxSGPJDYwAPhGTMdesHmJwO+UQg3OdATLC9cEYPqxZjRsbkcqHcYVuLlamOp4fKIYy+1yEc/3uQqNArAN8h2UwMMcZe54UsOt28GmeLOpLnvOFOxiG/dIbbafkFaYKnQQ3mOZaiDl3NuvkEUj+gckVJFOscPpuNPp7u5po= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750674669; c=relaxed/simple; bh=Qwv6pzhi6PuN0st6EpFSbXJ8MS0e0vzzWswD1TZPMls=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QDCj30vTmgpd/fPUrRet3ZnMZfyoLcglCExXaYpl3m8U7h77sR4++4gxH/uFyXvTEDnYl+/qZzMy5pKEuozbJnAOWZIbZflqEbMc5MNJnbplq1IxgTqEVz9IejoZqeDOPIp2TlcDm3SwPZPMD+9RfQhK372oSOe3UugQ6AuZ4Ak= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=QI4p74ep; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="QI4p74ep" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1750674665; bh=Qwv6pzhi6PuN0st6EpFSbXJ8MS0e0vzzWswD1TZPMls=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QI4p74ep7GJ2n1Skyil4M2uYoOfHtTFLwbdKVJyACJNN0IvIX9fnxwHTySIE0V5aX /gys3bsLFofoUCFYw/sRmzk8w64unMXiGWJ6Hs52sGdTMwhx/zut3oomHZB4h7DEsb R0cKPERjohlkV2oO/ELgxlq5kqlEjS9QCC1uRU9nLsnG7Z+XgwCvl5qgtjWXrY2EtO 4hJakwEa7bNU689ha/DjBB5qgc8AHin9LDTy8Oxkyzkqzc3Z5LDLdSF3LKicsMvpib DCVLn7JjsY1dCDoRpt8/qel/AmvhK0C3fIEXcycKY4Bmba5sLb7Bub1Xut8wAfYfjo poFMVRG1oQw9A== Received: from laura.lan (unknown [IPv6:2001:b07:646b:e2:e046:b666:1d47:e832]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laura.nao) by bali.collaboradmins.com (Postfix) with ESMTPSA id 91AA617E0D64; Mon, 23 Jun 2025 12:31:04 +0200 (CEST) From: Laura Nao To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, richardcochran@gmail.com Cc: guangjie.song@mediatek.com, wenst@chromium.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, kernel@collabora.com, Laura Nao Subject: [PATCH 29/30] dt-bindings: reset: Add MediaTek MT8196 Reset Controller binding Date: Mon, 23 Jun 2025 12:29:39 +0200 Message-Id: <20250623102940.214269-30-laura.nao@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250623102940.214269-1-laura.nao@collabora.com> References: <20250623102940.214269-1-laura.nao@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: AngeloGioacchino Del Regno Add a binding for the PEXTP0/1 and UFS reset controllers found in the MediaTek MT8196 Chromebook SoC. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Laura Nao --- .../reset/mediatek,mt8196-resets.h | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 include/dt-bindings/reset/mediatek,mt8196-resets.h diff --git a/include/dt-bindings/reset/mediatek,mt8196-resets.h b/include/d= t-bindings/reset/mediatek,mt8196-resets.h new file mode 100644 index 000000000000..1a01b2b01f7f --- /dev/null +++ b/include/dt-bindings/reset/mediatek,mt8196-resets.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */ +/* + * Copyright (c) 2025 Collabora Ltd. + * Author: AngeloGioacchino Del Regno + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8196 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8196 + +/* PEXTP0 resets */ +#define MT8196_PEXTP0_RST0_PCIE0_MAC 0 +#define MT8196_PEXTP0_RST0_PCIE0_PHY 1 + +/* PEXTP1 resets */ +#define MT8196_PEXTP1_RST0_PCIE1_MAC 0 +#define MT8196_PEXTP1_RST0_PCIE1_PHY 1 +#define MT8196_PEXTP1_RST0_PCIE2_MAC 2 +#define MT8196_PEXTP1_RST0_PCIE2_PHY 3 + +/* UFS resets */ +#define MT8196_UFSAO_RST0_UFS_MPHY 0 +#define MT8196_UFSAO_RST1_UFS_UNIPRO 1 +#define MT8196_UFSAO_RST1_UFS_CRYPTO 2 +#define MT8196_UFSAO_RST1_UFSHCI 3 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8196 */ --=20 2.39.5