From nobody Thu Oct 9 01:13:38 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DC46421B9F6; Mon, 23 Jun 2025 08:09:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750666197; cv=none; b=KzxfacmBzv6HUTiV2bqQgZ9JQ8m5R+3c62u6sx8ukY1wd/mJ60zF9j7txQd2+S0tW4KA6zn6Ev9kIUVwS1O5DWrKWCgqq7Bifo6TQChHMS5+Tzih6mDXF+fMWb6rXyrfrvxB1oFS1zuYBpxD0I2p0YvZIH2meq94Nl4hsj+5uYk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750666197; c=relaxed/simple; bh=jbvBVSK0QvyjWQCHzB+4AzcokjKNmiHdXDymBZimNes=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Ds37PfHjfHkm43+XX280u55Sz8YL0aMmWpAnGX7/L8TtE+DAuWNS+g4xTHa+teiEn4RjDKWJ9FCkeurv/2YRNiOMQLt0CnSZ7fF74/0EjNqT/NqdzoPP4CB7yzu3Lt/r3QahGrOqEmHu1zyoh0OgEhJF6g5Xj2O/ebQ/Fn66Qbs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: sMKA97+MS5SS+4SgxWSUrw== X-CSE-MsgGUID: GFCjrcszQ9i5vOHSuVYUHg== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 23 Jun 2025 17:04:50 +0900 Received: from ubuntu.adwin.renesas.com (unknown [10.226.93.157]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id B1EDA400F744; Mon, 23 Jun 2025 17:04:45 +0900 (JST) From: John Madieu To: geert+renesas@glider.be, magnus.damm@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, richardcochran@gmail.com Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, netdev@vger.kernel.org, biju.das.jz@bp.renesas.com, John Madieu Subject: [PATCH v3 2/3] arm64: dts: renesas: r9a09g047: Add GBETH nodes Date: Mon, 23 Jun 2025 10:04:04 +0200 Message-ID: <20250623080405.355083-3-john.madieu.xa@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250623080405.355083-1-john.madieu.xa@bp.renesas.com> References: <20250623080405.355083-1-john.madieu.xa@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add GBETH nodes to RZ/G3E (R9A09G047) SoC DTSI. Reviewed-by: Biju Das Tested-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: John Madieu --- Changes: v2: No changes but resending without dt-bindings patch v3: Labels mdio nodes arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 207 +++++++++++++++++++++ 1 file changed, 207 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g047.dtsi index a0d4fab4fe05..a6a5b1e53e9c 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -759,6 +759,213 @@ csi2cru: endpoint@0 { }; }; }; + + eth0: ethernet@15c30000 { + compatible =3D "renesas,r9a09g047-gbeth", "renesas,rzv2h-gbeth", "snps,= dwmac-5.20"; + reg =3D <0 0x15c30000 0 0x10000>; + clocks =3D <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, + <&cpg CPG_CORE R9A09G047_GBETH_0_CLK_PTP_REF_I>, + <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, + <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; + clock-names =3D "stmmaceth", "pclk", "ptp_ref", + "tx", "rx", "tx-180", "rx-180"; + interrupts =3D , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "macirq", "eth_wake_irq", "eth_lpi", + "rx-queue-0", "rx-queue-1", "rx-queue-2", + "rx-queue-3", "tx-queue-0", "tx-queue-1", + "tx-queue-2", "tx-queue-3"; + resets =3D <&cpg 0xb0>; + power-domains =3D <&cpg>; + snps,multicast-filter-bins =3D <256>; + snps,perfect-filter-entries =3D <128>; + rx-fifo-depth =3D <8192>; + tx-fifo-depth =3D <8192>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,mtl-rx-config =3D <&mtl_rx_setup0>; + snps,mtl-tx-config =3D <&mtl_tx_setup0>; + snps,txpbl =3D <32>; + snps,rxpbl =3D <32>; + status =3D "disabled"; + + mdio0: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mtl_rx_setup0: rx-queues-config { + snps,rx-queues-to-use =3D <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority =3D <0x1>; + snps,map-to-dma-channel =3D <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority =3D <0x2>; + snps,map-to-dma-channel =3D <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority =3D <0x4>; + snps,map-to-dma-channel =3D <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority =3D <0x8>; + snps,map-to-dma-channel =3D <3>; + }; + }; + + mtl_tx_setup0: tx-queues-config { + snps,tx-queues-to-use =3D <4>; + + queue0 { + snps,dcb-algorithm; + snps,priority =3D <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority =3D <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority =3D <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority =3D <0x8>; + }; + }; + }; + + eth1: ethernet@15c40000 { + compatible =3D "renesas,r9a09g047-gbeth", "renesas,rzv2h-gbeth", "snps,= dwmac-5.20"; + reg =3D <0 0x15c40000 0 0x10000>; + clocks =3D <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, + <&cpg CPG_CORE R9A09G047_GBETH_1_CLK_PTP_REF_I>, + <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, + <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; + clock-names =3D "stmmaceth", "pclk", "ptp_ref", + "tx", "rx", "tx-180", "rx-180"; + interrupts =3D , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "macirq", "eth_wake_irq", "eth_lpi", + "rx-queue-0", "rx-queue-1", "rx-queue-2", + "rx-queue-3", "tx-queue-0", "tx-queue-1", + "tx-queue-2", "tx-queue-3"; + resets =3D <&cpg 0xb1>; + power-domains =3D <&cpg>; + snps,multicast-filter-bins =3D <256>; + snps,perfect-filter-entries =3D <128>; + rx-fifo-depth =3D <8192>; + tx-fifo-depth =3D <8192>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,mtl-rx-config =3D <&mtl_rx_setup1>; + snps,mtl-tx-config =3D <&mtl_tx_setup1>; + snps,txpbl =3D <32>; + snps,rxpbl =3D <32>; + status =3D "disabled"; + + mdio1: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mtl_rx_setup1: rx-queues-config { + snps,rx-queues-to-use =3D <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority =3D <0x1>; + snps,map-to-dma-channel =3D <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority =3D <0x2>; + snps,map-to-dma-channel =3D <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority =3D <0x4>; + snps,map-to-dma-channel =3D <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority =3D <0x8>; + snps,map-to-dma-channel =3D <3>; + }; + }; + + mtl_tx_setup1: tx-queues-config { + snps,tx-queues-to-use =3D <4>; + + queue0 { + snps,dcb-algorithm; + snps,priority =3D <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority =3D <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority =3D <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority =3D <0x8>; + }; + }; + }; + }; + + stmmac_axi_setup: stmmac-axi-config { + snps,lpi_en; + snps,wr_osr_lmt =3D <0xf>; + snps,rd_osr_lmt =3D <0xf>; + snps,blen =3D <16 8 4 0 0 0 0>; }; =20 timer { --=20 2.25.1