From nobody Thu Oct 9 02:19:12 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 013851B423B; Mon, 23 Jun 2025 05:37:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750657077; cv=none; b=VmRH9OFkOXh4o/P0bZedlmkKyz38Cs21PmBT8SazMZ/55fwtCF2YoQanbALNBH1RYcSSrgXvrxoF0wZ3o9qrOc8c/9WzlZvEVxAg0/ErV3CS9tzseTOHVg0oWWsP40tHtjZkITwXqnhscbMYhJDZmem4KNIgALTyGSnAiswuKrs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750657077; c=relaxed/simple; bh=68gh7ZStYt0XUza57ju+vopZkxGb2+esdgKOq/17Fto=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=BkfORYI2aENi/dEpO8gaIGb+U2t3brIIex0sHvj0hr+sKBvisXN1MdZI7td3GBUfQ0RmyBQ0+OL7SKPPzAjtHmEz75sKQWKB1jyfLo17Lw/Gv05cUpJEiBvI3LI2lQaxS+DXVMHA76KvBASeM/heuMW319BZ/l4P9G96Xpcd7CY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=g3vYEKmK; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="g3vYEKmK" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 55N5boWq1447276; Mon, 23 Jun 2025 00:37:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1750657070; bh=RUgOZI4KuDRaK+I7FYlwDvWmH08roVidaCqOCfHs0OQ=; h=From:To:Subject:Date:In-Reply-To:References; b=g3vYEKmKuEjO2YhiH6whZDrgcnqtYIg5w12R4BbW6UKHBksk8TvbAo7YjQwPCkdAc RTdaiaLDg5e3ZNK2Q4Iarzb3OMLgJYgwrMK5PtjgzvDc+2XZrLj0dxShsnXZ2QQqhj uluIUnIu1XjLdVYJQ2VBuSgo8DYoOnkbywyev5Ew= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 55N5boTM183574 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 23 Jun 2025 00:37:50 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 23 Jun 2025 00:37:49 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 23 Jun 2025 00:37:49 -0500 Received: from uda0498651.dhcp.ti.com (uda0498651.dhcp.ti.com [172.24.227.7]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 55N5bSqS3428603; Mon, 23 Jun 2025 00:37:45 -0500 From: Sai Sree Kartheek Adivi To: Peter Ujfalusi , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Santosh Shilimkar , Sai Sree Kartheek Adivi , , , , , , , , , Subject: [PATCH v3 03/17] dmaengine: ti: k3-udma: move static inline helper functions to header file Date: Mon, 23 Jun 2025 11:07:02 +0530 Message-ID: <20250623053716.1493974-4-s-adivi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250623053716.1493974-1-s-adivi@ti.com> References: <20250623053716.1493974-1-s-adivi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Move static inline helper functions in k3-udma.c to k3-udma.h header file for better separation and re-use. Signed-off-by: Sai Sree Kartheek Adivi --- drivers/dma/ti/k3-udma.c | 108 -------------------------------------- drivers/dma/ti/k3-udma.h | 109 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 109 insertions(+), 108 deletions(-) diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index e0684d83f9791..4adcd679c6997 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -40,91 +40,6 @@ static const char * const mmr_names[] =3D { [MMR_TCHANRT] =3D "tchanrt", }; =20 -static inline struct udma_dev *to_udma_dev(struct dma_device *d) -{ - return container_of(d, struct udma_dev, ddev); -} - -static inline struct udma_chan *to_udma_chan(struct dma_chan *c) -{ - return container_of(c, struct udma_chan, vc.chan); -} - -static inline struct udma_desc *to_udma_desc(struct dma_async_tx_descripto= r *t) -{ - return container_of(t, struct udma_desc, vd.tx); -} - -/* Generic register access functions */ -static inline u32 udma_read(void __iomem *base, int reg) -{ - return readl(base + reg); -} - -static inline void udma_write(void __iomem *base, int reg, u32 val) -{ - writel(val, base + reg); -} - -static inline void udma_update_bits(void __iomem *base, int reg, - u32 mask, u32 val) -{ - u32 tmp, orig; - - orig =3D readl(base + reg); - tmp =3D orig & ~mask; - tmp |=3D (val & mask); - - if (tmp !=3D orig) - writel(tmp, base + reg); -} - -/* TCHANRT */ -static inline u32 udma_tchanrt_read(struct udma_chan *uc, int reg) -{ - if (!uc->tchan) - return 0; - return udma_read(uc->tchan->reg_rt, reg); -} - -static inline void udma_tchanrt_write(struct udma_chan *uc, int reg, u32 v= al) -{ - if (!uc->tchan) - return; - udma_write(uc->tchan->reg_rt, reg, val); -} - -static inline void udma_tchanrt_update_bits(struct udma_chan *uc, int reg, - u32 mask, u32 val) -{ - if (!uc->tchan) - return; - udma_update_bits(uc->tchan->reg_rt, reg, mask, val); -} - -/* RCHANRT */ -static inline u32 udma_rchanrt_read(struct udma_chan *uc, int reg) -{ - if (!uc->rchan) - return 0; - return udma_read(uc->rchan->reg_rt, reg); -} - -static inline void udma_rchanrt_write(struct udma_chan *uc, int reg, u32 v= al) -{ - if (!uc->rchan) - return; - udma_write(uc->rchan->reg_rt, reg, val); -} - -static inline void udma_rchanrt_update_bits(struct udma_chan *uc, int reg, - u32 mask, u32 val) -{ - if (!uc->rchan) - return; - udma_update_bits(uc->rchan->reg_rt, reg, mask, val); -} - static int navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_th= read) { struct udma_tisci_rm *tisci_rm =3D &ud->tisci_rm; @@ -216,17 +131,6 @@ static void udma_dump_chan_stdata(struct udma_chan *uc) } } =20 -static inline dma_addr_t udma_curr_cppi5_desc_paddr(struct udma_desc *d, - int idx) -{ - return d->hwdesc[idx].cppi5_desc_paddr; -} - -static inline void *udma_curr_cppi5_desc_vaddr(struct udma_desc *d, int id= x) -{ - return d->hwdesc[idx].cppi5_desc_vaddr; -} - static struct udma_desc *udma_udma_desc_from_paddr(struct udma_chan *uc, dma_addr_t paddr) { @@ -369,11 +273,6 @@ static bool udma_is_chan_paused(struct udma_chan *uc) return false; } =20 -static inline dma_addr_t udma_get_rx_flush_hwdesc_paddr(struct udma_chan *= uc) -{ - return uc->ud->rx_flush.hwdescs[uc->config.pkt_mode].cppi5_desc_paddr; -} - static int udma_push_to_ring(struct udma_chan *uc, int idx) { struct udma_desc *d =3D uc->desc; @@ -775,13 +674,6 @@ static void udma_cyclic_packet_elapsed(struct udma_cha= n *uc) d->desc_idx =3D (d->desc_idx + 1) % d->sglen; } =20 -static inline void udma_fetch_epib(struct udma_chan *uc, struct udma_desc = *d) -{ - struct cppi5_host_desc_t *h_desc =3D d->hwdesc[0].cppi5_desc_vaddr; - - memcpy(d->metadata, h_desc->epib, d->metadata_size); -} - static bool udma_is_desc_really_done(struct udma_chan *uc, struct udma_des= c *d) { u32 peer_bcnt, bcnt; diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h index 37aa9ba5b4d18..3a786b3eddc67 100644 --- a/drivers/dma/ti/k3-udma.h +++ b/drivers/dma/ti/k3-udma.h @@ -447,6 +447,115 @@ struct udma_chan { u32 id; }; =20 +/* K3 UDMA helper functions */ +static inline struct udma_dev *to_udma_dev(struct dma_device *d) +{ + return container_of(d, struct udma_dev, ddev); +} + +static inline struct udma_chan *to_udma_chan(struct dma_chan *c) +{ + return container_of(c, struct udma_chan, vc.chan); +} + +static inline struct udma_desc *to_udma_desc(struct dma_async_tx_descripto= r *t) +{ + return container_of(t, struct udma_desc, vd.tx); +} + +/* Generic register access functions */ +static inline u32 udma_read(void __iomem *base, int reg) +{ + return readl(base + reg); +} + +static inline void udma_write(void __iomem *base, int reg, u32 val) +{ + writel(val, base + reg); +} + +static inline void udma_update_bits(void __iomem *base, int reg, + u32 mask, u32 val) +{ + u32 tmp, orig; + + orig =3D readl(base + reg); + tmp =3D orig & ~mask; + tmp |=3D (val & mask); + + if (tmp !=3D orig) + writel(tmp, base + reg); +} + +/* TCHANRT */ +static inline u32 udma_tchanrt_read(struct udma_chan *uc, int reg) +{ + if (!uc->tchan) + return 0; + return udma_read(uc->tchan->reg_rt, reg); +} + +static inline void udma_tchanrt_write(struct udma_chan *uc, int reg, u32 v= al) +{ + if (!uc->tchan) + return; + udma_write(uc->tchan->reg_rt, reg, val); +} + +static inline void udma_tchanrt_update_bits(struct udma_chan *uc, int reg, + u32 mask, u32 val) +{ + if (!uc->tchan) + return; + udma_update_bits(uc->tchan->reg_rt, reg, mask, val); +} + +/* RCHANRT */ +static inline u32 udma_rchanrt_read(struct udma_chan *uc, int reg) +{ + if (!uc->rchan) + return 0; + return udma_read(uc->rchan->reg_rt, reg); +} + +static inline void udma_rchanrt_write(struct udma_chan *uc, int reg, u32 v= al) +{ + if (!uc->rchan) + return; + udma_write(uc->rchan->reg_rt, reg, val); +} + +static inline void udma_rchanrt_update_bits(struct udma_chan *uc, int reg, + u32 mask, u32 val) +{ + if (!uc->rchan) + return; + udma_update_bits(uc->rchan->reg_rt, reg, mask, val); +} + +static inline dma_addr_t udma_curr_cppi5_desc_paddr(struct udma_desc *d, + int idx) +{ + return d->hwdesc[idx].cppi5_desc_paddr; +} + +static inline void *udma_curr_cppi5_desc_vaddr(struct udma_desc *d, int id= x) +{ + return d->hwdesc[idx].cppi5_desc_vaddr; +} + +static inline dma_addr_t udma_get_rx_flush_hwdesc_paddr(struct udma_chan *= uc) +{ + return uc->ud->rx_flush.hwdescs[uc->config.pkt_mode].cppi5_desc_paddr; +} + +static inline void udma_fetch_epib(struct udma_chan *uc, struct udma_desc = *d) +{ + struct cppi5_host_desc_t *h_desc =3D d->hwdesc[0].cppi5_desc_vaddr; + + memcpy(d->metadata, h_desc->epib, d->metadata_size); +} + /* Direct access to UDMA low lever resources for the glue layer */ int xudma_navss_psil_pair(struct udma_dev *ud, u32 src_thread, u32 dst_thr= ead); int xudma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread, --=20 2.34.1