From nobody Thu Oct 9 02:19:12 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B27611DACB1; Mon, 23 Jun 2025 05:37:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750657080; cv=none; b=oqDm/m7BSbXBCrZEN0QIXeAl0UrZf6zFAGd8O6RTX6Cxd5iPCWJL13s+J+RFfwQOukXg/oaOzdyviC8TMm8J8/TPEg6GpGUMvOXKgi/6ZLVcWLQcdmB316jSzA5f9bSUFQXYclKHQ078aKdQ0eYt8va5sMTH7fctMKAIRE0erLc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750657080; c=relaxed/simple; bh=ftBn7SikCju7zI/wzfgqM1wneiRNZIVVAhcB8BTR908=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=IINHbdeG0pwOdQAxpV6aTiT1ASFcFYDb3l8TK/u42Iw4Z8XC2GXBlNlV6vyxwAQFRKDAGGMMtzH0q7eWGpnCVB4UHrJzWjtvV9MYrBnnMvL2TTJyhVTKNiWqoeQ1zz8xk++kk1Ag/2ytQjLxrvjCHY0vajUDFb/0GoUB4Zjl3DI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=BXOV/gcc; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="BXOV/gcc" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 55N5bdYU1447048; Mon, 23 Jun 2025 00:37:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1750657059; bh=elLIf7fn3ROfjQByGp/TsTtfayAS/aLZr2yQStBrTrY=; h=From:To:Subject:Date:In-Reply-To:References; b=BXOV/gccj91Q6DVbXf/CU2JsTbbZ2EvMxEXbXMjdt7/8aI6y0saGhiM+kF3QMBklD t17bVhz1GDEVT9OrXhBQQdGVh3PYRTxG1XGrwDI+sQmodV/2W2l4dRpn7xhCifWw7h sLMO035NufGGuM+fqW1MslPyNdr4BQ/zY23Se574= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 55N5bdm0183338 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 23 Jun 2025 00:37:39 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 23 Jun 2025 00:37:39 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 23 Jun 2025 00:37:39 -0500 Received: from uda0498651.dhcp.ti.com (uda0498651.dhcp.ti.com [172.24.227.7]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 55N5bSqQ3428603; Mon, 23 Jun 2025 00:37:34 -0500 From: Sai Sree Kartheek Adivi To: Peter Ujfalusi , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Santosh Shilimkar , Sai Sree Kartheek Adivi , , , , , , , , , Subject: [PATCH v3 01/17] dmaengine: ti: k3-udma: move macros to header file Date: Mon, 23 Jun 2025 11:07:00 +0530 Message-ID: <20250623053716.1493974-2-s-adivi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250623053716.1493974-1-s-adivi@ti.com> References: <20250623053716.1493974-1-s-adivi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Move macros defined in k3-udma.c to k3-udma.h for better separation and re-use. Signed-off-by: Sai Sree Kartheek Adivi --- drivers/dma/ti/k3-udma.c | 62 --------------------------------------- drivers/dma/ti/k3-udma.h | 63 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+), 62 deletions(-) diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index aa2dc762140f6..4cc64763de1f6 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -39,21 +39,6 @@ struct udma_static_tr { u16 bstcnt; /* RPSTR1 */ }; =20 -#define K3_UDMA_MAX_RFLOWS 1024 -#define K3_UDMA_DEFAULT_RING_SIZE 16 - -/* How SRC/DST tag should be updated by UDMA in the descriptor's Word 3 */ -#define UDMA_RFLOW_SRCTAG_NONE 0 -#define UDMA_RFLOW_SRCTAG_CFG_TAG 1 -#define UDMA_RFLOW_SRCTAG_FLOW_ID 2 -#define UDMA_RFLOW_SRCTAG_SRC_TAG 4 - -#define UDMA_RFLOW_DSTTAG_NONE 0 -#define UDMA_RFLOW_DSTTAG_CFG_TAG 1 -#define UDMA_RFLOW_DSTTAG_FLOW_ID 2 -#define UDMA_RFLOW_DSTTAG_DST_TAG_LO 4 -#define UDMA_RFLOW_DSTTAG_DST_TAG_HI 5 - struct udma_chan; =20 enum k3_dma_type { @@ -118,15 +103,6 @@ struct udma_oes_offsets { u32 pktdma_rchan_flow; }; =20 -#define UDMA_FLAG_PDMA_ACC32 BIT(0) -#define UDMA_FLAG_PDMA_BURST BIT(1) -#define UDMA_FLAG_TDTYPE BIT(2) -#define UDMA_FLAG_BURST_SIZE BIT(3) -#define UDMA_FLAGS_J7_CLASS (UDMA_FLAG_PDMA_ACC32 | \ - UDMA_FLAG_PDMA_BURST | \ - UDMA_FLAG_TDTYPE | \ - UDMA_FLAG_BURST_SIZE) - struct udma_match_data { enum k3_dma_type type; u32 psil_base; @@ -1837,38 +1813,6 @@ static int udma_alloc_rx_resources(struct udma_chan = *uc) return ret; } =20 -#define TISCI_BCDMA_BCHAN_VALID_PARAMS ( \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID) - -#define TISCI_BCDMA_TCHAN_VALID_PARAMS ( \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID) - -#define TISCI_BCDMA_RCHAN_VALID_PARAMS ( \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID) - -#define TISCI_UDMA_TCHAN_VALID_PARAMS ( \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID) - -#define TISCI_UDMA_RCHAN_VALID_PARAMS ( \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID | \ - TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID) - static int udma_tisci_m2m_channel_config(struct udma_chan *uc) { struct udma_dev *ud =3D uc->ud; @@ -5398,12 +5342,6 @@ static enum dmaengine_alignment udma_get_copy_align(= struct udma_dev *ud) } } =20 -#define TI_UDMAC_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ - BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ - BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \ - BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ - BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)) - static int udma_probe(struct platform_device *pdev) { struct device_node *navss_node =3D pdev->dev.parent->of_node; diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h index 9062a237cd167..750720cd06911 100644 --- a/drivers/dma/ti/k3-udma.h +++ b/drivers/dma/ti/k3-udma.h @@ -97,6 +97,69 @@ /* Address Space Select */ #define K3_ADDRESS_ASEL_SHIFT 48 =20 +#define K3_UDMA_MAX_RFLOWS 1024 +#define K3_UDMA_DEFAULT_RING_SIZE 16 + +/* How SRC/DST tag should be updated by UDMA in the descriptor's Word 3 */ +#define UDMA_RFLOW_SRCTAG_NONE 0 +#define UDMA_RFLOW_SRCTAG_CFG_TAG 1 +#define UDMA_RFLOW_SRCTAG_FLOW_ID 2 +#define UDMA_RFLOW_SRCTAG_SRC_TAG 4 + +#define UDMA_RFLOW_DSTTAG_NONE 0 +#define UDMA_RFLOW_DSTTAG_CFG_TAG 1 +#define UDMA_RFLOW_DSTTAG_FLOW_ID 2 +#define UDMA_RFLOW_DSTTAG_DST_TAG_LO 4 +#define UDMA_RFLOW_DSTTAG_DST_TAG_HI 5 + +#define UDMA_FLAG_PDMA_ACC32 BIT(0) +#define UDMA_FLAG_PDMA_BURST BIT(1) +#define UDMA_FLAG_TDTYPE BIT(2) +#define UDMA_FLAG_BURST_SIZE BIT(3) +#define UDMA_FLAGS_J7_CLASS (UDMA_FLAG_PDMA_ACC32 | \ + UDMA_FLAG_PDMA_BURST | \ + UDMA_FLAG_TDTYPE | \ + UDMA_FLAG_BURST_SIZE) + +#define TI_UDMAC_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ + BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \ + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ + BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)) + +/* TI_SCI Params */ +#define TISCI_BCDMA_BCHAN_VALID_PARAMS ( \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID) + +#define TISCI_BCDMA_TCHAN_VALID_PARAMS ( \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID) + +#define TISCI_BCDMA_RCHAN_VALID_PARAMS ( \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID) + +#define TISCI_UDMA_TCHAN_VALID_PARAMS ( \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID) + +#define TISCI_UDMA_RCHAN_VALID_PARAMS ( \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID | \ + TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID) + struct udma_dev; struct udma_tchan; struct udma_rchan; --=20 2.34.1