From nobody Thu Oct 9 02:19:10 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 730BC1E2852; Mon, 23 Jun 2025 05:39:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750657148; cv=none; b=UbEacvvpzRnxxKnBFWVrLWoYq4cf+/rpZXpXwiGLMjGPRUhIFN2RLpDDtjwdSEn8VYYerQg0AMBqJddAHPMZz9mU9MSzsxN0kgKPPlfbDdRbQiSBXalbFLlKujjVIW2YiWql203osmP3y7lG1kEHZG0KP66GpbOdSXkZDckCLVU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750657148; c=relaxed/simple; bh=387z28oGSGVVWuxh8VxhZcbFizHDod6ZqTlRdJTZdRE=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NITQCDHan2s07XboPrOqXh6+39uWdIa4Ehal3CY9HeUU5DK3WAcbGOT9Ohn5jMCBOvtkVG9pws234giSMYPYrmyQwA+vlx83z8xLIJPTEDlwSLhDFiXVNB8+XLXRlei3NF/xs+2B+P6DaW9UMIg4dNPwhHzv77g4C9gdsdMiLe8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=oxl7BP8D; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="oxl7BP8D" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 55N5cxmg1448451; Mon, 23 Jun 2025 00:38:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1750657139; bh=iYRpBvF2jlQhK+h8AUnki0wKcwp2JR5XoHwISg4/Cbk=; h=From:To:Subject:Date:In-Reply-To:References; b=oxl7BP8Dvk0t6ucY9VqVulXZsqcXJK3YpUI+HZ+ydJYcojUkDQXOQugcrL5Ipa7B+ xiSopP7uDucGU5kmOq/OVxLqn8HEB2rkxJ2bmgj+1psXZkokHSjv+fS3D0rW7VGy15 0JUWV3FHAWmxAUQHsxE0kxuWxTADSzGLxzMj7pLs= Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 55N5cxgB467746 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 23 Jun 2025 00:38:59 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 23 Jun 2025 00:38:59 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 23 Jun 2025 00:38:59 -0500 Received: from uda0498651.dhcp.ti.com (uda0498651.dhcp.ti.com [172.24.227.7]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 55N5bSqf3428603; Mon, 23 Jun 2025 00:38:54 -0500 From: Sai Sree Kartheek Adivi To: Peter Ujfalusi , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Santosh Shilimkar , Sai Sree Kartheek Adivi , , , , , , , , , Subject: [PATCH v3 16/17] dmaengine: ti: k3-udma-v2: Add support for PKTDMA V2 Date: Mon, 23 Jun 2025 11:07:15 +0530 Message-ID: <20250623053716.1493974-17-s-adivi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250623053716.1493974-1-s-adivi@ti.com> References: <20250623053716.1493974-1-s-adivi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The PKTDMA V2 is different than the existing PKTDMA supported by the k3-udma driver. The changes in PKTDMA V2 are: - Autopair: There is no longer a need for PSIL pair and AUTOPAIR bit needs to set in the RT_CTL register. - Static channel mapping: Each channel is mapped to a single peripheral. - Direct IRQs: There is no INT-A and interrupt lines from DMA are directly connected to GIC. - Remote side configuration handled by DMA. So no need to write to PEER registers to START / STOP / PAUSE / TEARDOWN. Signed-off-by: Sai Sree Kartheek Adivi --- drivers/dma/ti/k3-udma-common.c | 29 ++++- drivers/dma/ti/k3-udma-v2.c | 219 ++++++++++++++++++++++++++++++-- drivers/dma/ti/k3-udma.h | 3 + 3 files changed, 232 insertions(+), 19 deletions(-) diff --git a/drivers/dma/ti/k3-udma-common.c b/drivers/dma/ti/k3-udma-commo= n.c index 7aae327fa3b71..d609a4a957cc1 100644 --- a/drivers/dma/ti/k3-udma-common.c +++ b/drivers/dma/ti/k3-udma-common.c @@ -2414,12 +2414,21 @@ int pktdma_setup_resources(struct udma_dev *ud) =20 ud->tchan_map =3D devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt), sizeof(unsigned long), GFP_KERNEL); + bitmap_zero(ud->tchan_map, ud->tchan_cnt); ud->tchans =3D devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans), GFP_KERNEL); - ud->rchan_map =3D devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt), - sizeof(unsigned long), GFP_KERNEL); - ud->rchans =3D devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans), - GFP_KERNEL); + if (ud->match_data->type =3D=3D DMA_TYPE_PKTDMA_V2) { + ud->rchan_map =3D ud->tchan_map; + ud->rchans =3D ud->tchans; + ud->chan_map =3D ud->tchan_map; + ud->chans =3D ud->tchans; + } else { + ud->rchan_map =3D devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt), + sizeof(unsigned long), GFP_KERNEL); + bitmap_zero(ud->rchan_map, ud->rchan_cnt); + ud->rchans =3D devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans), + GFP_KERNEL); + } ud->rflow_in_use =3D devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt), sizeof(unsigned long), GFP_KERNEL); @@ -2427,6 +2436,8 @@ int pktdma_setup_resources(struct udma_dev *ud) GFP_KERNEL); ud->tflow_map =3D devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tflow_cnt), sizeof(unsigned long), GFP_KERNEL); + bitmap_zero(ud->tflow_map, ud->tflow_cnt); + =20 if (!ud->tchan_map || !ud->rchan_map || !ud->tflow_map || !ud->tchans || !ud->rchans || !ud->rflows || !ud->rflow_in_use) @@ -2455,6 +2466,7 @@ int setup_resources(struct udma_dev *ud) ret =3D bcdma_setup_resources(ud); break; case DMA_TYPE_PKTDMA: + case DMA_TYPE_PKTDMA_V2: ret =3D pktdma_setup_resources(ud); break; default: @@ -2464,7 +2476,7 @@ int setup_resources(struct udma_dev *ud) if (ret) return ret; =20 - if (ud->match_data->type =3D=3D DMA_TYPE_BCDMA_V2) { + if (ud->match_data->type >=3D DMA_TYPE_BCDMA_V2) { ch_count =3D ud->bchan_cnt + ud->tchan_cnt; if (ud->bchan_cnt) ch_count -=3D bitmap_weight(ud->bchan_map, ud->bchan_cnt); @@ -2525,6 +2537,13 @@ int setup_resources(struct udma_dev *ud) ud->rchan_cnt - bitmap_weight(ud->rchan_map, ud->rchan_cnt)); break; + case DMA_TYPE_PKTDMA_V2: + dev_info(dev, + "Channels: %d (tchan + rchan: %u)\n", + ch_count, + ud->chan_cnt - bitmap_weight(ud->chan_map, + ud->chan_cnt)); + break; default: break; } diff --git a/drivers/dma/ti/k3-udma-v2.c b/drivers/dma/ti/k3-udma-v2.c index e15ab7cee107d..4c4d807263c05 100644 --- a/drivers/dma/ti/k3-udma-v2.c +++ b/drivers/dma/ti/k3-udma-v2.c @@ -746,6 +746,146 @@ static int bcdma_v2_alloc_chan_resources(struct dma_c= han *chan) return ret; } =20 +static int pktdma_v2_alloc_chan_resources(struct dma_chan *chan) +{ + struct udma_chan *uc =3D to_udma_chan(chan); + struct udma_dev *ud =3D to_udma_dev(chan->device); + u32 irq_ring_idx; + __be32 addr[2] =3D {0, 0}; + struct of_phandle_args out_irq; + int ret; + + /* + * Make sure that the completion is in a known state: + * No teardown, the channel is idle + */ + reinit_completion(&uc->teardown_completed); + complete_all(&uc->teardown_completed); + uc->state =3D UDMA_CHAN_IS_IDLE; + + switch (uc->config.dir) { + case DMA_MEM_TO_DEV: + /* Slave transfer synchronized - mem to dev (TX) transfer */ + dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-DEV\n", __func__, + uc->id); + + ret =3D udma_v2_alloc_tx_resources(uc); + if (ret) { + uc->config.remote_thread_id =3D -1; + return ret; + } + + uc->config.src_thread =3D ud->psil_base + uc->tchan->id; + uc->config.dst_thread =3D uc->config.remote_thread_id; + uc->config.dst_thread |=3D K3_PSIL_DST_THREAD_ID_OFFSET; + + irq_ring_idx =3D uc->config.mapped_channel_id; + break; + case DMA_DEV_TO_MEM: + /* Slave transfer synchronized - dev to mem (RX) transfer */ + dev_dbg(uc->ud->dev, "%s: chan%d as DEV-to-MEM\n", __func__, + uc->id); + + ret =3D udma_v2_alloc_rx_resources(uc); + if (ret) { + uc->config.remote_thread_id =3D -1; + return ret; + } + + uc->config.src_thread =3D uc->config.remote_thread_id; + uc->config.dst_thread =3D (ud->psil_base + uc->rchan->id) | + K3_PSIL_DST_THREAD_ID_OFFSET; + + irq_ring_idx =3D uc->config.mapped_channel_id; + udma_write(uc->rflow->reg_rt, UDMA_RX_FLOWRT_RFA, BIT(28)); + break; + default: + /* Can not happen */ + dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n", + __func__, uc->id, uc->config.dir); + return -EINVAL; + } + + /* check if the channel configuration was successful */ + if (ret) + goto err_res_free; + + if (udma_is_chan_running(uc)) { + dev_warn(ud->dev, "chan%d: is running!\n", uc->id); + ud->reset_chan(uc, false); + if (udma_is_chan_running(uc)) { + dev_err(ud->dev, "chan%d: won't stop!\n", uc->id); + ret =3D -EBUSY; + goto err_res_free; + } + } + + uc->dma_dev =3D dmaengine_get_dma_device(chan); + uc->hdesc_pool =3D dma_pool_create(uc->name, uc->dma_dev, + uc->config.hdesc_size, ud->desc_align, + 0); + if (!uc->hdesc_pool) { + dev_err(ud->ddev.dev, + "Descriptor pool allocation failed\n"); + uc->use_dma_pool =3D false; + ret =3D -ENOMEM; + goto err_res_free; + } + + uc->use_dma_pool =3D true; + + uc->psil_paired =3D true; + + out_irq.np =3D dev_of_node(ud->dev); + out_irq.args_count =3D 1; + out_irq.args[0] =3D irq_ring_idx; + ret =3D of_irq_parse_raw(addr, &out_irq); + if (ret) + return ret; + + uc->irq_num_ring =3D irq_create_of_mapping(&out_irq); + + ret =3D devm_request_irq(ud->dev, uc->irq_num_ring, udma_v2_ring_irq_hand= ler, + IRQF_TRIGGER_HIGH, uc->name, uc); + + if (ret) { + dev_err(ud->dev, "chan%d: ring irq request failed\n", uc->id); + goto err_irq_free; + } + + uc->irq_num_udma =3D 0; + + udma_reset_rings(uc); + + INIT_DELAYED_WORK_ONSTACK(&uc->tx_drain.work, + udma_check_tx_completion); + + if (uc->tchan) + dev_dbg(ud->dev, + "chan%d: tchan%d, tflow%d, Remote thread: 0x%04x\n", + uc->id, uc->tchan->id, uc->tchan->tflow_id, + uc->config.remote_thread_id); + else if (uc->rchan) + dev_dbg(ud->dev, + "chan%d: rchan%d, rflow%d, Remote thread: 0x%04x\n", + uc->id, uc->rchan->id, uc->rflow->id, + uc->config.remote_thread_id); + return 0; + +err_irq_free: + uc->irq_num_ring =3D 0; +err_res_free: + udma_free_tx_resources(uc); + udma_free_rx_resources(uc); + + udma_reset_uchan(uc); + + dma_pool_destroy(uc->hdesc_pool); + uc->use_dma_pool =3D false; + + return ret; +} + static enum dma_status udma_v2_tx_status(struct dma_chan *chan, dma_cookie_t cookie, struct dma_tx_state *txstate) @@ -840,6 +980,7 @@ static int udma_v2_resume(struct dma_chan *chan) } =20 static struct platform_driver bcdma_v2_driver; +static struct platform_driver pktdma_v2_driver; =20 static bool udma_v2_dma_filter_fn(struct dma_chan *chan, void *param) { @@ -849,7 +990,8 @@ static bool udma_v2_dma_filter_fn(struct dma_chan *chan= , void *param) struct udma_chan *uc; struct udma_dev *ud; =20 - if (chan->device->dev->driver !=3D &bcdma_v2_driver.driver) + if (chan->device->dev->driver !=3D &bcdma_v2_driver.driver && + chan->device->dev->driver !=3D &pktdma_v2_driver.driver) return false; =20 uc =3D to_udma_chan(chan); @@ -892,7 +1034,7 @@ static bool udma_v2_dma_filter_fn(struct dma_chan *cha= n, void *param) ucc->notdpkt =3D ep_config->notdpkt; ucc->ep_type =3D ep_config->ep_type; =20 - if (ud->match_data->type =3D=3D DMA_TYPE_BCDMA_V2 && + if (ud->match_data->type >=3D DMA_TYPE_BCDMA_V2 && ep_config->mapped_channel_id >=3D 0) { ucc->mapped_channel_id =3D ep_config->mapped_channel_id; ucc->default_flow_id =3D ep_config->default_flow_id; @@ -991,11 +1133,33 @@ static struct udma_match_data bcdma_v2_data =3D { .rchan_cnt =3D 128, }; =20 +static struct udma_match_data pktdma_v2_data =3D { + .type =3D DMA_TYPE_PKTDMA_V2, + .psil_base =3D 0x1000, + .enable_memcpy_support =3D false, /* PKTDMA does not support MEM_TO_MEM */ + .flags =3D UDMA_FLAGS_J7_CLASS, + .statictr_z_mask =3D GENMASK(23, 0), + .burst_size =3D { + TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES, /* Normal Channels */ + 0, /* No H Channels */ + 0, /* No UH Channels */ + }, + .tchan_cnt =3D 97, + .rchan_cnt =3D 97, + .chan_cnt =3D 97, + .tflow_cnt =3D 112, + .rflow_cnt =3D 112, +}; + static const struct of_device_id udma_of_match[] =3D { { .compatible =3D "ti,am62l-dmss-bcdma", .data =3D &bcdma_v2_data, }, + { + .compatible =3D "ti,am62l-dmss-pktdma", + .data =3D &pktdma_v2_data, + }, { /* Sentinel */ }, }; =20 @@ -1014,15 +1178,22 @@ static int udma_v2_get_mmrs(struct platform_device = *pdev, struct udma_dev *ud) if (IS_ERR(ud->mmrs[V2_MMR_GCFG])) return PTR_ERR(ud->mmrs[V2_MMR_GCFG]); =20 - ud->bchan_cnt =3D ud->match_data->bchan_cnt; - /* There are no tchan and rchan in BCDMA_V2. + /* There are no tchan and rchan in BCDMA_V2 and PKTDMA_V2. * Duplicate chan as tchan and rchan to keep the common code - * in k3-udma-common.c functional for BCDMA_V2. + * in k3-udma-common.c functional. */ - ud->chan_cnt =3D ud->match_data->chan_cnt; - ud->tchan_cnt =3D ud->match_data->chan_cnt; - ud->rchan_cnt =3D ud->match_data->chan_cnt; - ud->rflow_cnt =3D ud->chan_cnt; + if (ud->match_data->type =3D=3D DMA_TYPE_BCDMA_V2) { + ud->bchan_cnt =3D ud->match_data->bchan_cnt; + ud->chan_cnt =3D ud->match_data->chan_cnt; + ud->tchan_cnt =3D ud->match_data->chan_cnt; + ud->rchan_cnt =3D ud->match_data->chan_cnt; + ud->rflow_cnt =3D ud->chan_cnt; + } else if (ud->match_data->type =3D=3D DMA_TYPE_PKTDMA_V2) { + ud->chan_cnt =3D ud->match_data->chan_cnt; + ud->tchan_cnt =3D ud->match_data->tchan_cnt; + ud->rchan_cnt =3D ud->match_data->rchan_cnt; + ud->rflow_cnt =3D ud->match_data->rflow_cnt; + } =20 for (i =3D 1; i < V2_MMR_LAST; i++) { if (i =3D=3D V2_MMR_BCHANRT && ud->bchan_cnt =3D=3D 0) @@ -1077,6 +1248,7 @@ static int udma_v2_probe(struct platform_device *pdev) ud->reset_chan =3D udma_v2_reset_chan; ud->decrement_byte_counters =3D udma_v2_decrement_byte_counters; ud->bcdma_setup_sci_resources =3D NULL; + ud->pktdma_setup_sci_resources =3D NULL; =20 ret =3D udma_v2_get_mmrs(pdev, ud); if (ret) @@ -1084,7 +1256,14 @@ static int udma_v2_probe(struct platform_device *pde= v) =20 struct k3_ringacc_init_data ring_init_data =3D {0}; =20 - ring_init_data.num_rings =3D ud->bchan_cnt + ud->chan_cnt; + if (ud->match_data->type =3D=3D DMA_TYPE_BCDMA_V2) { + ring_init_data.num_rings =3D ud->bchan_cnt + ud->chan_cnt; + } else if (ud->match_data->type =3D=3D DMA_TYPE_PKTDMA_V2) { + ring_init_data.num_rings =3D ud->rflow_cnt; + + ud->rflow_rt =3D devm_platform_ioremap_resource_byname(pdev, "ringrt"); + ring_init_data.base_rt =3D ud->rflow_rt; + } =20 ud->ringacc =3D k3_ringacc_dmarings_init(pdev, &ring_init_data); =20 @@ -1093,8 +1272,10 @@ static int udma_v2_probe(struct platform_device *pde= v) =20 dma_cap_set(DMA_SLAVE, ud->ddev.cap_mask); =20 - dma_cap_set(DMA_CYCLIC, ud->ddev.cap_mask); - ud->ddev.device_prep_dma_cyclic =3D udma_prep_dma_cyclic; + if (ud->match_data->type !=3D DMA_TYPE_PKTDMA_V2) { + dma_cap_set(DMA_CYCLIC, ud->ddev.cap_mask); + ud->ddev.device_prep_dma_cyclic =3D udma_prep_dma_cyclic; + } =20 ud->ddev.device_config =3D udma_slave_config; ud->ddev.device_prep_slave_sg =3D udma_prep_slave_sg; @@ -1108,8 +1289,18 @@ static int udma_v2_probe(struct platform_device *pde= v) ud->ddev.dbg_summary_show =3D udma_dbg_summary_show; #endif =20 - ud->ddev.device_alloc_chan_resources =3D - bcdma_v2_alloc_chan_resources; + switch (ud->match_data->type) { + case DMA_TYPE_BCDMA_V2: + ud->ddev.device_alloc_chan_resources =3D + bcdma_v2_alloc_chan_resources; + break; + case DMA_TYPE_PKTDMA_V2: + ud->ddev.device_alloc_chan_resources =3D + pktdma_v2_alloc_chan_resources; + break; + default: + return -EINVAL; + } =20 ud->ddev.device_free_chan_resources =3D udma_free_chan_resources; =20 diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h index c68dbc5df5961..17ffac613a34b 100644 --- a/drivers/dma/ti/k3-udma.h +++ b/drivers/dma/ti/k3-udma.h @@ -23,8 +23,11 @@ #define UDMA_RX_FLOW_ID_FW_OES_REG 0x80 #define UDMA_RX_FLOW_ID_FW_STATUS_REG 0x88 =20 +#define UDMA_RX_FLOWRT_RFA 0x8 + /* BCHANRT/TCHANRT/RCHANRT registers */ #define UDMA_CHAN_RT_CTL_REG 0x0 +#define UDMA_CHAN_RT_CFG_REG 0x4 #define UDMA_CHAN_RT_SWTRIG_REG 0x8 #define UDMA_CHAN_RT_STDATA_REG 0x80 =20 --=20 2.34.1