From nobody Thu Oct 9 02:19:11 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4AF61F2BAB; Mon, 23 Jun 2025 05:38:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750657125; cv=none; b=RkC336fjX5r99sURo7n306569bt2obKgJBBWXTX67X8QFl6PEJ44iST7QLP03sxbOWMSj1aEiHP0g25njfWTeejntjhMl8fAGCfjMjFFo98XX1OSj8G1+0lMWfgVP/Rwszi4AX/qZ0/k4Eg0VGZ5Qpy0jcAWIvQ+eAjtcZpWndk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750657125; c=relaxed/simple; bh=3wPJE/ILkVufjXfL1kZnOVBrTfkNXpRJCei7na7XAB0=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=AS0AIO/rof+N2U5bwaIODvzsnOy883YGRb5a+8WMYfUAw6WDloTd5mjjl+wWOB/h/KYWAwTjfJkArkRx5ZSOa5WAy59HUZ2+mtjVNzgZso8tg1HvAReXJ6xOTUJij3KaaRdmojvaK45rxQwHle+haDi8WOpqt6V1iC8YT9dXtxU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=MUJPdmDE; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="MUJPdmDE" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTP id 55N5cc2k1167954; Mon, 23 Jun 2025 00:38:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1750657118; bh=YdIhzV0m/uQrD1tj9v1Pozpo7cw4jdhzBohKMeP3hqc=; h=From:To:Subject:Date:In-Reply-To:References; b=MUJPdmDESJmme26NgFk87Emdrx1RoAXQ7iZ/m6LleceEBYPsVRgzivsFw1iz7lURl fjnefftwUUo2m76qdWKDImp1hEWC8sEFUzKoeHOOJR8+P7ItcgMSB4JKxlGlUty1KB Nz9p/1Yuu3AJ3z7M/KzV0JONLaPNllvcPbjZlh5w= Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 55N5cch52931867 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 23 Jun 2025 00:38:38 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 23 Jun 2025 00:38:38 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 23 Jun 2025 00:38:37 -0500 Received: from uda0498651.dhcp.ti.com (uda0498651.dhcp.ti.com [172.24.227.7]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 55N5bSqb3428603; Mon, 23 Jun 2025 00:38:33 -0500 From: Sai Sree Kartheek Adivi To: Peter Ujfalusi , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Santosh Shilimkar , Sai Sree Kartheek Adivi , , , , , , , , , Subject: [PATCH v3 12/17] dt-bindings: dma: ti: Add K3 BCDMA V2 Date: Mon, 23 Jun 2025 11:07:11 +0530 Message-ID: <20250623053716.1493974-13-s-adivi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250623053716.1493974-1-s-adivi@ti.com> References: <20250623053716.1493974-1-s-adivi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" New binding document for Texas Instruments K3 Block Copy DMA (BCDMA) V2. BCDMA V2 is introduced as part of AM62L. Signed-off-by: Sai Sree Kartheek Adivi Reviewed-by: Krzysztof Kozlowski --- .../bindings/dma/ti/k3-bcdma-v2.yaml | 94 +++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/ti/k3-bcdma-v2.ya= ml diff --git a/Documentation/devicetree/bindings/dma/ti/k3-bcdma-v2.yaml b/Do= cumentation/devicetree/bindings/dma/ti/k3-bcdma-v2.yaml new file mode 100644 index 0000000000000..c50b2edbf8441 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/ti/k3-bcdma-v2.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2024-2025 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/ti/k3-bcdma-v2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments K3 DMSS BCDMA V2 + +maintainers: + - Sai Sree Kartheek Adivi + +description: | + The BCDMA V2 is intended to perform similar functions as the TR mode cha= nnels + of K3 UDMA-P. BCDMA V2 includes block copy channels and Split channels. + + Block copy channels mainly used for memory to memory transfers, but with + optional triggers a block copy channel can service peripherals by access= ing + directly to memory mapped registers or area. + + Split channels can be used to service PSI-L based peripherals. The perip= herals + can be PSI-L native or legacy, non PSI-L native peripherals with PDMAs. = PDMA + is tasked to act as a bridge between the PSI-L fabric and the legacy per= ipheral. + +allOf: + - $ref: /schemas/dma/dma-controller.yaml# + +properties: + compatible: + const: ti,am62l-dmss-bcdma + + reg: + items: + - description: BCDMA Control /Status + - description: Block Copy Channel Realtime + - description: Channel Realtime + - description: Ring Realtime + + reg-names: + items: + - const: gcfg + - const: bchanrt + - const: chanrt + - const: ringrt + + "#dma-cells": + const: 4 + description: | + cell 1: Trigger type for the channel + 0 - disable / no trigger + 1 - internal channel event + 2 - external signal + 3 - timer manager event + + cell 2: parameter for the trigger: + if cell 1 is 0 (disable / no trigger): + Unused, ignored + if cell 1 is 1 (internal channel event): + channel number whose TR event should trigger the current channel. + if cell 1 is 2 or 3 (external signal or timer manager event): + index of global interfaces that come into the DMA. + + Please refer to the device documentation for global interface in= dexes. + + cell 3: Channel number for the peripheral + + Please refer to the device documentation for the channel map. + + cell 4: ASEL value for the channel + +required: + - compatible + - reg + - reg-names + - "#dma-cells" + +unevaluatedProperties: false + +examples: + - | + main { + #address-cells =3D <2>; + #size-cells =3D <2>; + + dma-controller@485c4000 { + compatible =3D "ti,am62l-dmss-bcdma"; + reg =3D <0x00 0x485c4000 0x00 0x4000>, + <0x00 0x48880000 0x00 0x10000>, + <0x00 0x48800000 0x00 0x80000>, + <0x00 0x47000000 0x00 0x200000>; + reg-names =3D "gcfg", "bchanrt", "chanrt", "ringrt"; + #dma-cells =3D <4>; + }; + }; --=20 2.34.1