From nobody Thu Oct 9 02:19:10 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E2B171F3BA2; Mon, 23 Jun 2025 05:38:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750657126; cv=none; b=DCNlt07abud0rAw4jCKhEM7091+5ZagREu/PXZmZLslHLiOsV+UNsQXx7mHOjq/sCnGnY0XRCpM63McGRoguAxtQ9oKanbf/uELCv6/4nYkFeRvWe/uA7ZNfr5u76CRB+lqWazkTmXOvJ09AYLOBRPGc/FIDk3rPZPXhfnRrdLE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750657126; c=relaxed/simple; bh=NKb2sK+j2Z7yZOa3G+c5QIZXjHkHqKHNvJUPFn6eNCw=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gjn6dhQpHo1v9KV3N27KlEJoH2BdQflrFmwQ1rLLTAbkMTisLuQmb1KZMkq/3fJITd0svyueT9kXLjyoQqUScsuS7qP7iAnPap9vKNC5X1VoJXrcA75v9AkQiAw4OKGITCT4nS/R+L8UHN65zkRmZEvK7ki5AqMYDkpqNMhmkvI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=hfjI+3eK; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="hfjI+3eK" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 55N5cXPh795217; Mon, 23 Jun 2025 00:38:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1750657113; bh=oTaQyFZLkP45VzgeICeeB0stMQxMjzL+e9NXYUfKzBo=; h=From:To:Subject:Date:In-Reply-To:References; b=hfjI+3eK0QBNlxpjuXBU16JTO79fjgTTro4gz8Je1rDLdVwhCsOK5G7fMMYW0X7C8 rpvNZdIMC/HrLyVLI2HTKNWOAZ/0y8U5IuMQS8CsVFydc8a1xCoMsYqYq21KKoTqIP Ialfa6eRWmcPFQ5VqRmz6EO6fLjMgH6+BYfrMOaw= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 55N5cXH32931756 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 23 Jun 2025 00:38:33 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 23 Jun 2025 00:38:32 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 23 Jun 2025 00:38:32 -0500 Received: from uda0498651.dhcp.ti.com (uda0498651.dhcp.ti.com [172.24.227.7]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 55N5bSqa3428603; Mon, 23 Jun 2025 00:38:27 -0500 From: Sai Sree Kartheek Adivi To: Peter Ujfalusi , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Santosh Shilimkar , Sai Sree Kartheek Adivi , , , , , , , , , Subject: [PATCH v3 11/17] drivers: soc: ti: k3-ringacc: handle absence of tisci Date: Mon, 23 Jun 2025 11:07:10 +0530 Message-ID: <20250623053716.1493974-12-s-adivi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250623053716.1493974-1-s-adivi@ti.com> References: <20250623053716.1493974-1-s-adivi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Handle absence of tisci with direct register writes. This will support platforms that do not have tisci firmware like AM62L. Remove TI_SCI_INTA_IRQCHIP dependency for TI_K3_RINGACC in Kconfig as it is required conditionally (only for devices that has TI_SCI). Signed-off-by: Sai Sree Kartheek Adivi --- drivers/soc/ti/Kconfig | 1 - drivers/soc/ti/k3-ringacc.c | 184 ++++++++++++++++++++++++++---- include/linux/soc/ti/k3-ringacc.h | 17 +++ 3 files changed, 177 insertions(+), 25 deletions(-) diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig index 1a93001c9e367..5aa27bc43a81b 100644 --- a/drivers/soc/ti/Kconfig +++ b/drivers/soc/ti/Kconfig @@ -53,7 +53,6 @@ config WKUP_M3_IPC config TI_K3_RINGACC tristate "K3 Ring accelerator Sub System" depends on ARCH_K3 || COMPILE_TEST - depends on TI_SCI_INTA_IRQCHIP help Say y here to support the K3 Ring accelerator module. The Ring Accelerator (RINGACC or RA) provides hardware acceleration diff --git a/drivers/soc/ti/k3-ringacc.c b/drivers/soc/ti/k3-ringacc.c index 7602b8a909b05..e39250d57771f 100644 --- a/drivers/soc/ti/k3-ringacc.c +++ b/drivers/soc/ti/k3-ringacc.c @@ -45,6 +45,49 @@ struct k3_ring_rt_regs { u32 hwindx; }; =20 +#define K3_RINGACC_RT_CFG_REGS_OFS 0x40 +#define K3_DMARING_CFG_ADDR_HI_MASK GENMASK(3, 0) +#define K3_DMARING_CFG_ASEL_SHIFT 16 +#define K3_DMARING_CFG_SIZE_MASK GENMASK(15, 0) + +/** + * struct k3_ring_cfg_regs - The RA Configuration Registers region + * + * @ba_lo: Ring Base Address Low Register + * @ba_hi: Ring Base Address High Register + * @size: Ring Size Register + */ +struct k3_ring_cfg_regs { + u32 ba_lo; + u32 ba_hi; + u32 size; +}; + +#define K3_RINGACC_RT_INT_REGS_OFS 0x140 +#define K3_RINGACC_RT_INT_ENABLE_SET_COMPLETE BIT(0) +#define K3_RINGACC_RT_INT_ENABLE_SET_TR BIT(2) + +/** + * struct k3_rint_intr_regs { + * + * @enable_set: Ring Interrupt Enable Register + * @resv_4: Reserved + * @clr: Ring Interrupt Clear Register + * @resv_16: Reserved + * @status_set: Ring Interrupt Status Set Register + * @resv_8: Reserved + * @status: Ring Interrupt Status Register + */ +struct k3_ring_intr_regs { + u32 enable_set; + u32 resv_4; + u32 clr; + u32 resv_16; + u32 status_set; + u32 resv_8; + u32 status; +}; + #define K3_RINGACC_RT_REGS_STEP 0x1000 #define K3_DMARING_RT_REGS_STEP 0x2000 #define K3_DMARING_RT_REGS_REVERSE_OFS 0x1000 @@ -138,6 +181,8 @@ struct k3_ring_state { * struct k3_ring - RA Ring descriptor * * @rt: Ring control/status registers + * @cfg: Ring config registers + * @intr: Ring interrupt registers * @fifos: Ring queues registers * @proxy: Ring Proxy Datapath registers * @ring_mem_dma: Ring buffer dma address @@ -157,6 +202,8 @@ struct k3_ring_state { */ struct k3_ring { struct k3_ring_rt_regs __iomem *rt; + struct k3_ring_cfg_regs __iomem *cfg; + struct k3_ring_intr_regs __iomem *intr; struct k3_ring_fifo_regs __iomem *fifos; struct k3_ringacc_proxy_target_regs __iomem *proxy; dma_addr_t ring_mem_dma; @@ -466,15 +513,31 @@ static void k3_ringacc_ring_reset_sci(struct k3_ring = *ring) struct k3_ringacc *ringacc =3D ring->parent; int ret; =20 - ring_cfg.nav_id =3D ringacc->tisci_dev_id; - ring_cfg.index =3D ring->ring_id; - ring_cfg.valid_params =3D TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID; - ring_cfg.count =3D ring->size; + if (!ringacc->tisci) { + u32 reg; =20 - ret =3D ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); - if (ret) - dev_err(ringacc->dev, "TISCI reset ring fail (%d) ring_idx %d\n", - ret, ring->ring_id); + if (!ring->cfg) + return; + + reg =3D readl(&ring->cfg->size); + reg &=3D ~K3_DMARING_CFG_SIZE_MASK; + writel(reg, &ring->cfg->size); + + /* Ensure the register clear operation completes before writing new valu= e */ + wmb(); + reg |=3D ring->size; + writel(reg, &ring->cfg->size); + } else { + ring_cfg.nav_id =3D ringacc->tisci_dev_id; + ring_cfg.index =3D ring->ring_id; + ring_cfg.valid_params =3D TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID; + ring_cfg.count =3D ring->size; + + ret =3D ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); + if (ret) + dev_err(ringacc->dev, "TISCI reset ring fail (%d) ring_idx %d\n", + ret, ring->ring_id); + } } =20 void k3_ringacc_ring_reset(struct k3_ring *ring) @@ -500,10 +563,25 @@ static void k3_ringacc_ring_reconfig_qmode_sci(struct= k3_ring *ring, ring_cfg.valid_params =3D TI_SCI_MSG_VALUE_RM_RING_MODE_VALID; ring_cfg.mode =3D mode; =20 - ret =3D ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); - if (ret) - dev_err(ringacc->dev, "TISCI reconf qmode fail (%d) ring_idx %d\n", - ret, ring->ring_id); + if (!ringacc->tisci) { + u32 reg; + + writel(ring_cfg.addr_lo, &ring->cfg->ba_lo); + writel((ring_cfg.addr_hi & K3_DMARING_CFG_ADDR_HI_MASK) + + (ring_cfg.asel << K3_DMARING_CFG_ASEL_SHIFT), + &ring->cfg->ba_hi); + + reg =3D readl(&ring->cfg->size); + reg &=3D ~K3_DMARING_CFG_SIZE_MASK; + reg |=3D ring_cfg.count & K3_DMARING_CFG_SIZE_MASK; + + writel(reg, &ring->cfg->size); + } else { + ret =3D ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); + if (ret) + dev_err(ringacc->dev, "TISCI reconf qmode fail (%d) ring_idx %d\n", + ret, ring->ring_id); + } } =20 void k3_ringacc_ring_reset_dma(struct k3_ring *ring, u32 occ) @@ -575,10 +653,25 @@ static void k3_ringacc_ring_free_sci(struct k3_ring *= ring) ring_cfg.index =3D ring->ring_id; ring_cfg.valid_params =3D TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER; =20 - ret =3D ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); - if (ret) - dev_err(ringacc->dev, "TISCI ring free fail (%d) ring_idx %d\n", - ret, ring->ring_id); + if (!ringacc->tisci) { + u32 reg; + + writel(ring_cfg.addr_lo, &ring->cfg->ba_lo); + writel((ring_cfg.addr_hi & K3_DMARING_CFG_ADDR_HI_MASK) + + (ring_cfg.asel << K3_DMARING_CFG_ASEL_SHIFT), + &ring->cfg->ba_hi); + + reg =3D readl(&ring->cfg->size); + reg &=3D ~K3_DMARING_CFG_SIZE_MASK; + reg |=3D ring_cfg.count & K3_DMARING_CFG_SIZE_MASK; + + writel(reg, &ring->cfg->size); + } else { + ret =3D ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); + if (ret) + dev_err(ringacc->dev, "TISCI ring free fail (%d) ring_idx %d\n", + ret, ring->ring_id); + } } =20 int k3_ringacc_ring_free(struct k3_ring *ring) @@ -669,15 +762,30 @@ int k3_ringacc_get_ring_irq_num(struct k3_ring *ring) } EXPORT_SYMBOL_GPL(k3_ringacc_get_ring_irq_num); =20 +u32 k3_ringacc_ring_get_irq_status(struct k3_ring *ring) +{ + struct k3_ringacc *ringacc =3D ring->parent; + struct k3_ring *ring2 =3D &ringacc->rings[ring->ring_id]; + + return readl(&ring2->intr->status); +} +EXPORT_SYMBOL_GPL(k3_ringacc_ring_get_irq_status); + +void k3_ringacc_ring_clear_irq(struct k3_ring *ring) +{ + struct k3_ringacc *ringacc =3D ring->parent; + struct k3_ring *ring2 =3D &ringacc->rings[ring->ring_id]; + + writel(0xFF, &ring2->intr->status); +} +EXPORT_SYMBOL_GPL(k3_ringacc_ring_clear_irq); + static int k3_ringacc_ring_cfg_sci(struct k3_ring *ring) { struct ti_sci_msg_rm_ring_cfg ring_cfg =3D { 0 }; struct k3_ringacc *ringacc =3D ring->parent; int ret; =20 - if (!ringacc->tisci) - return -EINVAL; - ring_cfg.nav_id =3D ringacc->tisci_dev_id; ring_cfg.index =3D ring->ring_id; ring_cfg.valid_params =3D TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER; @@ -688,6 +796,24 @@ static int k3_ringacc_ring_cfg_sci(struct k3_ring *rin= g) ring_cfg.size =3D ring->elm_size; ring_cfg.asel =3D ring->asel; =20 + if (!ringacc->tisci) { + u32 reg; + + writel(ring_cfg.addr_lo, &ring->cfg->ba_lo); + writel((ring_cfg.addr_hi & K3_DMARING_CFG_ADDR_HI_MASK) + + (ring_cfg.asel << K3_DMARING_CFG_ASEL_SHIFT), + &ring->cfg->ba_hi); + + reg =3D readl(&ring->cfg->size); + reg &=3D ~K3_DMARING_CFG_SIZE_MASK; + reg |=3D ring_cfg.count & K3_DMARING_CFG_SIZE_MASK; + + writel(reg, &ring->cfg->size); + writel(K3_RINGACC_RT_INT_ENABLE_SET_COMPLETE | K3_RINGACC_RT_INT_ENABLE_= SET_TR, + &ring->intr->enable_set); + return 0; + } + ret =3D ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); if (ret) dev_err(ringacc->dev, "TISCI config ring fail (%d) ring_idx %d\n", @@ -1346,8 +1472,11 @@ static int k3_ringacc_probe_dt(struct k3_ringacc *ri= ngacc) return PTR_ERR(ringacc->rm_gp_range); } =20 - return ti_sci_inta_msi_domain_alloc_irqs(ringacc->dev, - ringacc->rm_gp_range); + if (IS_ENABLED(CONFIG_TI_K3_UDMA)) + return ti_sci_inta_msi_domain_alloc_irqs(ringacc->dev, + ringacc->rm_gp_range); + else + return 0; } =20 static const struct k3_ringacc_soc_data k3_ringacc_soc_data_sr1 =3D { @@ -1480,9 +1609,12 @@ struct k3_ringacc *k3_ringacc_dmarings_init(struct p= latform_device *pdev, =20 mutex_init(&ringacc->req_lock); =20 - base_rt =3D devm_platform_ioremap_resource_byname(pdev, "ringrt"); - if (IS_ERR(base_rt)) - return ERR_CAST(base_rt); + base_rt =3D data->base_rt; + if (!base_rt) { + base_rt =3D devm_platform_ioremap_resource_byname(pdev, "ringrt"); + if (IS_ERR(base_rt)) + return ERR_CAST(base_rt); + } =20 ringacc->rings =3D devm_kzalloc(dev, sizeof(*ringacc->rings) * @@ -1498,6 +1630,10 @@ struct k3_ringacc *k3_ringacc_dmarings_init(struct p= latform_device *pdev, struct k3_ring *ring =3D &ringacc->rings[i]; =20 ring->rt =3D base_rt + K3_DMARING_RT_REGS_STEP * i; + ring->cfg =3D base_rt + K3_RINGACC_RT_CFG_REGS_OFS + + K3_DMARING_RT_REGS_STEP * i; + ring->intr =3D base_rt + K3_RINGACC_RT_INT_REGS_OFS + + K3_DMARING_RT_REGS_STEP * i; ring->parent =3D ringacc; ring->ring_id =3D i; ring->proxy_id =3D K3_RINGACC_PROXY_NOT_USED; diff --git a/include/linux/soc/ti/k3-ringacc.h b/include/linux/soc/ti/k3-ri= ngacc.h index 39b022b925986..9f2d141c988bd 100644 --- a/include/linux/soc/ti/k3-ringacc.h +++ b/include/linux/soc/ti/k3-ringacc.h @@ -158,6 +158,22 @@ u32 k3_ringacc_get_ring_id(struct k3_ring *ring); */ int k3_ringacc_get_ring_irq_num(struct k3_ring *ring); =20 +/** + * k3_ringacc_ring_get_irq_status - Get the irq status for the ring + * @ring: pointer on ring + * + * Returns the interrupt status + */ +u32 k3_ringacc_ring_get_irq_status(struct k3_ring *ring); + +/** + * k3_ringacc_ring_clear_irq - Clear all interrupts + * @ring: pointer on ring + * + * Clears all the interrupts on the ring + */ +void k3_ringacc_ring_clear_irq(struct k3_ring *ring); + /** * k3_ringacc_ring_cfg - ring configure * @ring: pointer on ring @@ -262,6 +278,7 @@ struct k3_ringacc_init_data { const struct ti_sci_handle *tisci; u32 tisci_dev_id; u32 num_rings; + void __iomem *base_rt; }; =20 struct k3_ringacc *k3_ringacc_dmarings_init(struct platform_device *pdev, --=20 2.34.1