From nobody Wed Oct 8 22:19:01 2025 Received: from todd.t-8ch.de (todd.t-8ch.de [159.69.126.157]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5DB721B9C9; Mon, 23 Jun 2025 21:25:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.69.126.157 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750713946; cv=none; b=NaNuBIv4TZ/xziOyiOuQAXxQakbb/3z/U2Et74JriOzx8betGZXccEdCC9nEL/sLXo0E7irb5FvBMrwIc5A3cxzmWXlgHywSqHJBiNplKDQNqXGGvlBbPl8Ww1Ro2pfdQLOMFwagrZ23iUyLyYLBiFuK0fVHrWVm0MxoD8VX/WA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750713946; c=relaxed/simple; bh=98CrYfiF4BtrJsy4mcJlUCMY0HAKCKJDc4QFtC0CKUs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TzabqLZx1JfR/OGe6mWeFPrrQKT3c+NCaMC7CcVhxc3mlRoA34VlFLbpHQAB7bGQPhvg+YNQkvRpYqeXogu4nC5IolX90MxooC5fNbQJ5qeXYFjPNPA5g6iYKovI8yutkBzPkLFc5cUy+qDS/jN0REBYuiEiol8LPfgV5yLD41s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=weissschuh.net; spf=pass smtp.mailfrom=weissschuh.net; dkim=pass (1024-bit key) header.d=weissschuh.net header.i=@weissschuh.net header.b=I1TjsbgX; arc=none smtp.client-ip=159.69.126.157 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=weissschuh.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=weissschuh.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=weissschuh.net header.i=@weissschuh.net header.b="I1TjsbgX" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=weissschuh.net; s=mail; t=1750713942; bh=98CrYfiF4BtrJsy4mcJlUCMY0HAKCKJDc4QFtC0CKUs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=I1TjsbgXXK9fHk4KfpiRfGOnRNwphCmIif/IIkTvOi0Unj2PsnjzKLzmekjHo2RFJ XXKpuKFTNVtM7rnK8aQh/uUK6BjwDqOlaXq6RngkA+P5T5hto/Me3HNK+NwJzsLyqc 8S4frozUVkRza2GKCo9y64doo7NQMkShtPg/NA3I= From: =?utf-8?q?Thomas_Wei=C3=9Fschuh?= Date: Mon, 23 Jun 2025 23:25:36 +0200 Subject: [PATCH v3 1/4] tools/nolibc: MIPS: drop $gp setup Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250623-nolibc-mips-n32-v3-1-6ae2d89f4259@weissschuh.net> References: <20250623-nolibc-mips-n32-v3-0-6ae2d89f4259@weissschuh.net> In-Reply-To: <20250623-nolibc-mips-n32-v3-0-6ae2d89f4259@weissschuh.net> To: Willy Tarreau , Shuah Khan , Thomas Bogendoerfer , "Maciej W. Rozycki" Cc: Sebastian Andrzej Siewior , linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-mips@vger.kernel.org, =?utf-8?q?Thomas_Wei=C3=9Fschuh?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750713941; l=1658; i=linux@weissschuh.net; s=20221212; h=from:subject:message-id; bh=98CrYfiF4BtrJsy4mcJlUCMY0HAKCKJDc4QFtC0CKUs=; b=DK0FRPqX+11S7qlrhNy8SVQa/50ciVSsZU6ZHmlvqk4wFbgs9FFjgmrYGgQeaAkQZhWRb1W7F XFFiin8uqUyD6oPsbVcUOyCHUvpx6I/Wa6q5uaEfXCK32qHUEOeQAiI X-Developer-Key: i=linux@weissschuh.net; a=ed25519; pk=KcycQgFPX2wGR5azS7RhpBqedglOZVgRPfdFSPB1LNw= The setup of the global pointer "$gp" register was necessary when the C entrypoint was called through "jal ". However since commit 0daf8c86a451 ("tools/nolibc: mips: load current functi= on to $t9") "jalr" is used instead which does not require "$gp". Remove the unnecessary $gp setup, simplifying the code and opening the road for some other cleanups. Suggested-by: Maciej W. Rozycki Link: https://lore.kernel.org/lkml/alpine.DEB.2.21.2502172208570.65342@angi= e.orcam.me.uk/ Signed-off-by: Thomas Wei=C3=9Fschuh Tested-by: Sebastian Andrzej Siewior --- tools/include/nolibc/arch-mips.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/tools/include/nolibc/arch-mips.h b/tools/include/nolibc/arch-m= ips.h index 753a8ed2cf695f0b5eac4b5e4d317fdb383ebf93..6d023d9f120301b2d6837c923c1= 42ab2cf87ae5a 100644 --- a/tools/include/nolibc/arch-mips.h +++ b/tools/include/nolibc/arch-mips.h @@ -185,13 +185,7 @@ void __attribute__((weak, noreturn)) __nolibc_entrypoi= nt __no_stack_protector __ __asm__ volatile ( ".set push\n" ".set noreorder\n" - "bal 1f\n" /* prime $ra for .cpload = */ - "nop\n" - "1:\n" - ".cpload $ra\n" "move $a0, $sp\n" /* save stack pointer to $a0, as arg1 of _start= _c */ - "addiu $sp, $sp, -4\n" /* space for .cprestore to store $gp = */ - ".cprestore 0\n" "li $t0, -8\n" "and $sp, $sp, $t0\n" /* $sp must be 8-byte aligned = */ "addiu $sp, $sp, -16\n" /* the callee expects to save a0..a3 there = */ --=20 2.50.0 From nobody Wed Oct 8 22:19:01 2025 Received: from todd.t-8ch.de (todd.t-8ch.de [159.69.126.157]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FD5721FF50; Mon, 23 Jun 2025 21:25:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.69.126.157 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750713946; cv=none; b=Bdpsl4wuygUHJqoLqA7jRDSSiyO1qiDr2IXXN93uTDX//FiLFckPqjPaP3b19h2nQzeCUhookFOMegExaz4LWNNWIpuAGSB9O514YA+JfOOCfTNUURj5duprkCqfiEcQmoolUcWptTivVadOkTpLlCDHGhjzYZEx+udQmQXrEKs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750713946; c=relaxed/simple; bh=K4401D/s9X8trfbLrKrkvgktSNGSmeMc0zrERdDGY3o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=myJQcSBmLdlWe9JpLFFnE5MMiYdOR90oNOPzrTyJwHpbZifxNm3VDZSlpVCVqRhlx4OZ6b+MrMiRulMsOI2B9uiwM6HZ7BxvRKKNsKUQ94N5PdXpBxtkQ8fXgAHJbxb8VCdqBixe9BvoyuDfcMPWQYRabmADwK+skAK1T++jDDw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=weissschuh.net; spf=pass smtp.mailfrom=weissschuh.net; dkim=pass (1024-bit key) header.d=weissschuh.net header.i=@weissschuh.net header.b=Ii9HZmjt; arc=none smtp.client-ip=159.69.126.157 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=weissschuh.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=weissschuh.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=weissschuh.net header.i=@weissschuh.net header.b="Ii9HZmjt" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=weissschuh.net; s=mail; t=1750713942; bh=K4401D/s9X8trfbLrKrkvgktSNGSmeMc0zrERdDGY3o=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Ii9HZmjtJ1vzUHdZiyIfbR4GqgwIynWJh4u6bWLGRCOar7vU6FaeF1iggMqHIxTxT l7hytbqGtMPIhZBLN1oBoQX5Tmrs4d7Ywm2bCEbeqcVK6ik3QkGz3t4dnEr9sguz5h fvdbrooGK5fG3wCFg6ukSbamNvrBkU3h754DPfJI= From: =?utf-8?q?Thomas_Wei=C3=9Fschuh?= Date: Mon, 23 Jun 2025 23:25:37 +0200 Subject: [PATCH v3 2/4] tools/nolibc: MIPS: drop manual stack pointer alignment Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250623-nolibc-mips-n32-v3-2-6ae2d89f4259@weissschuh.net> References: <20250623-nolibc-mips-n32-v3-0-6ae2d89f4259@weissschuh.net> In-Reply-To: <20250623-nolibc-mips-n32-v3-0-6ae2d89f4259@weissschuh.net> To: Willy Tarreau , Shuah Khan , Thomas Bogendoerfer , "Maciej W. Rozycki" Cc: Sebastian Andrzej Siewior , linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-mips@vger.kernel.org, =?utf-8?q?Thomas_Wei=C3=9Fschuh?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750713941; l=1367; i=linux@weissschuh.net; s=20221212; h=from:subject:message-id; bh=K4401D/s9X8trfbLrKrkvgktSNGSmeMc0zrERdDGY3o=; b=e+vX5aMPOhXOax9UhDwDZCV86w/LuP0z/Zp8WYsdiiuEu6dGlDugQGpSBk3IcpEOZp3x1Nc4L nwEZF3ibA71A4VjAftT13g2pRyRTJRzq/UOmi178qv5CGX01acRv6S3 X-Developer-Key: i=linux@weissschuh.net; a=ed25519; pk=KcycQgFPX2wGR5azS7RhpBqedglOZVgRPfdFSPB1LNw= The stack pointer is already aligned by the kernel to a multiple of 16. All modifications of the register have been removed from the entrypoint, so the manual realignment is unnecessary. Drop the manual alignment. Suggested-by: Maciej W. Rozycki Link: https://lore.kernel.org/lkml/alpine.DEB.2.21.2502161523290.65342@angi= e.orcam.me.uk/ Signed-off-by: Thomas Wei=C3=9Fschuh Tested-by: Sebastian Andrzej Siewior --- tools/include/nolibc/arch-mips.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/tools/include/nolibc/arch-mips.h b/tools/include/nolibc/arch-m= ips.h index 6d023d9f120301b2d6837c923c142ab2cf87ae5a..0776de7574b451aeb34531bc469= 6c7bd9b694268 100644 --- a/tools/include/nolibc/arch-mips.h +++ b/tools/include/nolibc/arch-mips.h @@ -186,8 +186,6 @@ void __attribute__((weak, noreturn)) __nolibc_entrypoin= t __no_stack_protector __ ".set push\n" ".set noreorder\n" "move $a0, $sp\n" /* save stack pointer to $a0, as arg1 of _start= _c */ - "li $t0, -8\n" - "and $sp, $sp, $t0\n" /* $sp must be 8-byte aligned = */ "addiu $sp, $sp, -16\n" /* the callee expects to save a0..a3 there = */ "lui $t9, %hi(_start_c)\n" /* ABI requires current function address in $= t9 */ "ori $t9, %lo(_start_c)\n" --=20 2.50.0 From nobody Wed Oct 8 22:19:01 2025 Received: from todd.t-8ch.de (todd.t-8ch.de [159.69.126.157]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34BAD1EEA3C; Mon, 23 Jun 2025 21:25:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.69.126.157 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750713946; cv=none; b=gltKdp9/lM13KgBdP6hoadzNSlRGTJnBo0EsXU+zL3qvH00pk95hS1itBmp0wKvnmKT68HJPwTY4erz0kdN9vYTzJ20YoRdAi8pjmPVFObY7KejVufu5/BWdsl54BqEiRdCGP1RO3jnps1MCYkBHMt3+hHtP1j3QRsxKXRm2Ls8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750713946; c=relaxed/simple; bh=SA23DUA65m1dGBqAcEo41euuXPrElMD5TLx7znnGhkA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RE8sBb9dlb6ppJP6ouyQ8OnbfuTvPZJl/nlsGJFVSrm3kEgH32AE2CCzEeGVSXz8ArFSnya33US2EqshWTl2LfScYml1NH9fhYSxMynkrW23lmAbw/XLi/lh6LvQ02PRvI7NxvQU8Jkm6vgtO5B2NQLmGXx58djFjyKlW6gmOSw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=weissschuh.net; spf=pass smtp.mailfrom=weissschuh.net; dkim=pass (1024-bit key) header.d=weissschuh.net header.i=@weissschuh.net header.b=hHskGiBO; arc=none smtp.client-ip=159.69.126.157 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=weissschuh.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=weissschuh.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=weissschuh.net header.i=@weissschuh.net header.b="hHskGiBO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=weissschuh.net; s=mail; t=1750713942; bh=SA23DUA65m1dGBqAcEo41euuXPrElMD5TLx7znnGhkA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=hHskGiBOUaOxBluiH2gxS4QMRHYVgiDSqwhPe0rJZxuTz3Es+Ql5mYaDL96YeKKo2 0ETzstdJE8/zdngrmxiMy0dYDGl1kk5l7Aam91He4Aw87j/LBFzagppcttFJ3l0lZR WSDOj4NCZaapCCCWRUayXjsz4Y4mHWnl2THlbNCc= From: =?utf-8?q?Thomas_Wei=C3=9Fschuh?= Date: Mon, 23 Jun 2025 23:25:38 +0200 Subject: [PATCH v3 3/4] tools/nolibc: MIPS: drop noreorder option Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250623-nolibc-mips-n32-v3-3-6ae2d89f4259@weissschuh.net> References: <20250623-nolibc-mips-n32-v3-0-6ae2d89f4259@weissschuh.net> In-Reply-To: <20250623-nolibc-mips-n32-v3-0-6ae2d89f4259@weissschuh.net> To: Willy Tarreau , Shuah Khan , Thomas Bogendoerfer , "Maciej W. Rozycki" Cc: Sebastian Andrzej Siewior , linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-mips@vger.kernel.org, =?utf-8?q?Thomas_Wei=C3=9Fschuh?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750713941; l=1537; i=linux@weissschuh.net; s=20221212; h=from:subject:message-id; bh=SA23DUA65m1dGBqAcEo41euuXPrElMD5TLx7znnGhkA=; b=IvUwZdvvp82+e6RX8ICmudXsXZwwkixB+udr4AyjcliugVTFobYX1hu+dX8aeoWsdJ5Eee4HN WdCYOMk4jl8DiuDUheUVadYFrJx/hWPNVRxR1kdSuW5mCol1yNTnfMf X-Developer-Key: i=linux@weissschuh.net; a=ed25519; pk=KcycQgFPX2wGR5azS7RhpBqedglOZVgRPfdFSPB1LNw= There are no more statements in the assembly code which would require the usage of ".set noreorder". Remove the option. This also allows removal of the manual "nop" instruction in the delay slot. Suggested-by: Maciej W. Rozycki Link: https://lore.kernel.org/lkml/alpine.DEB.2.21.2502172208570.65342@angi= e.orcam.me.uk/ Signed-off-by: Thomas Wei=C3=9Fschuh Tested-by: Sebastian Andrzej Siewior --- tools/include/nolibc/arch-mips.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/tools/include/nolibc/arch-mips.h b/tools/include/nolibc/arch-m= ips.h index 0776de7574b451aeb34531bc4696c7bd9b694268..4f0b969f66af610d3c986f3ff0e= 1c3f3a0be16b5 100644 --- a/tools/include/nolibc/arch-mips.h +++ b/tools/include/nolibc/arch-mips.h @@ -183,15 +183,11 @@ void __start(void); void __attribute__((weak, noreturn)) __nolibc_entrypoint __no_stack_protec= tor __start(void) { __asm__ volatile ( - ".set push\n" - ".set noreorder\n" "move $a0, $sp\n" /* save stack pointer to $a0, as arg1 of _start= _c */ "addiu $sp, $sp, -16\n" /* the callee expects to save a0..a3 there = */ "lui $t9, %hi(_start_c)\n" /* ABI requires current function address in $= t9 */ "ori $t9, %lo(_start_c)\n" "jalr $t9\n" /* transfer to c runtime = */ - " nop\n" /* delayed slot = */ - ".set pop\n" ); __nolibc_entrypoint_epilogue(); } --=20 2.50.0 From nobody Wed Oct 8 22:19:01 2025 Received: from todd.t-8ch.de (todd.t-8ch.de [159.69.126.157]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B47D1E51FA; Mon, 23 Jun 2025 21:25:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.69.126.157 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750713946; cv=none; b=l/4dOl9AoVBNvhqH2U+0kAy6ljU5lESy5l2CxJ75C4v8Omg5ODjsxXvFf1LSD9wiglQ+J1BatgktjlGtgtEyc5YQBlFd0S2CKDxPMfRn6JniOLQrka3G02xTgfWhRRQuYO3g1ZkvPaUzmf8b60eU+9V13IV387em3TLccOK9j0I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750713946; c=relaxed/simple; bh=UeQDK9ENQ7vUtQyrUkOq5dcJzYpYWfOhsPHIfj1iITM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cBIwq0UIWR2sMHZmANyHLNbFyzGZKSGIcgY0JCWb6xwQodODB5Rom2olbyGkJaeWsWwx+azeROkR5R0lENd0DC5s6wcQAP4qiO/Q0gorl/K5CAIoTmYjopYgZPdYVdpyZ6TRnE08+iou4XIY/W3yaMBuMdOStldma5+SFm/+9BM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=weissschuh.net; spf=pass smtp.mailfrom=weissschuh.net; dkim=pass (1024-bit key) header.d=weissschuh.net header.i=@weissschuh.net header.b=CoxXizIW; arc=none smtp.client-ip=159.69.126.157 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=weissschuh.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=weissschuh.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=weissschuh.net header.i=@weissschuh.net header.b="CoxXizIW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=weissschuh.net; s=mail; t=1750713942; bh=UeQDK9ENQ7vUtQyrUkOq5dcJzYpYWfOhsPHIfj1iITM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=CoxXizIW+zt23YgX9hL6aDtyR+6dStg/ArgBUfBGU+NvbJa/SrbWXY2oRjP5gqI2m VyjAVfHA4J706yFRVCR4jgNw2DGoqp1i0eQcQTczeV/msqMA4tkaV/DeqBPFG1c0Jv +Ek5aRkMm/QUWu6wtkihp592R/E81shvYqY2F6BU= From: =?utf-8?q?Thomas_Wei=C3=9Fschuh?= Date: Mon, 23 Jun 2025 23:25:39 +0200 Subject: [PATCH v3 4/4] tools/nolibc: MIPS: add support for N64 and N32 ABIs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250623-nolibc-mips-n32-v3-4-6ae2d89f4259@weissschuh.net> References: <20250623-nolibc-mips-n32-v3-0-6ae2d89f4259@weissschuh.net> In-Reply-To: <20250623-nolibc-mips-n32-v3-0-6ae2d89f4259@weissschuh.net> To: Willy Tarreau , Shuah Khan , Thomas Bogendoerfer , "Maciej W. Rozycki" Cc: Sebastian Andrzej Siewior , linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-mips@vger.kernel.org, =?utf-8?q?Thomas_Wei=C3=9Fschuh?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750713941; l=15927; i=linux@weissschuh.net; s=20221212; h=from:subject:message-id; bh=UeQDK9ENQ7vUtQyrUkOq5dcJzYpYWfOhsPHIfj1iITM=; b=eh141JVPYa/Hx3BdzR2cslKxpOvpD/40HYaLrS0vPt2xxDo7mm9I29mAbnesO9Xjqc56nLXd+ OChk5v/lnOSD+YtP9o2n8Z/boEd740VwuOVZLqfg2KJqupexatsMqMj X-Developer-Key: i=linux@weissschuh.net; a=ed25519; pk=KcycQgFPX2wGR5azS7RhpBqedglOZVgRPfdFSPB1LNw= Add support for the MIPS 64bit N64 and ILP32 N32 ABIs. In addition to different byte orders and ABIs there are also different releases of the MIPS architecture. To avoid blowing up the test matrix, only add a subset of all possible test combinations. Signed-off-by: Thomas Wei=C3=9Fschuh Tested-by: Sebastian Andrzej Siewior --- tools/include/nolibc/arch-mips.h | 105 +++++++++++++++++++++= ---- tools/testing/selftests/nolibc/Makefile.nolibc | 26 ++++++ tools/testing/selftests/nolibc/run-tests.sh | 2 +- 3 files changed, 117 insertions(+), 16 deletions(-) diff --git a/tools/include/nolibc/arch-mips.h b/tools/include/nolibc/arch-m= ips.h index 4f0b969f66af610d3c986f3ff0e1c3f3a0be16b5..0cbac63b249adf80ecbf70ba074= f9ea5d56d9278 100644 --- a/tools/include/nolibc/arch-mips.h +++ b/tools/include/nolibc/arch-mips.h @@ -10,7 +10,7 @@ #include "compiler.h" #include "crt.h" =20 -#if !defined(_ABIO32) +#if !defined(_ABIO32) && !defined(_ABIN32) && !defined(_ABI64) #error Unsupported MIPS ABI #endif =20 @@ -32,11 +32,32 @@ * - the arguments are cast to long and assigned into the target registe= rs * which are then simply passed as registers to the asm code, so that = we * don't have to experience issues with register constraints. + * + * Syscalls for MIPS ABI N32, same as ABI O32 with the following differenc= es : + * - arguments are in a0, a1, a2, a3, t0, t1, t2, t3. + * t0..t3 are also known as a4..a7. + * - stack is 16-byte aligned */ =20 +#if defined(_ABIO32) + #define _NOLIBC_SYSCALL_CLOBBERLIST \ "memory", "cc", "at", "v1", "hi", "lo", \ "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", "t8", "t9" +#define _NOLIBC_SYSCALL_STACK_RESERVE "addiu $sp, $sp, -32\n" +#define _NOLIBC_SYSCALL_STACK_UNRESERVE "addiu $sp, $sp, 32\n" + +#else /* _ABIN32 || _ABI64 */ + +/* binutils, GCC and clang disagree about register aliases, use numbers in= stead. */ +#define _NOLIBC_SYSCALL_CLOBBERLIST \ + "memory", "cc", "at", "v1", \ + "10", "11", "12", "13", "14", "15", "24", "25" + +#define _NOLIBC_SYSCALL_STACK_RESERVE +#define _NOLIBC_SYSCALL_STACK_UNRESERVE + +#endif /* _ABIO32 */ =20 #define my_syscall0(num) = \ ({ = \ @@ -44,9 +65,9 @@ register long _arg4 __asm__ ("a3"); \ \ __asm__ volatile ( \ - "addiu $sp, $sp, -32\n" \ + _NOLIBC_SYSCALL_STACK_RESERVE \ "syscall\n" \ - "addiu $sp, $sp, 32\n" \ + _NOLIBC_SYSCALL_STACK_UNRESERVE \ : "=3Dr"(_num), "=3Dr"(_arg4) \ : "r"(_num) \ : _NOLIBC_SYSCALL_CLOBBERLIST \ @@ -61,9 +82,9 @@ register long _arg4 __asm__ ("a3"); \ \ __asm__ volatile ( \ - "addiu $sp, $sp, -32\n" \ + _NOLIBC_SYSCALL_STACK_RESERVE \ "syscall\n" \ - "addiu $sp, $sp, 32\n" \ + _NOLIBC_SYSCALL_STACK_UNRESERVE \ : "=3Dr"(_num), "=3Dr"(_arg4) \ : "0"(_num), \ "r"(_arg1) \ @@ -80,9 +101,9 @@ register long _arg4 __asm__ ("a3"); \ \ __asm__ volatile ( \ - "addiu $sp, $sp, -32\n" \ + _NOLIBC_SYSCALL_STACK_RESERVE \ "syscall\n" \ - "addiu $sp, $sp, 32\n" \ + _NOLIBC_SYSCALL_STACK_UNRESERVE \ : "=3Dr"(_num), "=3Dr"(_arg4) \ : "0"(_num), \ "r"(_arg1), "r"(_arg2) \ @@ -100,9 +121,9 @@ register long _arg4 __asm__ ("a3"); \ \ __asm__ volatile ( \ - "addiu $sp, $sp, -32\n" \ + _NOLIBC_SYSCALL_STACK_RESERVE \ "syscall\n" \ - "addiu $sp, $sp, 32\n" \ + _NOLIBC_SYSCALL_STACK_UNRESERVE \ : "=3Dr"(_num), "=3Dr"(_arg4) \ : "0"(_num), \ "r"(_arg1), "r"(_arg2), "r"(_arg3) \ @@ -120,9 +141,9 @@ register long _arg4 __asm__ ("a3") =3D (long)(arg4); \ \ __asm__ volatile ( \ - "addiu $sp, $sp, -32\n" \ + _NOLIBC_SYSCALL_STACK_RESERVE \ "syscall\n" \ - "addiu $sp, $sp, 32\n" \ + _NOLIBC_SYSCALL_STACK_UNRESERVE \ : "=3Dr" (_num), "=3Dr"(_arg4) \ : "0"(_num), \ "r"(_arg1), "r"(_arg2), "r"(_arg3), "r"(_arg4) \ @@ -131,6 +152,8 @@ _arg4 ? -_num : _num; \ }) =20 +#if defined(_ABIO32) + #define my_syscall5(num, arg1, arg2, arg3, arg4, arg5) = \ ({ = \ register long _num __asm__ ("v0") =3D (num); \ @@ -141,10 +164,10 @@ register long _arg5 =3D (long)(arg5); \ \ __asm__ volatile ( \ - "addiu $sp, $sp, -32\n" \ + _NOLIBC_SYSCALL_STACK_RESERVE \ "sw %7, 16($sp)\n" \ "syscall\n" \ - "addiu $sp, $sp, 32\n" \ + _NOLIBC_SYSCALL_STACK_UNRESERVE \ : "=3Dr" (_num), "=3Dr"(_arg4) \ : "0"(_num), \ "r"(_arg1), "r"(_arg2), "r"(_arg3), "r"(_arg4), "r"(_arg5) \ @@ -164,11 +187,53 @@ register long _arg6 =3D (long)(arg6); \ \ __asm__ volatile ( \ - "addiu $sp, $sp, -32\n" \ + _NOLIBC_SYSCALL_STACK_RESERVE \ "sw %7, 16($sp)\n" \ "sw %8, 20($sp)\n" \ "syscall\n" \ - "addiu $sp, $sp, 32\n" \ + _NOLIBC_SYSCALL_STACK_UNRESERVE \ + : "=3Dr" (_num), "=3Dr"(_arg4) \ + : "0"(_num), \ + "r"(_arg1), "r"(_arg2), "r"(_arg3), "r"(_arg4), "r"(_arg5), \ + "r"(_arg6) \ + : _NOLIBC_SYSCALL_CLOBBERLIST \ + ); \ + _arg4 ? -_num : _num; \ +}) + +#else /* _ABIN32 || _ABI64 */ + +#define my_syscall5(num, arg1, arg2, arg3, arg4, arg5) = \ +({ = \ + register long _num __asm__ ("v0") =3D (num); \ + register long _arg1 __asm__ ("$4") =3D (long)(arg1); \ + register long _arg2 __asm__ ("$5") =3D (long)(arg2); \ + register long _arg3 __asm__ ("$6") =3D (long)(arg3); \ + register long _arg4 __asm__ ("$7") =3D (long)(arg4); \ + register long _arg5 __asm__ ("$8") =3D (long)(arg5); \ + \ + __asm__ volatile ( \ + "syscall\n" \ + : "=3Dr" (_num), "=3Dr"(_arg4) \ + : "0"(_num), \ + "r"(_arg1), "r"(_arg2), "r"(_arg3), "r"(_arg4), "r"(_arg5) \ + : _NOLIBC_SYSCALL_CLOBBERLIST \ + ); \ + _arg4 ? -_num : _num; \ +}) + +#define my_syscall6(num, arg1, arg2, arg3, arg4, arg5, arg6) = \ +({ = \ + register long _num __asm__ ("v0") =3D (num); \ + register long _arg1 __asm__ ("$4") =3D (long)(arg1); \ + register long _arg2 __asm__ ("$5") =3D (long)(arg2); \ + register long _arg3 __asm__ ("$6") =3D (long)(arg3); \ + register long _arg4 __asm__ ("$7") =3D (long)(arg4); \ + register long _arg5 __asm__ ("$8") =3D (long)(arg5); \ + register long _arg6 __asm__ ("$9") =3D (long)(arg6); \ + \ + __asm__ volatile ( \ + "syscall\n" \ : "=3Dr" (_num), "=3Dr"(_arg4) \ : "0"(_num), \ "r"(_arg1), "r"(_arg2), "r"(_arg3), "r"(_arg4), "r"(_arg5), \ @@ -178,15 +243,25 @@ _arg4 ? -_num : _num; \ }) =20 +#endif /* _ABIO32 */ + /* startup code, note that it's called __start on MIPS */ void __start(void); void __attribute__((weak, noreturn)) __nolibc_entrypoint __no_stack_protec= tor __start(void) { __asm__ volatile ( "move $a0, $sp\n" /* save stack pointer to $a0, as arg1 of _start= _c */ +#if defined(_ABIO32) "addiu $sp, $sp, -16\n" /* the callee expects to save a0..a3 there = */ +#endif /* _ABIO32 */ "lui $t9, %hi(_start_c)\n" /* ABI requires current function address in $= t9 */ "ori $t9, %lo(_start_c)\n" +#if defined(_ABI64) + "lui $t0, %highest(_start_c)\n" + "ori $t0, %higher(_start_c)\n" + "dsll $t0, 0x20\n" + "or $t9, $t0\n" +#endif /* _ABI64 */ "jalr $t9\n" /* transfer to c runtime = */ ); __nolibc_entrypoint_epilogue(); diff --git a/tools/testing/selftests/nolibc/Makefile.nolibc b/tools/testing= /selftests/nolibc/Makefile.nolibc index 6d62f350d0c16405785a8aabc7f5741b82e55370..9b56191b10b3c2a12da8ae22a41= d57167b63707e 100644 --- a/tools/testing/selftests/nolibc/Makefile.nolibc +++ b/tools/testing/selftests/nolibc/Makefile.nolibc @@ -53,6 +53,10 @@ ARCH_ppc64 =3D powerpc ARCH_ppc64le =3D powerpc ARCH_mips32le =3D mips ARCH_mips32be =3D mips +ARCH_mipsn32le =3D mips +ARCH_mipsn32be =3D mips +ARCH_mips64le =3D mips +ARCH_mips64be =3D mips ARCH_riscv32 =3D riscv ARCH_riscv64 =3D riscv ARCH_s390x =3D s390 @@ -69,6 +73,10 @@ IMAGE_arm =3D arch/arm/boot/zImage IMAGE_armthumb =3D arch/arm/boot/zImage IMAGE_mips32le =3D vmlinuz IMAGE_mips32be =3D vmlinuz +IMAGE_mipsn32le =3D vmlinuz +IMAGE_mipsn32be =3D vmlinuz +IMAGE_mips64le =3D vmlinuz +IMAGE_mips64be =3D vmlinuz IMAGE_ppc =3D vmlinux IMAGE_ppc64 =3D vmlinux IMAGE_ppc64le =3D arch/powerpc/boot/zImage @@ -93,6 +101,10 @@ DEFCONFIG_arm =3D multi_v7_defconfig DEFCONFIG_armthumb =3D multi_v7_defconfig DEFCONFIG_mips32le =3D malta_defconfig DEFCONFIG_mips32be =3D malta_defconfig generic/eb.config +DEFCONFIG_mipsn32le =3D malta_defconfig generic/64r2.config +DEFCONFIG_mipsn32be =3D malta_defconfig generic/64r6.config generic/eb.co= nfig +DEFCONFIG_mips64le =3D malta_defconfig generic/64r6.config +DEFCONFIG_mips64be =3D malta_defconfig generic/64r2.config generic/eb.co= nfig DEFCONFIG_ppc =3D pmac32_defconfig DEFCONFIG_ppc64 =3D powernv_be_defconfig DEFCONFIG_ppc64le =3D powernv_defconfig @@ -124,6 +136,10 @@ QEMU_ARCH_arm =3D arm QEMU_ARCH_armthumb =3D arm QEMU_ARCH_mips32le =3D mipsel # works with malta_defconfig QEMU_ARCH_mips32be =3D mips +QEMU_ARCH_mipsn32le =3D mips64el +QEMU_ARCH_mipsn32be =3D mips64 +QEMU_ARCH_mips64le =3D mips64el +QEMU_ARCH_mips64be =3D mips64 QEMU_ARCH_ppc =3D ppc QEMU_ARCH_ppc64 =3D ppc64 QEMU_ARCH_ppc64le =3D ppc64 @@ -139,6 +155,8 @@ QEMU_ARCH_m68k =3D m68k QEMU_ARCH =3D $(QEMU_ARCH_$(XARCH)) =20 QEMU_ARCH_USER_ppc64le =3D ppc64le +QEMU_ARCH_USER_mipsn32le =3D mipsn32el +QEMU_ARCH_USER_mipsn32be =3D mipsn32 QEMU_ARCH_USER =3D $(or $(QEMU_ARCH_USER_$(XARCH)),$(QEMU_ARCH_$(X= ARCH))) =20 QEMU_BIOS_DIR =3D /usr/share/edk2/ @@ -157,6 +175,10 @@ QEMU_ARGS_arm =3D -M virt -append "panic=3D-1 $= (TEST:%=3DNOLIBC_TEST=3D%)" QEMU_ARGS_armthumb =3D -M virt -append "panic=3D-1 $(TEST:%=3DNOLIBC_TES= T=3D%)" QEMU_ARGS_mips32le =3D -M malta -append "panic=3D-1 $(TEST:%=3DNOLIBC_TE= ST=3D%)" QEMU_ARGS_mips32be =3D -M malta -append "panic=3D-1 $(TEST:%=3DNOLIBC_TE= ST=3D%)" +QEMU_ARGS_mipsn32le =3D -M malta -cpu 5KEc -append "panic=3D-1 $(TEST:%= =3DNOLIBC_TEST=3D%)" +QEMU_ARGS_mipsn32be =3D -M malta -cpu I6400 -append "panic=3D-1 $(TEST:%= =3DNOLIBC_TEST=3D%)" +QEMU_ARGS_mips64le =3D -M malta -cpu I6400 -append "panic=3D-1 $(TEST:%= =3DNOLIBC_TEST=3D%)" +QEMU_ARGS_mips64be =3D -M malta -cpu 5KEc -append "panic=3D-1 $(TEST:%= =3DNOLIBC_TEST=3D%)" QEMU_ARGS_ppc =3D -M g3beige -append "console=3DttyS0 panic=3D-1 $(= TEST:%=3DNOLIBC_TEST=3D%)" QEMU_ARGS_ppc64 =3D -M powernv -append "console=3Dhvc0 panic=3D-1 $(T= EST:%=3DNOLIBC_TEST=3D%)" QEMU_ARGS_ppc64le =3D -M powernv -append "console=3Dhvc0 panic=3D-1 $(T= EST:%=3DNOLIBC_TEST=3D%)" @@ -191,6 +213,10 @@ CFLAGS_s390x =3D -m64 CFLAGS_s390 =3D -m31 CFLAGS_mips32le =3D -EL -mabi=3D32 -fPIC CFLAGS_mips32be =3D -EB -mabi=3D32 +CFLAGS_mipsn32le =3D -EL -mabi=3Dn32 -fPIC -march=3Dmips64r2 +CFLAGS_mipsn32be =3D -EB -mabi=3Dn32 -march=3Dmips64r6 +CFLAGS_mips64le =3D -EL -mabi=3D64 -march=3Dmips64r6 +CFLAGS_mips64be =3D -EB -mabi=3D64 -march=3Dmips64r2 CFLAGS_sparc32 =3D $(call cc-option,-m32) ifeq ($(origin XARCH),command line) CFLAGS_XARCH =3D $(CFLAGS_$(XARCH)) diff --git a/tools/testing/selftests/nolibc/run-tests.sh b/tools/testing/se= lftests/nolibc/run-tests.sh index 53d843731c3e0d80dac0764d58b63c43a105021f..97fa9b7c7232dc1e3fb79a7cf8e= cdb0934cb38be 100755 --- a/tools/testing/selftests/nolibc/run-tests.sh +++ b/tools/testing/selftests/nolibc/run-tests.sh @@ -20,7 +20,7 @@ llvm=3D all_archs=3D( i386 x86_64 arm64 arm armthumb - mips32le mips32be + mips32le mips32be mipsn32le mipsn32be mips64le mips64be ppc ppc64 ppc64le riscv32 riscv64 s390x s390 --=20 2.50.0