From nobody Mon Dec 15 22:31:40 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91E63233701 for ; Mon, 23 Jun 2025 10:50:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750675842; cv=none; b=ICj8RWX9Byc9rDKtTN9TE3Gds7LCQ9id/qGW+Pwk29+lT3WeGJkyN+MVXlEfJquV/KQo0XXNRZaEUtW0/zIlpcVDWDHbddKlnqwjt/AYfw0Nr2gYxSi5fzEg927JViHKPEjTCUR8a5wGfbUYeb04x2De9jO/avSlaKW62nSsa64= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750675842; c=relaxed/simple; bh=rk3IUXQZtzpNgDHc4TWz8qsml0b4el8IWm2S5mzHUtg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:To:CC; b=MKgXd2ZHzecoACWGwzv7i2zDxa/o5iCmciwpNrp2upL7bOhMto4tZzfXx32sDRklN3lo8fwewToMDJ8jT4WTP2SvElq9gOxRZXH4EWqI811x3sricg2fFUDO1EtTg0oySdmDZseyoPIa19xemLYeZZ1OBBfHL8Hb3pCVSzZlo5Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=hTz1h2yI; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="hTz1h2yI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750675841; x=1782211841; h=from:date:subject:mime-version:content-transfer-encoding: message-id:to:cc; bh=rk3IUXQZtzpNgDHc4TWz8qsml0b4el8IWm2S5mzHUtg=; b=hTz1h2yIhN2SwkME+BwW05g2vGeZCX8/KqXMJkibFqTyyFsP+wEbzFpJ GwapiSJMpYyMG6dVON6PKH/3taXO4OtTr7I9TLdydckZkzI43qJiqlsEr Y7wU0UZbFYzyNbVONp43ylLpm+4W1bg2DfaRZlDFByfFGkhSCJR37qIak GVnFjFqNNfmivX4kbaWLhz5xHFXC5yOiWdX5gSj8ax9iXaZKB69DJz/XI Qwm4aljjmRa3crW47KopsbGOuspssrr55sQRRsuPqJOyZUZS+33qfwIwx ueTcu8UAU/XkfsHVWpI9RHfmzkHaW1k0djtZCoOjwQsvkDXFD/n2Zk+Zc A==; X-CSE-ConnectionGUID: 6bSZM/9OSRy4OCnNpkPakQ== X-CSE-MsgGUID: Tgjy0TvIRPGqMZ48FubJyg== X-IronPort-AV: E=Sophos;i="6.16,258,1744095600"; d="scan'208";a="43105617" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Jun 2025 03:50:34 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Mon, 23 Jun 2025 03:50:29 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Mon, 23 Jun 2025 03:50:23 -0700 From: Dharma Balasubiramani Date: Mon, 23 Jun 2025 16:20:20 +0530 Subject: [PATCH v2] drm/bridge: microchip-lvds: fix bus format mismatch with VESA displays Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250623-microchip-lvds-v2-1-8ecbabc6abc4@microchip.com> X-B4-Tracking: v=1; b=H4sIAGsxWWgC/3WMzQ7CIBCEX6XZsxiWSH889T1MDwirbGJLA4ZoG t5d7MGbmdM3mfk2SBSZEpybDSJlThyWCurQgPVmuZNgVxmUVFq22IuZbQzW8yoe2SVx7VCjG1o 5nAzU0xrpxq9deJkqe07PEN+7P+O3/avKKGrIkDbWdaZX429wtGGGqZTyARMRUnewAAAA To: Manikandan Muralidharan , Andrzej Hajda , Neil Armstrong , "Robert Foss" , Laurent Pinchart , Jonas Karlman , "Jernej Skrabec" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter CC: , , "Sandeep Sheriker M" , Dharma Balasubiramani X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1750675822; l=5514; i=dharma.b@microchip.com; s=20240209; h=from:subject:message-id; bh=ERy9vkRv7sHUQQmIkZ0cGBnXyaHHcDyCGdJs2X5F8fM=; b=4vUlMxxV3nHZ8s98H7ds6voTow3QFAke4gVDuv5SfegGyEHrzY6jfkPNKdnGAJHNEehNMSiPG NvBJA9kJLOVBiX2Yl0L1gto5vHX75OEYAEvDM5tqYg/u7fxCvy1AxK5 X-Developer-Key: i=dharma.b@microchip.com; a=ed25519; pk=kCq31LcpLAe9HDfIz9ZJ1U7T+osjOi7OZSbe0gqtyQ4= From: Sandeep Sheriker M The LVDS controller was hardcoded to JEIDA mapping, which leads to distorted output on panels expecting VESA mapping. Update the driver to dynamically select the appropriate mapping and pixel size based on the panel's advertised media bus format. This ensures compatibility with both JEIDA and VESA displays. Modernize the bridge ops to use atomic_enable/disable, and retrieve the bus format from the connector via the atomic bridge state. Signed-off-by: Sandeep Sheriker M Signed-off-by: Dharma Balasubiramani --- Note: Tested the changes on newvision 10.1 VESA display. Changes in v2: - Switch to atomic bridge functions - Drop custom connector creation - Use drm_atomic_get_new_connector_for_encoder() - Link to v1: https://lore.kernel.org/r/20250618-microchip-lvds-v1-1-1eae5a= cd7a82@microchip.com --- drivers/gpu/drm/bridge/microchip-lvds.c | 64 +++++++++++++++++++++++++++--= ---- 1 file changed, 54 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/bridge/microchip-lvds.c b/drivers/gpu/drm/brid= ge/microchip-lvds.c index 9f4ff82bc6b4..b71478aa36e9 100644 --- a/drivers/gpu/drm/bridge/microchip-lvds.c +++ b/drivers/gpu/drm/bridge/microchip-lvds.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -41,9 +42,11 @@ =20 /* Bitfields in LVDSC_CFGR (Configuration Register) */ #define LVDSC_CFGR_PIXSIZE_24BITS 0 +#define LVDSC_CFGR_PIXSIZE_18BITS 1 #define LVDSC_CFGR_DEN_POL_HIGH 0 #define LVDSC_CFGR_DC_UNBALANCED 0 #define LVDSC_CFGR_MAPPING_JEIDA BIT(6) +#define LVDSC_CFGR_MAPPING_VESA 0 =20 /*Bitfields in LVDSC_SR */ #define LVDSC_SR_CS BIT(0) @@ -76,9 +79,10 @@ static inline void lvds_writel(struct mchp_lvds *lvds, u= 32 offset, u32 val) writel_relaxed(val, lvds->regs + offset); } =20 -static void lvds_serialiser_on(struct mchp_lvds *lvds) +static void lvds_serialiser_on(struct mchp_lvds *lvds, u32 bus_format) { unsigned long timeout =3D jiffies + msecs_to_jiffies(LVDS_POLL_TIMEOUT_MS= ); + u8 map, pix_size; =20 /* The LVDSC registers can only be written if WPEN is cleared */ lvds_writel(lvds, LVDSC_WPMR, (LVDSC_WPMR_WPKEY_PSSWD & @@ -93,11 +97,24 @@ static void lvds_serialiser_on(struct mchp_lvds *lvds) usleep_range(1000, 2000); } =20 + switch (bus_format) { + case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: + map =3D LVDSC_CFGR_MAPPING_JEIDA; + pix_size =3D LVDSC_CFGR_PIXSIZE_18BITS; + break; + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: + map =3D LVDSC_CFGR_MAPPING_VESA; + pix_size =3D LVDSC_CFGR_PIXSIZE_24BITS; + break; + default: + map =3D LVDSC_CFGR_MAPPING_JEIDA; + pix_size =3D LVDSC_CFGR_PIXSIZE_24BITS; + break; + } + /* Configure the LVDSC */ - lvds_writel(lvds, LVDSC_CFGR, (LVDSC_CFGR_MAPPING_JEIDA | - LVDSC_CFGR_DC_UNBALANCED | - LVDSC_CFGR_DEN_POL_HIGH | - LVDSC_CFGR_PIXSIZE_24BITS)); + lvds_writel(lvds, LVDSC_CFGR, (map | LVDSC_CFGR_DC_UNBALANCED | + LVDSC_CFGR_DEN_POL_HIGH | pix_size)); =20 /* Enable the LVDS serializer */ lvds_writel(lvds, LVDSC_CR, LVDSC_CR_SER_EN); @@ -113,7 +130,8 @@ static int mchp_lvds_attach(struct drm_bridge *bridge, bridge, flags); } =20 -static void mchp_lvds_enable(struct drm_bridge *bridge) +static void mchp_lvds_atomic_pre_enable(struct drm_bridge *bridge, + struct drm_atomic_state *state) { struct mchp_lvds *lvds =3D bridge_to_lvds(bridge); int ret; @@ -129,11 +147,35 @@ static void mchp_lvds_enable(struct drm_bridge *bridg= e) dev_err(lvds->dev, "failed to get pm runtime: %d\n", ret); return; } +} + +static void mchp_lvds_atomic_enable(struct drm_bridge *bridge, + struct drm_atomic_state *state) +{ + struct mchp_lvds *lvds =3D bridge_to_lvds(bridge); + struct drm_connector *connector; + + /* default to jeida-24 */ + u32 bus_format =3D MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA; + + connector =3D drm_atomic_get_new_connector_for_encoder(state, bridge->enc= oder); + if (connector && connector->display_info.num_bus_formats) + bus_format =3D connector->display_info.bus_formats[0]; + + lvds_serialiser_on(lvds, bus_format); +} + +static void mchp_lvds_atomic_disable(struct drm_bridge *bridge, + struct drm_atomic_state *state) +{ + struct mchp_lvds *lvds =3D bridge_to_lvds(bridge); =20 - lvds_serialiser_on(lvds); + /* Turn off the serialiser */ + lvds_writel(lvds, LVDSC_CR, 0); } =20 -static void mchp_lvds_disable(struct drm_bridge *bridge) +static void mchp_lvds_atomic_post_disable(struct drm_bridge *bridge, + struct drm_atomic_state *state) { struct mchp_lvds *lvds =3D bridge_to_lvds(bridge); =20 @@ -143,8 +185,10 @@ static void mchp_lvds_disable(struct drm_bridge *bridg= e) =20 static const struct drm_bridge_funcs mchp_lvds_bridge_funcs =3D { .attach =3D mchp_lvds_attach, - .enable =3D mchp_lvds_enable, - .disable =3D mchp_lvds_disable, + .atomic_pre_enable =3D mchp_lvds_atomic_pre_enable, + .atomic_enable =3D mchp_lvds_atomic_enable, + .atomic_disable =3D mchp_lvds_atomic_disable, + .atomic_post_disable =3D mchp_lvds_atomic_post_disable, }; =20 static int mchp_lvds_probe(struct platform_device *pdev) --- base-commit: 4325743c7e209ae7845293679a4de94b969f2bef change-id: 20250618-microchip-lvds-b7151d96094a Best regards, --=20 Dharma Balasubiramani