From nobody Wed Oct 8 23:02:54 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9AC42253F35; Mon, 23 Jun 2025 12:56:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750683413; cv=none; b=qUFA0swV3e0Xay41fHHIrEpu0nBghqxj+FWy0b/Xh4zJ/ciR5q7bxhXgquLKzzz8ny6fEMkaZJa+GScOTY9TdJLIamBNXcS2SvgC4UeHE/i6eIhwofakY9++Jwc3hbSiww/VCxw0AzmLyQFdSvRZor3t+6bN6aKJzxkWYKrA/Cc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750683413; c=relaxed/simple; bh=GVjFe4ObRxWxhFMM0FviQ7S/XQ0xsxyQJkNxl0XAxIE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RC6wsb5+9JvufQ52TklSSZVjQlj1BWkPPi5ORjJUdJSkgFa9Qfk2EFWkT5QNCxsDOnS9UqNiaC6fLKigk1JXOQi0PsA996ODDWqnecWhFL+pKaYvyMoHov8Uj/SXI1b+krCKxxsSv6Kj4I0jdabx8/KnvXX569BfxDJ3U+WtVfo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Gs6OLwpU; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Gs6OLwpU" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 11B87C4CEF6; Mon, 23 Jun 2025 12:56:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750683413; bh=GVjFe4ObRxWxhFMM0FviQ7S/XQ0xsxyQJkNxl0XAxIE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Gs6OLwpUhQG/IueLFxoH/Cz8a3suIICLHaT/RJ6GVJZq48sZ0jI09lAxpuSC+O6xj YAkGIOgZAZixF2qp3qfNmgl2hKWBRCOYn3s+m5sAwjMnYKmQoiWQKSSN/TtlxiiSYM daSHXRloUA7mb36Au+C92Xp2zv6wMkBq5KwcY6tY/IQN28moru6oLC1KFnS3KxKmJG 5f6dSPCjBKOvhNfgRFLNQ43Pc9/BXHp3Yy2MoH80SePWBg1hl0NJGSxO8CVPDNLDi9 Q48qACq9obNQdIZqY96CC38N5BKp46hEJn7Wo6gaN1rnLAO6hHjwAwIhidZcvFJBA4 tgJJzWdbR2vpA== From: Conor Dooley To: sboyd@kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v3 1/9] dt-bindings: mfd: syscon document the control-scb syscon on PolarFire SoC Date: Mon, 23 Jun 2025 13:56:15 +0100 Message-ID: <20250623-playoff-napkin-5426a5e304cd@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250623-levitate-nugget-08c9a01f401d@spud> References: <20250623-levitate-nugget-08c9a01f401d@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1505; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=hxOaJHTVRbH1YgnYGVBXvMwqTyw6bMbbuBO5TUxUKWE=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDBmRfu+FmR1j5lrcd7wdr3zopH7R7EiV+tknnZ6x25w2D K2xuNTXUcrCIMbBICumyJJ4u69Fav0flx3OPW9h5rAygQxh4OIUgIlIVjD8lf/+6PrEmg1pTf+W MYRqS60ocdCKPtCr9K7p0PejKbo+NxkZXpermORO5/fwqA8+Ely26M4hx10BP7kahSd3pMcFRFo zAwA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The "control-scb" region, contains the "tvs" temperature and voltage sensors and the control/status registers for the system controller's mailbox. The mailbox has a dedicated node, so there's no need for a child node describing it, looking the syscon up by compatible is sufficient. Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- v2: add the control-scb syscon here too, since it doesn't have any children. --- Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentat= ion/devicetree/bindings/mfd/syscon.yaml index 27672adeb1fed..d18be50dd7127 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -90,6 +90,7 @@ select: - mediatek,mt8173-pctl-a-syscfg - mediatek,mt8365-syscfg - microchip,lan966x-cpu-syscon + - microchip,mpfs-control-scb - microchip,mpfs-sysreg-scb - microchip,sam9x60-sfr - microchip,sama7d65-ddr3phy @@ -197,6 +198,7 @@ properties: - mediatek,mt8365-infracfg-nao - mediatek,mt8365-syscfg - microchip,lan966x-cpu-syscon + - microchip,mpfs-control-scb - microchip,mpfs-sysreg-scb - microchip,sam9x60-sfr - microchip,sama7d65-ddr3phy --=20 2.45.2 From nobody Wed Oct 8 23:02:54 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB317253F35; Mon, 23 Jun 2025 12:56:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750683417; cv=none; b=rPekfi464hdukI1mPN1emIywaVKvlvd1Cso0Peirqd60W5IWyZXcKmfYcHdphFcIU36t33ciR8JD3fX6u5zdUN9qbK0vveG+WCF1krMrRn0RLt2r5vKTmmkWuCnZXoX0dYNa+gEHq60lgoa9+UOz3QW8tHXfRqs3nfZcNAhydrk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750683417; c=relaxed/simple; bh=PIHOS5LM4Q5ULhIpiS+e6H3YXH5KbzpMBhW+qqqEPHU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=obGQgiT9RwToGmhGRJnXd6F+SFuEo70nEtCiFCzL0T6pBJFQxV9CIweHtFhs/VjxA0BRc//pxBqv8xK8ubzHsOQSAjZbNiu3i/3EMCbRmW2V5++AJo2iqW0+2WVK4/4yBkM0zLiUL9MemB+TiXLpv6TqF7Q+pyNms6fIvszD6BE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gNXbW/13; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gNXbW/13" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E4504C4CEF2; Mon, 23 Jun 2025 12:56:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750683417; bh=PIHOS5LM4Q5ULhIpiS+e6H3YXH5KbzpMBhW+qqqEPHU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gNXbW/135BTxQgteCZ6aZnwg0bZcP2fpcaoQBVoKkCrUsItwnPWJ4j7XkiCovARAv Iw/MoVJ2oXMf1JmTBnWkO9bQadh4pTU/m7zg3hhRppXu9gPl+kiTcJFesQljIkj2ci 1+xWant1y5AL+FeiyxrYm3jLBzrvLrRocqBvYbynLQOETtgFJTiDzXqrMD8CDL3Wgx VP7ojKyRLBlwX2ax0qBdxGBcTerD28xPgsoOZU4/BiBESumF9MnP64f5Zppl2OZkYv 99Ay0ROvx2Ik/Mt5mJwcCpEqffvcLMgV2ScTWVgVEnAGugwRBYIG1VCNBPBHr5SaGM nPcdPjDn1dTxA== From: Conor Dooley To: sboyd@kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/9] dt-bindings: soc: microchip: document the simple-mfd syscon on PolarFire SoC Date: Mon, 23 Jun 2025 13:56:16 +0100 Message-ID: <20250623-underwear-refinery-9203f771bc39@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250623-levitate-nugget-08c9a01f401d@spud> References: <20250623-levitate-nugget-08c9a01f401d@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2876; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=VHCdWiaaucWgmq2/9huhuDTRmVGS9+Jq0xOGf5lOCpE=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDBmRfu+XC5877sWkIJNSLM2868HGEgW9+sqV0zrmb2xzS 0uSWCnVUcrCIMbBICumyJJ4u69Fav0flx3OPW9h5rAygQxh4OIUgIksUGP4Z7I9XIihYDJ3lkqs /9f7ob8660Q1dN+qHRP1e/+qPu/tTUaGx1bnKu7N3XPU9vGxYJZXsk9+CvdL9P+btKr/v6fLiqP GjAA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley "mss-top-sysreg" contains clocks, pinctrl, resets, an interrupt controller and more. At this point, only the reset controller child is described as that's all that is described by the existing bindings. The clock controller already has a dedicated node, and will retain it as there are other clock regions, so like the mailbox, a compatible-based lookup of the syscon is sufficient to keep the clock driver working as before, so no child is needed. There's also an interrupt multiplexing service provided by this syscon, for which there is work in progress at [1]. Link: https://lore.kernel.org/linux-gpio/20240723-uncouple-enforcer-7c48e4a= 4fefe@wendy/ [1] Signed-off-by: Conor Dooley Reviewed-by: Krzysztof Kozlowski --- v3: - drop simple-mfd at Krzysztof's request since the child nodes do not yet exist. v2: - clean up various minor comments from Rob on mpfs-mss-top-sysreg - remove mpfs-control-scb from this patch --- .../microchip,mpfs-mss-top-sysreg.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/microchip/microch= ip,mpfs-mss-top-sysreg.yaml diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs= -mss-top-sysreg.yaml b/Documentation/devicetree/bindings/soc/microchip/micr= ochip,mpfs-mss-top-sysreg.yaml new file mode 100644 index 0000000000000..1ab691db87950 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-to= p-sysreg.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-mss-top-sy= sreg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire SoC Microprocessor Subsystem (MSS) sysreg regis= ter region + +maintainers: + - Conor Dooley + +description: + An wide assortment of registers that control elements of the MSS on Pola= rFire + SoC, including pinmuxing, resets and clocks among others. + +properties: + compatible: + items: + - const: microchip,mpfs-mss-top-sysreg + - const: syscon + + reg: + maxItems: 1 + + '#reset-cells': + description: + The AHB/AXI peripherals on the PolarFire SoC have reset support, so + from CLK_ENVM to CLK_CFM. The reset consumer should specify the + desired peripheral via the clock ID in its "resets" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full li= st + of PolarFire clock/reset IDs. + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + syscon@20002000 { + compatible =3D "microchip,mpfs-mss-top-sysreg", "syscon"; + reg =3D <0x20002000 0x1000>; + #reset-cells =3D <1>; + }; + --=20 2.45.2 From nobody Wed Oct 8 23:02:54 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5698325522D; Mon, 23 Jun 2025 12:57:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750683421; cv=none; b=oI2/paM1eKx5sM7oEFx51nUU127B1PJXlhRqI9nOs7kEbqELI91xknTgXHqvRLP6MIPPPorO8WAInuB4EEZJc/8dtrnYnJgeW3WOCyd5/hzMsViooljpc7g64qMPHPCLqSVR/PvHcu+DzKRkh+2puT8ppiJkhE82Nsk1tAai16c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750683421; c=relaxed/simple; bh=7jVhqVGAjc9ZFGXbZZzkY3dEWfHE6F5nEf5rIqPjM64=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Q7rC6i6hZjAn2vUhtsK/90kbJTbxVJTE5c9D/XzvPQ/mn8+hRYBFlBxSXGQVHR/CVahodOHhql3ak3ZQH6gfiP+5yH299KoC4MwaFb0ItC5JrzjEdIiKRxbPCske14jfshuVBjJWu8NtjCxhi9Ve3dg5/rwmChNReEGIC2hsGp0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XdNV0jr/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XdNV0jr/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9A48BC4CEF0; Mon, 23 Jun 2025 12:56:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750683420; bh=7jVhqVGAjc9ZFGXbZZzkY3dEWfHE6F5nEf5rIqPjM64=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XdNV0jr/9S94RUaodZnYgQMI4wpfwTL2EOTMWES4QoCs27GyTgxxqfG9djDCNUoR+ Mt3EN1dIrRKOWFu/Gf6ifwrlFwQbg1vR+XS3yT/efYpd+KqSD2uetWXoreQzvTpIJ4 wpj6AK+mohhAT7xSmEVJ5KTHKyYSnDtSoXWCJ72egGkqCqfD79+ETmCbLPl+PiPCjP piYmZH7BUHBrh5dVz2XwAz8Gmyzb5QkUurTkR54wgd/iUhkEQi++4MB75eLScyaTW/ iS+BC8JmlCqI574jnv3RCc5yU/Y7vaW6OHdn2o3Bu1KayICxBddyOk9XH3LnyGeBuB kGiST5CXUqPVw== From: Conor Dooley To: sboyd@kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/9] soc: microchip: add mfd drivers for two syscon regions on PolarFire SoC Date: Mon, 23 Jun 2025 13:56:17 +0100 Message-ID: <20250623-rentable-eggbeater-98e9b7b64633@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250623-levitate-nugget-08c9a01f401d@spud> References: <20250623-levitate-nugget-08c9a01f401d@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4881; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=P0KwHlFPlXIpFEUesBiUq9EexeIVzEEKS9WSONg93nU=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDBmRfu9XffVtbpaP+tmulhcg8iVO3bdyucf08CTxE7K3C 63av93uKGVhEONgkBVTZEm83dcitf6Pyw7nnrcwc1iZQIYwcHEKwER+bWT4xcRqeuXNM73lk/rb WBZrlCbYScZlcMyx59RYz7ss72ccE8P/uL4j5SyS+XEb+U+lxz5fdnyqw/qu88Z/Z0ovfXnkOj8 nHwA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The control-scb and mss-top-sysreg regions on PolarFire SoC both fulfill multiple purposes. The former is used for mailbox functions in addition to the temperature & voltage sensor while the latter is used for clocks, resets, interrupt muxing and pinctrl. Signed-off-by: Conor Dooley --- drivers/soc/microchip/Kconfig | 13 ++++++ drivers/soc/microchip/Makefile | 1 + drivers/soc/microchip/mpfs-control-scb.c | 45 +++++++++++++++++++ drivers/soc/microchip/mpfs-mss-top-sysreg.c | 48 +++++++++++++++++++++ 4 files changed, 107 insertions(+) create mode 100644 drivers/soc/microchip/mpfs-control-scb.c create mode 100644 drivers/soc/microchip/mpfs-mss-top-sysreg.c diff --git a/drivers/soc/microchip/Kconfig b/drivers/soc/microchip/Kconfig index 19f4b576f822b..31d188311e05f 100644 --- a/drivers/soc/microchip/Kconfig +++ b/drivers/soc/microchip/Kconfig @@ -9,3 +9,16 @@ config POLARFIRE_SOC_SYS_CTRL module will be called mpfs_system_controller. =20 If unsure, say N. + +config POLARFIRE_SOC_SYSCONS + bool "PolarFire SoC (MPFS) syscon drivers" + default y + depends on ARCH_MICROCHIP + select MFD_CORE + help + These drivers add support for the syscons on PolarFire SoC (MPFS). + Without these drivers core parts of the kernel such as clocks + and resets will not function correctly. + + If unsure, and on a PolarFire SoC, say y. + diff --git a/drivers/soc/microchip/Makefile b/drivers/soc/microchip/Makefile index 14489919fe4b3..1a3a1594b089b 100644 --- a/drivers/soc/microchip/Makefile +++ b/drivers/soc/microchip/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_POLARFIRE_SOC_SYS_CTRL) +=3D mpfs-sys-controller.o +obj-$(CONFIG_POLARFIRE_SOC_SYSCONS) +=3D mpfs-control-scb.o mpfs-mss-top-s= ysreg.o diff --git a/drivers/soc/microchip/mpfs-control-scb.c b/drivers/soc/microch= ip/mpfs-control-scb.c new file mode 100644 index 0000000000000..d1a8e79c232e3 --- /dev/null +++ b/drivers/soc/microchip/mpfs-control-scb.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include + +static const struct mfd_cell mpfs_control_scb_devs[] =3D { + { .name =3D "mpfs-tvs", }, +}; + +static int mpfs_control_scb_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + int ret; + + ret =3D mfd_add_devices(dev, PLATFORM_DEVID_NONE, mpfs_control_scb_devs, + 1, NULL, 0, NULL); + if (ret) + return ret; + + return 0; +} + +static const struct of_device_id mpfs_control_scb_of_match[] =3D { + {.compatible =3D "microchip,mpfs-control-scb", }, + {}, +}; +MODULE_DEVICE_TABLE(of, mpfs_control_scb_of_match); + +static struct platform_driver mpfs_control_scb_driver =3D { + .driver =3D { + .name =3D "mpfs-control-scb", + .of_match_table =3D mpfs_control_scb_of_match, + }, + .probe =3D mpfs_control_scb_probe, +}; +module_platform_driver(mpfs_control_scb_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("PolarFire SoC control scb driver"); diff --git a/drivers/soc/microchip/mpfs-mss-top-sysreg.c b/drivers/soc/micr= ochip/mpfs-mss-top-sysreg.c new file mode 100644 index 0000000000000..9b2e7b84cdba2 --- /dev/null +++ b/drivers/soc/microchip/mpfs-mss-top-sysreg.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include + +static const struct mfd_cell mpfs_mss_top_sysreg_devs[] =3D { + { .name =3D "mpfs-reset", }, +}; + +static int mpfs_mss_top_sysreg_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + int ret; + + ret =3D mfd_add_devices(dev, PLATFORM_DEVID_NONE, mpfs_mss_top_sysreg_dev= s, + 1, NULL, 0, NULL); + if (ret) + return ret; + + if (devm_of_platform_populate(dev)) + dev_err(dev, "Error populating children\n"); + + return 0; +} + +static const struct of_device_id mpfs_mss_top_sysreg_of_match[] =3D { + {.compatible =3D "microchip,mpfs-mss-top-sysreg", }, + {}, +}; +MODULE_DEVICE_TABLE(of, mpfs_mss_top_sysreg_of_match); + +static struct platform_driver mpfs_mss_top_sysreg_driver =3D { + .driver =3D { + .name =3D "mpfs-mss-top-sysreg", + .of_match_table =3D mpfs_mss_top_sysreg_of_match, + }, + .probe =3D mpfs_mss_top_sysreg_probe, +}; +module_platform_driver(mpfs_mss_top_sysreg_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("PolarFire SoC mss top sysreg driver"); --=20 2.45.2 From nobody Wed Oct 8 23:02:54 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03AF125522B; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UPgE1kp6" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5008DC4CEF3; Mon, 23 Jun 2025 12:57:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750683424; bh=OBN546Xw/XSBw1gh+gDHqku7W/MmXiHf4o1JKHEMJYY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UPgE1kp6j+P7lyqJv8VobwOmGm7NFUPUKXeUTYG/cgSM4b24dUpuw8GZUG0gppLKK yM1QqMa7jMGLXOvHe/qqCWqbpPmI5t2FMBY0H9Fy2IKsu/yo47eDHkD0VTd0fgAdBn TPLk2UojF0mrQPcQM/TJjC89qnw/nNTmE1qp9Cgc7OQAXfJOzItHgpEOh3PwZAITX8 BZskbY0gKuOEa7k8pEwSiWQX5klQUcyBBDiMUd/9mNRxlW+W38St9h+wQneh9VyYPu /sWHPSIgHk0etVYLiu+XwQ8VBUQfKCnHEqQYVtESe34wD23DdpwOgkqEYS1vYh4kli d6rgmfW0nQGag== From: Conor Dooley To: sboyd@kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 4/9] reset: mpfs: add non-auxiliary bus probing Date: Mon, 23 Jun 2025 13:56:18 +0100 Message-ID: <20250623-equate-ogle-0ce3293567e2@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250623-levitate-nugget-08c9a01f401d@spud> References: <20250623-levitate-nugget-08c9a01f401d@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6071; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=LdtKOZ18m1Z5XTBQK39rScuREwN0yhaKcaTMme0dp2Y=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDBmRfu8LLcs+9eZxOEiFV3+3ft+iwtWUJc4z7Uf/k9PR9 qvWH9jZUcLCIMbBICumyJJ4u69Fav0flx3OPW9h5rAygQxh4OIUgIloP2Bk2KmQKN0WK32vbGrb /GtsHQuONq7vvz+BZ8edeRLzf3Lb72b4pmvI8eXlbpvm/OwsoTmeCyeYnhJYcdqa41jT+YIwpe+ MAA== X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley While the auxiliary bus was a nice bandaid, and meant that re-writing the representation of the clock regions in devicetree was not required, it has run its course. The "mss_top_sysreg" region that contains the clock and reset regions, also contains pinctrl and an interrupt controller, so the time has come rewrite the devicetree and probe the reset controller from an mfd devicetree node, rather than implement those drivers using the auxiliary bus. Wanting to avoid propagating this naive/incorrect description of the hardware to the new pic64gx SoC is a major motivating factor here. Signed-off-by: Conor Dooley --- v2: Implement the request to use regmap_update_bits(). I found that I then hated the read/write helpers since they were just bloat, so I ripped them out. I replaced the regular spin_lock_irqsave() stuff with a guard(spinlock_irqsave), since that's a simpler way of handling the two different paths through such a trivial pair of functions. --- drivers/reset/reset-mpfs.c | 81 ++++++++++++++++++++++++++++++-------- 1 file changed, 65 insertions(+), 16 deletions(-) diff --git a/drivers/reset/reset-mpfs.c b/drivers/reset/reset-mpfs.c index 574e59db83a4f..9c3e996f3a099 100644 --- a/drivers/reset/reset-mpfs.c +++ b/drivers/reset/reset-mpfs.c @@ -7,12 +7,15 @@ * */ #include +#include #include #include +#include #include #include #include #include +#include #include #include #include @@ -27,11 +30,14 @@ #define MPFS_SLEEP_MIN_US 100 #define MPFS_SLEEP_MAX_US 200 =20 +#define REG_SUBBLK_RESET_CR 0x88u + /* block concurrent access to the soft reset register */ static DEFINE_SPINLOCK(mpfs_reset_lock); =20 struct mpfs_reset { void __iomem *base; + struct regmap *regmap; struct reset_controller_dev rcdev; }; =20 @@ -46,41 +52,50 @@ static inline struct mpfs_reset *to_mpfs_reset(struct r= eset_controller_dev *rcde static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long i= d) { struct mpfs_reset *rst =3D to_mpfs_reset(rcdev); - unsigned long flags; u32 reg; =20 - spin_lock_irqsave(&mpfs_reset_lock, flags); + guard(spinlock_irqsave)(&mpfs_reset_lock); + + if (rst->regmap) { + regmap_update_bits(rst->regmap, REG_SUBBLK_RESET_CR, BIT(id), BIT(id)); + return 0; + } =20 reg =3D readl(rst->base); reg |=3D BIT(id); writel(reg, rst->base); =20 - spin_unlock_irqrestore(&mpfs_reset_lock, flags); - return 0; } =20 static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long= id) { struct mpfs_reset *rst =3D to_mpfs_reset(rcdev); - unsigned long flags; u32 reg; =20 - spin_lock_irqsave(&mpfs_reset_lock, flags); + guard(spinlock_irqsave)(&mpfs_reset_lock); + + if (rst->regmap) { + regmap_update_bits(rst->regmap, REG_SUBBLK_RESET_CR, BIT(id), 0); + return 0; + } =20 reg =3D readl(rst->base); reg &=3D ~BIT(id); writel(reg, rst->base); =20 - spin_unlock_irqrestore(&mpfs_reset_lock, flags); - return 0; } =20 static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long i= d) { struct mpfs_reset *rst =3D to_mpfs_reset(rcdev); - u32 reg =3D readl(rst->base); + u32 reg; + + if (rst->regmap) + regmap_read(rst->regmap, REG_SUBBLK_RESET_CR, ®); + else + reg =3D readl(rst->base); =20 /* * It is safe to return here as MPFS_NUM_RESETS makes sure the sign bit @@ -130,11 +145,45 @@ static int mpfs_reset_xlate(struct reset_controller_d= ev *rcdev, return index - MPFS_PERIPH_OFFSET; } =20 -static int mpfs_reset_probe(struct auxiliary_device *adev, - const struct auxiliary_device_id *id) +static int mpfs_reset_mfd_probe(struct platform_device *pdev) { - struct device *dev =3D &adev->dev; struct reset_controller_dev *rcdev; + struct device *dev =3D &pdev->dev; + struct mpfs_reset *rst; + + rst =3D devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL); + if (!rst) + return -ENOMEM; + + rcdev =3D &rst->rcdev; + rcdev->dev =3D dev; + rcdev->ops =3D &mpfs_reset_ops; + + rcdev->of_node =3D pdev->dev.parent->of_node; + rcdev->of_reset_n_cells =3D 1; + rcdev->of_xlate =3D mpfs_reset_xlate; + rcdev->nr_resets =3D MPFS_NUM_RESETS; + + rst->regmap =3D device_node_to_regmap(pdev->dev.parent->of_node); + if (IS_ERR(rst->regmap)) + dev_err_probe(dev, PTR_ERR(rst->regmap), "Failed to find syscon regmap\n= "); + + return devm_reset_controller_register(dev, rcdev); +} + +static struct platform_driver mpfs_reset_mfd_driver =3D { + .probe =3D mpfs_reset_mfd_probe, + .driver =3D { + .name =3D "mpfs-reset", + }, +}; +module_platform_driver(mpfs_reset_mfd_driver); + +static int mpfs_reset_adev_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct reset_controller_dev *rcdev; + struct device *dev =3D &adev->dev; struct mpfs_reset *rst; =20 rst =3D devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL); @@ -145,8 +194,8 @@ static int mpfs_reset_probe(struct auxiliary_device *ad= ev, =20 rcdev =3D &rst->rcdev; rcdev->dev =3D dev; - rcdev->dev->parent =3D dev->parent; rcdev->ops =3D &mpfs_reset_ops; + rcdev->of_node =3D dev->parent->of_node; rcdev->of_reset_n_cells =3D 1; rcdev->of_xlate =3D mpfs_reset_xlate; @@ -222,12 +271,12 @@ static const struct auxiliary_device_id mpfs_reset_id= s[] =3D { }; MODULE_DEVICE_TABLE(auxiliary, mpfs_reset_ids); =20 -static struct auxiliary_driver mpfs_reset_driver =3D { - .probe =3D mpfs_reset_probe, +static struct auxiliary_driver mpfs_reset_aux_driver =3D { + .probe =3D mpfs_reset_adev_probe, .id_table =3D mpfs_reset_ids, }; =20 -module_auxiliary_driver(mpfs_reset_driver); +module_auxiliary_driver(mpfs_reset_aux_driver); =20 MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver"); MODULE_AUTHOR("Conor Dooley "); --=20 2.45.2 From nobody Wed Oct 8 23:02:54 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A96C255F5F; Mon, 23 Jun 2025 12:57:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750683428; cv=none; b=reDRa6e6vWjfHZJ3PGNB+SrZ1m9uuD0F7l2RaLQY2YB5l2eiqmLG3zqL0u+mfLRt4IidbLU4rGrNxtfzV3mQ9i/OUDOsDwbqNKGJAYIReLhzbwXgI4kDwfUmD74jZaCyQczJ9V1wi0AeaINI6yOP1RtFbQT8jJC2S8VIau3KgAY= ARC-Message-Signature: i=1; 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b=LrmrexSb7s2B0rwEd3k6FjaQH9FDthqJ78OwE105n2ChC8RJ+fOH+6Fy1mDMBQmKX TVbUWV2HEuzd1h4frHvAtTePvUUX+/qMRGNwG/v82+MzHlPRg7ZhfkE16EiFcqw046 0ogEwBwvtxJsBYJlwygufv6S2OY5kopxjCGxY6xKLV+HvZ2EJxVcxPkRAoRK0sFbqx QDlRcESNbq4rrvaEbEn/HCET+1MWbgA07yS0VvL16THp7xZ5V89BxMHSremTIWQe+D FjthczL/uZsLG9fAgCZavnwvxfb1cYGW1FxXuUrpKM3GRoIH7FTAIogtJthNa+DTAA 9QM4VUxJ2wQfg== From: Conor Dooley To: sboyd@kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 5/9] dt-bindings: clk: microchip: mpfs: remove first reg region Date: Mon, 23 Jun 2025 13:56:19 +0100 Message-ID: <20250623-hypnotist-research-c6e8af149d02@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250623-levitate-nugget-08c9a01f401d@spud> References: <20250623-levitate-nugget-08c9a01f401d@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3161; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=UdUqQObnXpHYaHDeBwfkNqw526ibviGaaI8ii4cMcNg=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDBmRfh/eO/tU9G0JrHy57NtajeBnCyofGSw9tfmIqNlup lffWI986yhlYRDjYJAVU2RJvN3XIrX+j8sO5563MHNYmUCGMHBxCsBE6t4zMuxq3H2r44Vbvb3A qvtThDtevXt52n8Rjxbfmjm2u8RruL8wMky7Llr1KGnV7Zc5mXdWbfHI6FQvq77xSmm/yAqORWz zTzICAA== X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The first reg region in this binding is not exclusively for clocks, as evidenced by the dual role of this device as a reset controller at present. The first region is however better described by a simple-mfd syscon, but this would have require a significant re-write of the devicetree for the platform, so the easy way out was chosen when reset support was first introduced. The region doesn't just contain clock and reset registers, it also contains pinctrl and interrupt controller functionality, so drop the region from the clock binding so that it can be described instead by a simple-mfd syscon rather than propagate this incorrect description of the hardware to the new pic64gx SoC. Acked-by: Rob Herring (Arm) Signed-off-by: Conor Dooley --- .../bindings/clock/microchip,mpfs-clkcfg.yaml | 36 +++++++++++-------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.= yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml index e4e1c31267d2a..ee4f31596d978 100644 --- a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml @@ -22,16 +22,23 @@ properties: const: microchip,mpfs-clkcfg =20 reg: - items: - - description: | - clock config registers: - These registers contain enable, reset & divider tables for the, = cpu, - axi, ahb and rtc/mtimer reference clocks as well as enable and r= eset - for the peripheral clocks. - - description: | - mss pll dri registers: - Block of registers responsible for dynamic reconfiguration of th= e mss - pll + oneOf: + - items: + - description: | + clock config registers: + These registers contain enable, reset & divider tables for t= he, cpu, + axi, ahb and rtc/mtimer reference clocks as well as enable a= nd reset + for the peripheral clocks. + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration o= f the mss + pll + deprecated: true + - items: + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration o= f the mss + pll =20 clocks: maxItems: 1 @@ -69,11 +76,12 @@ examples: - | #include soc { - #address-cells =3D <2>; - #size-cells =3D <2>; - clkcfg: clock-controller@20002000 { + #address-cells =3D <1>; + #size-cells =3D <1>; + + clkcfg: clock-controller@3E001000 { compatible =3D "microchip,mpfs-clkcfg"; - reg =3D <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0= x1000>; + reg =3D <0x3E001000 0x1000>; clocks =3D <&ref>; #clock-cells =3D <1>; }; --=20 2.45.2 From nobody Wed Oct 8 23:02:54 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1FA2525394C; Mon, 23 Jun 2025 12:57:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750683432; cv=none; b=tCs7rqf1mg7+b1Dm039bmXMFBs2fGaR5eSRKbsAF5MLjcQC9ECd6dqDtEYB3X5dgM8qlEflveKjV1jwnsYFVsvdQQLlphfZf+Jeh6GTOofoVGQVtSVan9iM9reHbCJ8i4+LGnoK+U54UIz6MgBmziS7pyHTxYkpVK760jFduXbQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750683432; c=relaxed/simple; bh=ix4sQ34JPxCSiUUiRsS0uHeEHS+bhk2iYFRRYP8FzOs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=J/epvLKiTRQegiQEmxa8dF+DWPaByCKv3arXDCS86jEA/pzmK6kZF4aCrzUfQ7RPOLiHZkswV7WXMzp50zcddS/7iAmBLimBRKFT/4SQ0CIOzbR8tOgdLxTB9Yn0x8Shan703FWhuGjLn6SU+clrfL8VTwIPkT3swDWghbejJkA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=U80bDazB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="U80bDazB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B0426C4CEF2; Mon, 23 Jun 2025 12:57:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750683432; bh=ix4sQ34JPxCSiUUiRsS0uHeEHS+bhk2iYFRRYP8FzOs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=U80bDazBAxV3LbQXojEjjkURit4HqA1wBXOVefF4khXubI9+sNChj3EiY+7bV+4SL dKxmdwFwjeq5A8AaNNAsNVDkPbAvxlcbVUL5GlgfLwopG4pOjOflc6VKOpeK4QBga7 KSd7w17wciCYll7+b/DBgyJ6/30pt26HghuVZ6Q2xm829fwj3MN3ThHefK+Sgiqtx9 FRt5wS1iLHjFATZM0EfgKcE8gqUK1XhEL/tTel6+8Yx8/lLkc1sP7RLQn4uC7035aA lM7oCCTiLvTtgLkIYthoIjJxwDosFBuBKHmZHYnEzH9+xZmVkvKUKTygXPdphJEayT nvYweseGyl4xg== From: Conor Dooley To: sboyd@kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 6/9] riscv: dts: microchip: fix mailbox description Date: Mon, 23 Jun 2025 13:56:20 +0100 Message-ID: <20250623-crazily-boogieman-08d72613ebac@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250623-levitate-nugget-08c9a01f401d@spud> References: <20250623-levitate-nugget-08c9a01f401d@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2050; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=UOaeuCyA0NwooEKtPScWmm72FpyZFfETubTA7thTmBE=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDBmRfh8uz/vidvtnKfe2og9S+fVvOUTCFMI8TTkj+U0N5 CbvzCjrKGVhEONgkBVTZEm83dcitf6Pyw7nnrcwc1iZQIYwcHEKwER+r2P4pyBasvZWwsv6rsrJ e5ujD82/KJnknJ6zeNubO3oPJNezmDH8d3hQZtpil/rtqoyApVqIvdhkCWPZDJao4uk5+t/fz+r lAAA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley When the binding for the mailbox on PolarFire SoC was originally written, and later modified, mistakes were made - and the precise nature of the later modification should have been a giveaway, but alas I was naive at the time. A more correct modelling of the hardware is to use two syscons and have a single reg entry for the mailbox, containing the mailbox region. The two syscons contain the general control/status registers for the mailbox and the interrupt related registers respectively. The reason for two syscons is that the same mailbox is present on the non-SoC version of the FPGA, which has no interrupt controller, and the shared part of the rtl was unchanged between devices. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/= microchip/mpfs.dtsi index 9883ca3554c50..f9d6bf08e7170 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -259,6 +259,11 @@ clkcfg: clkcfg@20002000 { #reset-cells =3D <1>; }; =20 + sysreg_scb: syscon@20003000 { + compatible =3D "microchip,mpfs-sysreg-scb", "syscon"; + reg =3D <0x0 0x20003000 0x0 0x1000>; + }; + ccc_se: clock-controller@38010000 { compatible =3D "microchip,mpfs-ccc"; reg =3D <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>, @@ -521,10 +526,14 @@ usb: usb@20201000 { status =3D "disabled"; }; =20 - mbox: mailbox@37020000 { + control_scb: syscon@37020000 { + compatible =3D "microchip,mpfs-control-scb", "syscon"; + reg =3D <0x0 0x37020000 0x0 0x100>; + }; + + mbox: mailbox@37020800 { compatible =3D "microchip,mpfs-mailbox"; - reg =3D <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>, - <0x0 0x37020800 0x0 0x100>; + reg =3D <0x0 0x37020800 0x0 0x1000>; interrupt-parent =3D <&plic>; interrupts =3D <96>; #mbox-cells =3D <1>; --=20 2.45.2 From nobody Wed Oct 8 23:02:54 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D097125394C; Mon, 23 Jun 2025 12:57:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750683435; cv=none; b=FqDwIvJ3uoKb+vP7aU5QtvI43NcF9N4/r3gPc6Mf1U2Mj8vWYvrdXXHkVxGdpK+0V3eGgWdZHn5E29h+ifwwfNdcMqZmlFRq4CAi8LYZrM7agDtzaljDPnYOZCo+3ZnBi3kjtVuBVLApMZUeFbgeEv6R5uCttrsT64NVKHgpb8o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750683435; c=relaxed/simple; bh=DJSrVH7GlOfN6cb35orDOkMbtdc3M+/Haiv087kcVL8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DVxhpaiINbyUoMLI6TSFghq1Zd3M5eJbfXRN4BgW5SWhWKATmlAjMAgoxAr1HiSdS5idG+Bf8TQNVl8wrVIxiv+kzd5cecLIeHDdd0uL7roKKYO0M3SL8QMaVD0md6WMd3vzrR9aBbiV1GRWDIU+naCeg87UTWOq8fyXTh5NqwY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nwk0lrZo; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nwk0lrZo" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 66D50C4CEF1; Mon, 23 Jun 2025 12:57:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750683435; bh=DJSrVH7GlOfN6cb35orDOkMbtdc3M+/Haiv087kcVL8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nwk0lrZoQ8QRJxM8yO+5HvwUYw5maLMsKdJH7qfImv4ivCVFRbevnbIGIjyAeQWbI txTlVb6SH/C97X4uHb7kWgjgCejXe+58nfgkHfi3Hc+KnqfSX+M+kYcqrkYIUxwoms 1zj+Aeg9LVPNZEwfvWK31I/t2WZ7zGCzoeKVGS6BmS6pne6FwPmMvcP4lIEsNxZFWK 0NjXeQTt69EaSiPuxE1hS/c0bfg6CRcAs+PxecqSNGmVZm8USpn8i4KMtS5Wi0NTTW yIZEtN5HJ5SuLMsxoN1w658SLRPRKuwtwjp9zu/fe/i8057A46RC3+OPG4/7fLmOpJ 1RUNEPYYhpdcA== From: Conor Dooley To: sboyd@kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 7/9] riscv: dts: microchip: convert clock and reset to use syscon Date: Mon, 23 Jun 2025 13:56:21 +0100 Message-ID: <20250623-bobble-corncob-6c4e70431679@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250623-levitate-nugget-08c9a01f401d@spud> References: <20250623-levitate-nugget-08c9a01f401d@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2218; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=UH99rELY30Gno51gklgXi1R8GCrl6eHh831fS+cCFNY=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDBmRfh+Kdp1KKuifLc+kYCjJxlj+7rzhSoHGqVsiDI4u9 9uwcuG8jlIWBjEOBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAExk+mWG/04HQjw65q2WbJJk OlKyU2dV47GUujNGmZ//nVJbFVgwdxIjw/lg59rzC2StGNjzp0hfmH3+F9cBFbHi6KWF5m8v+9d v4gIA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The "subblock" clocks and reset registers on PolarFire SoC are located in the mss-top-sysreg region, alongside pinctrl and interrupt control functionality. Re-write the devicetree to describe the sys explicitly, as its own node, rather than as a region of the clock node. Correspondingly, the phandles to the reset controller must be updated to the new provider. The drivers will continue to support the old way of doing things. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/= microchip/mpfs.dtsi index f9d6bf08e7170..5c2963e269b83 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -251,11 +251,9 @@ pdma: dma-controller@3000000 { #dma-cells =3D <1>; }; =20 - clkcfg: clkcfg@20002000 { - compatible =3D "microchip,mpfs-clkcfg"; - reg =3D <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; - clocks =3D <&refclk>; - #clock-cells =3D <1>; + mss_top_sysreg: syscon@20002000 { + compatible =3D "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd"; + reg =3D <0x0 0x20002000 0x0 0x1000>; #reset-cells =3D <1>; }; =20 @@ -452,7 +450,7 @@ mac0: ethernet@20110000 { local-mac-address =3D [00 00 00 00 00 00]; clocks =3D <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; clock-names =3D "pclk", "hclk"; - resets =3D <&clkcfg CLK_MAC0>; + resets =3D <&mss_top_sysreg CLK_MAC0>; status =3D "disabled"; }; =20 @@ -466,7 +464,7 @@ mac1: ethernet@20112000 { local-mac-address =3D [00 00 00 00 00 00]; clocks =3D <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; clock-names =3D "pclk", "hclk"; - resets =3D <&clkcfg CLK_MAC1>; + resets =3D <&mss_top_sysreg CLK_MAC1>; status =3D "disabled"; }; =20 @@ -550,5 +548,12 @@ syscontroller_qspi: spi@37020100 { clocks =3D <&scbclk>; status =3D "disabled"; }; + + clkcfg: clkcfg@3e001000 { + compatible =3D "microchip,mpfs-clkcfg"; + reg =3D <0x0 0x3e001000 0x0 0x1000>; + clocks =3D <&refclk>; + #clock-cells =3D <1>; + }; }; }; --=20 2.45.2 From nobody Wed Oct 8 23:02:54 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BDC1F253B71; Mon, 23 Jun 2025 12:57:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 23 Jun 2025 12:57:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750683439; bh=EBH4dzV8nz2vAJt0ZF+dvJ35dmpskLhXzVZFwIge6PE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Z0HMbv30bAifkjQCDB+FedGI22m5DimtiAjSr+AeOFi0zwK0q9sYQUGdXQ+AILfWZ NHgQzgyCpyilxiJdQ1FShPQobdXrKqJwHOjBaSfLpB5s0QdNv/BfIzVbi2ZExsY7lt No7CvwtePWzcK3u+MLyAsvRUS6om50nDFYtqy6cAsd55fV3ZXniwz5vG4l0eEpSGc1 6Dk/VxITolD1ObayMh5KAY/OsyIDXmokM7Oi1yfOmOLJ7BDU3r1RqptTdj/hy3nbu3 JETQx+/lgbTe9Zw7MNYp7VNUFKBsWEC3DnQ2ywL/fQbzw9yOcWnJeAQ6Y0qycRmdZO jtEx/sKYAkQEg== From: Conor Dooley To: sboyd@kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 8/9] clk: divider, gate: create regmap-backed copies of gate and divider clocks Date: Mon, 23 Jun 2025 13:56:22 +0100 Message-ID: <20250623-spleen-rambling-8bd898f2788e@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250623-levitate-nugget-08c9a01f401d@spud> References: <20250623-levitate-nugget-08c9a01f401d@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=22733; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=6K4iy7GXKBlrb9HwCicSnDWt+XpYXCWJDy7A8bSesQ0=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDBmRfh9LZ929e/R68IuFX6omd5W7C767EKZVwhr2ofveZ mbX/ZPWd5SyMIhxMMiKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAixTaMDC0tZy7ucotNfzrt Hp9S6LnM+65XrIsO3v07Qzg7OO5D1ydGhr++3TGdp9uOxFf/Paj7Qmj2jdWiW01ynVY1H14u+df wIh8A X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Implement regmap-backed copies of gate and divider clocks by replacing the iomem pointer to the clock registers with a regmap and offset within. Signed-off-by: Conor Dooley --- drivers/clk/Kconfig | 8 + drivers/clk/Makefile | 2 + drivers/clk/clk-divider-regmap.c | 271 +++++++++++++++++++++++++++++++ drivers/clk/clk-gate-regmap.c | 254 +++++++++++++++++++++++++++++ include/linux/clk-provider.h | 120 ++++++++++++++ 5 files changed, 655 insertions(+) create mode 100644 drivers/clk/clk-divider-regmap.c create mode 100644 drivers/clk/clk-gate-regmap.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 19c1ed280fd7f..273154031325e 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -33,6 +33,14 @@ menuconfig COMMON_CLK =20 if COMMON_CLK =20 +config COMMON_CLK_DIVIDER_REGMAP + bool + select REGMAP + +config COMMON_CLK_GATE_REGMAP + bool + select REGMAP + config COMMON_CLK_WM831X tristate "Clock driver for WM831x/2x PMICs" depends on MFD_WM831X diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 42867cd37c33d..6dbc1fe1e03e2 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -20,11 +20,13 @@ clk-test-y :=3D clk_test.o \ kunit_clk_assigned_rates_zero_consumer.dtbo.o \ kunit_clk_parent_data_test.dtbo.o obj-$(CONFIG_COMMON_CLK) +=3D clk-divider.o +obj-$(CONFIG_COMMON_CLK_DIVIDER_REGMAP) +=3D clk-divider-regmap.o obj-$(CONFIG_COMMON_CLK) +=3D clk-fixed-factor.o obj-$(CONFIG_COMMON_CLK) +=3D clk-fixed-rate.o obj-$(CONFIG_CLK_FIXED_RATE_KUNIT_TEST) +=3D clk-fixed-rate-test.o clk-fixed-rate-test-y :=3D clk-fixed-rate_test.o kunit_clk_fixed_rate_tes= t.dtbo.o obj-$(CONFIG_COMMON_CLK) +=3D clk-gate.o +obj-$(CONFIG_COMMON_CLK_GATE_REGMAP) +=3D clk-gate-regmap.o obj-$(CONFIG_CLK_GATE_KUNIT_TEST) +=3D clk-gate_test.o obj-$(CONFIG_COMMON_CLK) +=3D clk-multiplier.o obj-$(CONFIG_COMMON_CLK) +=3D clk-mux.o diff --git a/drivers/clk/clk-divider-regmap.c b/drivers/clk/clk-divider-reg= map.c new file mode 100644 index 0000000000000..43b8f3dedb9e1 --- /dev/null +++ b/drivers/clk/clk-divider-regmap.c @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include + +static inline u32 clk_div_regmap_readl(struct clk_divider_regmap *divider) +{ + u32 val; + + regmap_read(divider->regmap, divider->map_offset, &val); + + return val; +} + +static inline void clk_div_regmap_writel(struct clk_divider_regmap *divide= r, u32 val) +{ + regmap_write(divider->regmap, divider->map_offset, val); + +} + +static unsigned long clk_divider_regmap_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_divider_regmap *divider =3D to_clk_divider_regmap(hw); + unsigned int val; + + val =3D clk_div_regmap_readl(divider) >> divider->shift; + val &=3D clk_div_mask(divider->width); + + return divider_recalc_rate(hw, parent_rate, val, divider->table, + divider->flags, divider->width); +} + +static long clk_divider_regmap_round_rate(struct clk_hw *hw, unsigned long= rate, + unsigned long *prate) +{ + struct clk_divider_regmap *divider =3D to_clk_divider_regmap(hw); + + /* if read only, just return current value */ + if (divider->flags & CLK_DIVIDER_READ_ONLY) { + u32 val; + + val =3D clk_div_regmap_readl(divider) >> divider->shift; + val &=3D clk_div_mask(divider->width); + + return divider_ro_round_rate(hw, rate, prate, divider->table, + divider->width, divider->flags, + val); + } + + return divider_round_rate(hw, rate, prate, divider->table, + divider->width, divider->flags); +} + +static int clk_divider_regmap_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_divider_regmap *divider =3D to_clk_divider_regmap(hw); + + /* if read only, just return current value */ + if (divider->flags & CLK_DIVIDER_READ_ONLY) { + u32 val; + + val =3D clk_div_regmap_readl(divider) >> divider->shift; + val &=3D clk_div_mask(divider->width); + + return divider_ro_determine_rate(hw, req, divider->table, + divider->width, + divider->flags, val); + } + + return divider_determine_rate(hw, req, divider->table, divider->width, + divider->flags); +} + +static int clk_divider_regmap_set_rate(struct clk_hw *hw, unsigned long ra= te, + unsigned long parent_rate) +{ + struct clk_divider_regmap *divider =3D to_clk_divider_regmap(hw); + int value; + unsigned long flags =3D 0; + u32 val; + + value =3D divider_get_val(rate, parent_rate, divider->table, + divider->width, divider->flags); + if (value < 0) + return value; + + if (divider->lock) + spin_lock_irqsave(divider->lock, flags); + else + __acquire(divider->lock); + + if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { + val =3D clk_div_mask(divider->width) << (divider->shift + 16); + } else { + val =3D clk_div_regmap_readl(divider); + val &=3D ~(clk_div_mask(divider->width) << divider->shift); + } + val |=3D (u32)value << divider->shift; + clk_div_regmap_writel(divider, val); + + if (divider->lock) + spin_unlock_irqrestore(divider->lock, flags); + else + __release(divider->lock); + + return 0; +} + +const struct clk_ops clk_divider_regmap_ops =3D { + .recalc_rate =3D clk_divider_regmap_recalc_rate, + .round_rate =3D clk_divider_regmap_round_rate, + .determine_rate =3D clk_divider_regmap_determine_rate, + .set_rate =3D clk_divider_regmap_set_rate, +}; +EXPORT_SYMBOL_GPL(clk_divider_regmap_ops); + +const struct clk_ops clk_divider_regmap_ro_ops =3D { + .recalc_rate =3D clk_divider_regmap_recalc_rate, + .round_rate =3D clk_divider_regmap_round_rate, + .determine_rate =3D clk_divider_regmap_determine_rate, +}; +EXPORT_SYMBOL_GPL(clk_divider_regmap_ro_ops); + +struct clk_hw *__clk_hw_register_divider_regmap(struct device *dev, + struct device_node *np, const char *name, + const char *parent_name, const struct clk_hw *parent_hw, + const struct clk_parent_data *parent_data, unsigned long flags, + struct regmap *regmap, u8 map_offset, u8 shift, u8 width, + u8 clk_divider_flags, const struct clk_div_table *table, + spinlock_t *lock) +{ + struct clk_divider_regmap *div; + struct clk_hw *hw; + struct clk_init_data init =3D {}; + int ret; + + if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) { + if (width + shift > 16) { + pr_warn("divider value exceeds LOWORD field\n"); + return ERR_PTR(-EINVAL); + } + } + + /* allocate the divider */ + div =3D kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) + return ERR_PTR(-ENOMEM); + + init.name =3D name; + if (clk_divider_flags & CLK_DIVIDER_READ_ONLY) + init.ops =3D &clk_divider_regmap_ro_ops; + else + init.ops =3D &clk_divider_regmap_ops; + init.flags =3D flags; + init.parent_names =3D parent_name ? &parent_name : NULL; + init.parent_hws =3D parent_hw ? &parent_hw : NULL; + init.parent_data =3D parent_data; + if (parent_name || parent_hw || parent_data) + init.num_parents =3D 1; + else + init.num_parents =3D 0; + + /* struct clk_divider assignments */ + div->regmap =3D regmap; + div->map_offset =3D map_offset; + div->shift =3D shift; + div->width =3D width; + div->flags =3D clk_divider_flags; + div->lock =3D lock; + div->hw.init =3D &init; + div->table =3D table; + + /* register the clock */ + hw =3D &div->hw; + ret =3D clk_hw_register(dev, hw); + if (ret) { + kfree(div); + hw =3D ERR_PTR(ret); + } + + return hw; +} +EXPORT_SYMBOL_GPL(__clk_hw_register_divider_regmap); + +struct clk *clk_register_divider_regmap_table(struct device *dev, const ch= ar *name, + const char *parent_name, unsigned long flags, + struct regmap *regmap, u8 map_offset, u8 shift, u8 width, + u8 clk_divider_flags, const struct clk_div_table *table, + spinlock_t *lock) +{ + struct clk_hw *hw; + + hw =3D __clk_hw_register_divider_regmap(dev, NULL, name, parent_name, NU= LL, + NULL, flags, regmap, map_offset, + shift, width, clk_divider_flags, + table, lock); + if (IS_ERR(hw)) + return ERR_CAST(hw); + return hw->clk; +} +EXPORT_SYMBOL_GPL(clk_register_divider_regmap_table); + +void clk_unregister_divider_regmap(struct clk *clk) +{ + struct clk_divider_regmap *div; + struct clk_hw *hw; + + hw =3D __clk_get_hw(clk); + if (!hw) + return; + + div =3D to_clk_divider_regmap(hw); + + clk_unregister(clk); + kfree(div); +} +EXPORT_SYMBOL_GPL(clk_unregister_divider_regmap); + +/** + * clk_hw_unregister_divider_regmap - unregister a clk divider + * @hw: hardware-specific clock data to unregister + */ +void clk_hw_unregister_divider_regmap(struct clk_hw *hw) +{ + struct clk_divider_regmap *div; + + div =3D to_clk_divider_regmap(hw); + + clk_hw_unregister(hw); + kfree(div); +} +EXPORT_SYMBOL_GPL(clk_hw_unregister_divider_regmap); + +static void devm_clk_hw_release_divider_regmap(struct device *dev, void *r= es) +{ + clk_hw_unregister_divider_regmap(*(struct clk_hw **)res); +} + +struct clk_hw *__devm_clk_hw_register_divider_regmap(struct device *dev, + struct device_node *np, const char *name, + const char *parent_name, const struct clk_hw *parent_hw, + const struct clk_parent_data *parent_data, unsigned long flags, + struct regmap *regmap, u8 map_offset, u8 shift, u8 width, + u8 clk_divider_flags, const struct clk_div_table *table, + spinlock_t *lock) +{ + struct clk_hw **ptr, *hw; + + ptr =3D devres_alloc(devm_clk_hw_release_divider_regmap, sizeof(*ptr), GF= P_KERNEL); + if (!ptr) + return ERR_PTR(-ENOMEM); + + hw =3D __clk_hw_register_divider_regmap(dev, np, name, parent_name, paren= t_hw, + parent_data, flags, regmap, map_offset, + shift, width, clk_divider_flags, table, + lock); + + if (!IS_ERR(hw)) { + *ptr =3D hw; + devres_add(dev, ptr); + } else { + devres_free(ptr); + } + + return hw; +} +EXPORT_SYMBOL_GPL(__devm_clk_hw_register_divider_regmap); diff --git a/drivers/clk/clk-gate-regmap.c b/drivers/clk/clk-gate-regmap.c new file mode 100644 index 0000000000000..05d61c1c3c3df --- /dev/null +++ b/drivers/clk/clk-gate-regmap.c @@ -0,0 +1,254 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * DOC: basic gatable clock which can gate and ungate its output + * + * Traits of this clock: + * prepare - clk_(un)prepare only ensures parent is (un)prepared + * enable - clk_enable and clk_disable are functional & control gating + * rate - inherits rate from parent. No clk_set_rate support + * parent - fixed parent. No clk_set_parent support + */ + +static inline u32 clk_gate_regmap_readl(struct clk_gate_regmap *gate) +{ + u32 val; + + regmap_read(gate->map, gate->map_offset, &val); + + return val; +} + +static inline void clk_gate_regmap_writel(struct clk_gate_regmap *gate, u3= 2 val) +{ + regmap_write(gate->map, gate->map_offset, val); + +} + +/* + * It works on following logic: + * + * For enabling clock, enable =3D 1 + * set2dis =3D 1 -> clear bit -> set =3D 0 + * set2dis =3D 0 -> set bit -> set =3D 1 + * + * For disabling clock, enable =3D 0 + * set2dis =3D 1 -> set bit -> set =3D 1 + * set2dis =3D 0 -> clear bit -> set =3D 0 + * + * So, result is always: enable xor set2dis. + */ +static void clk_gate_regmap_endisable(struct clk_hw *hw, int enable) +{ + struct clk_gate_regmap *gate =3D to_clk_gate_regmap(hw); + int set =3D gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; + unsigned long flags; + u32 reg; + + set ^=3D enable; + + if (gate->lock) + spin_lock_irqsave(gate->lock, flags); + else + __acquire(gate->lock); + + if (gate->flags & CLK_GATE_HIWORD_MASK) { + reg =3D BIT(gate->bit_idx + 16); + if (set) + reg |=3D BIT(gate->bit_idx); + } else { + reg =3D clk_gate_regmap_readl(gate); + + if (set) + reg |=3D BIT(gate->bit_idx); + else + reg &=3D ~BIT(gate->bit_idx); + } + + clk_gate_regmap_writel(gate, reg); + + if (gate->lock) + spin_unlock_irqrestore(gate->lock, flags); + else + __release(gate->lock); +} + +static int clk_gate_regmap_enable(struct clk_hw *hw) +{ + clk_gate_regmap_endisable(hw, 1); + + return 0; +} + +static void clk_gate_regmap_disable(struct clk_hw *hw) +{ + clk_gate_regmap_endisable(hw, 0); +} + +int clk_gate_regmap_is_enabled(struct clk_hw *hw) +{ + u32 reg; + struct clk_gate_regmap *gate =3D to_clk_gate_regmap(hw); + + reg =3D clk_gate_regmap_readl(gate); + + /* if a set bit disables this clk, flip it before masking */ + if (gate->flags & CLK_GATE_SET_TO_DISABLE) + reg ^=3D BIT(gate->bit_idx); + + reg &=3D BIT(gate->bit_idx); + + return reg ? 1 : 0; +} +EXPORT_SYMBOL_GPL(clk_gate_regmap_is_enabled); + +const struct clk_ops clk_gate_regmap_ops =3D { + .enable =3D clk_gate_regmap_enable, + .disable =3D clk_gate_regmap_disable, + .is_enabled =3D clk_gate_regmap_is_enabled, +}; +EXPORT_SYMBOL_GPL(clk_gate_regmap_ops); + +struct clk_hw *__clk_hw_register_gate_regmap(struct device *dev, + struct device_node *np, const char *name, + const char *parent_name, const struct clk_hw *parent_hw, + const struct clk_parent_data *parent_data, + unsigned long flags, + struct regmap *map, u8 map_offset, u8 bit_idx, + u8 clk_gate_flags, spinlock_t *lock) +{ + struct clk_gate_regmap *gate; + struct clk_hw *hw; + struct clk_init_data init =3D {}; + int ret =3D -EINVAL; + + if (clk_gate_flags & CLK_GATE_HIWORD_MASK) { + if (bit_idx > 15) { + pr_err("gate bit exceeds LOWORD field\n"); + return ERR_PTR(-EINVAL); + } + } + + /* allocate the gate */ + gate =3D kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + init.name =3D name; + init.ops =3D &clk_gate_regmap_ops; + init.flags =3D flags; + init.parent_names =3D parent_name ? &parent_name : NULL; + init.parent_hws =3D parent_hw ? &parent_hw : NULL; + init.parent_data =3D parent_data; + if (parent_name || parent_hw || parent_data) + init.num_parents =3D 1; + else + init.num_parents =3D 0; + + /* struct clk_gate_regmap assignments */ + gate->map =3D map; + gate->map_offset =3D map_offset; + gate->bit_idx =3D bit_idx; + gate->flags =3D clk_gate_flags; + gate->lock =3D lock; + gate->hw.init =3D &init; + + hw =3D &gate->hw; + if (dev || !np) + ret =3D clk_hw_register(dev, hw); + else if (np) + ret =3D of_clk_hw_register(np, hw); + if (ret) { + kfree(gate); + hw =3D ERR_PTR(ret); + } + + return hw; + +} +EXPORT_SYMBOL_GPL(__clk_hw_register_gate_regmap); + +struct clk *clk_register_gate_regmap(struct device *dev, const char *name, + const char *parent_name, unsigned long flags, struct regmap *map, + u8 map_offset, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock) +{ + struct clk_hw *hw; + + hw =3D __clk_hw_register_gate_regmap(dev, NULL, name, parent_name, NULL, + NULL, flags, map, map_offset, bit_idx, + clk_gate_flags, lock); + if (IS_ERR(hw)) + return ERR_CAST(hw); + return hw->clk; +} +EXPORT_SYMBOL_GPL(clk_register_gate_regmap); + +void clk_unregister_gate_regmap(struct clk *clk) +{ + struct clk_gate_regmap *gate; + struct clk_hw *hw; + + hw =3D __clk_get_hw(clk); + if (!hw) + return; + + gate =3D to_clk_gate_regmap(hw); + + clk_unregister(clk); + kfree(gate); +} +EXPORT_SYMBOL_GPL(clk_unregister_gate_regmap); + +void clk_hw_unregister_gate_regmap(struct clk_hw *hw) +{ + struct clk_gate_regmap *gate; + + gate =3D to_clk_gate_regmap(hw); + + clk_hw_unregister(hw); + kfree(gate); +} +EXPORT_SYMBOL_GPL(clk_hw_unregister_gate_regmap); + +static void devm_clk_hw_release_gate_regmap(struct device *dev, void *res) +{ + clk_hw_unregister_gate_regmap(*(struct clk_hw **)res); +} + +struct clk_hw *__devm_clk_hw_register_gate_regmap(struct device *dev, + struct device_node *np, const char *name, + const char *parent_name, const struct clk_hw *parent_hw, + const struct clk_parent_data *parent_data, + unsigned long flags, struct regmap *map, + u8 map_offset, u8 bit_idx, + u8 clk_gate_flags, spinlock_t *lock) +{ + struct clk_hw **ptr, *hw; + + ptr =3D devres_alloc(devm_clk_hw_release_gate_regmap, sizeof(*ptr), GFP_K= ERNEL); + if (!ptr) + return ERR_PTR(-ENOMEM); + + hw =3D __clk_hw_register_gate_regmap(dev, np, name, parent_name, parent_h= w, + parent_data, flags, map, map_offset, + bit_idx, clk_gate_flags, lock); + + if (!IS_ERR(hw)) { + *ptr =3D hw; + devres_add(dev, ptr); + } else { + devres_free(ptr); + } + + return hw; +} +EXPORT_SYMBOL_GPL(__devm_clk_hw_register_gate_regmap); diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 2e6e603b74934..6f5cf6670b48d 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -8,6 +8,7 @@ =20 #include #include +#include =20 /* * flags used across common struct clk. these flags should only affect the @@ -526,6 +527,7 @@ void of_fixed_clk_setup(struct device_node *np); struct clk_gate { struct clk_hw hw; void __iomem *reg; + u8 map_offset; u8 bit_idx; u8 flags; spinlock_t *lock; @@ -538,6 +540,37 @@ struct clk_gate { #define CLK_GATE_BIG_ENDIAN BIT(2) =20 extern const struct clk_ops clk_gate_ops; + +#ifdef CONFIG_COMMON_CLK_GATE_REGMAP +/** + * struct clk_gate_regmap - gating clock via regmap + * + * @hw: handle between common and hardware-specific interfaces + * @map: regmap controlling gate + * @map_offset: register offset within the regmap controlling gate + * @bit_idx: single bit controlling gate + * @flags: hardware-specific flags + * @lock: register lock + * + * Clock which can gate its output. Implements .enable & .disable + * + * Flags: + * See clk_gate + */ +struct clk_gate_regmap { + struct clk_hw hw; + struct regmap *map; + u8 map_offset; + u8 bit_idx; + u8 flags; + spinlock_t *lock; +}; + +#define to_clk_gate_regmap(_hw) container_of(_hw, struct clk_gate_regmap, = hw) + +extern const struct clk_ops clk_gate_regmap_ops; +#endif + struct clk_hw *__clk_hw_register_gate(struct device *dev, struct device_node *np, const char *name, const char *parent_name, const struct clk_hw *parent_hw, @@ -663,6 +696,31 @@ void clk_unregister_gate(struct clk *clk); void clk_hw_unregister_gate(struct clk_hw *hw); int clk_gate_is_enabled(struct clk_hw *hw); =20 +#ifdef CONFIG_COMMON_CLK_GATE_REGMAP +struct clk_hw *__clk_hw_register_gate_regmap(struct device *dev, + struct device_node *np, const char *name, + const char *parent_name, const struct clk_hw *parent_hw, + const struct clk_parent_data *parent_data, + unsigned long flags, + struct regmap *map, u8 map_offset, u8 bit_idx, + u8 clk_gate_flags, spinlock_t *lock); +struct clk_hw *__devm_clk_hw_register_gate_regmap(struct device *dev, + struct device_node *np, const char *name, + const char *parent_name, const struct clk_hw *parent_hw, + const struct clk_parent_data *parent_data, + unsigned long flags, + struct regmap *map, u8 map_offset, u8 bit_idx, + u8 clk_gate_flags, spinlock_t *lock); +struct clk *clk_register_gate_regmap(struct device *dev, const char *name, + const char *parent_name, unsigned long flags, + struct regmap *map, u8 map_offset, u8 bit_idx, + u8 clk_gate_flags, spinlock_t *lock); + +void clk_unregister_gate_regmap(struct clk *clk); +void clk_hw_unregister_gate_regmap(struct clk_hw *hw); +int clk_gate_regmap_is_enabled(struct clk_hw *hw); +#endif + struct clk_div_table { unsigned int val; unsigned int div; @@ -736,6 +794,41 @@ struct clk_divider { extern const struct clk_ops clk_divider_ops; extern const struct clk_ops clk_divider_ro_ops; =20 +#ifdef CONFIG_COMMON_CLK_DIVIDER_REGMAP +/** + * struct clk_divider_regmap - adjustable divider clock via regmap + * + * @hw: handle between common and hardware-specific interfaces + * @map: regmap containing the divider + * @map_offset: register offset within the regmap containing the divider + * @shift: shift to the divider bit field + * @width: width of the divider bit field + * @table: array of value/divider pairs, last entry should have div =3D 0 + * @lock: register lock + * + * Clock with an adjustable divider affecting its output frequency. Imple= ments + * .recalc_rate, .set_rate and .round_rate + * + * @flags: + * See clk_divider + */ +struct clk_divider_regmap { + struct clk_hw hw; + struct regmap *regmap; + u8 map_offset; + u8 shift; + u8 width; + u8 flags; + const struct clk_div_table *table; + spinlock_t *lock; +}; + +#define to_clk_divider_regmap(_hw) container_of(_hw, struct clk_divider_re= gmap, hw) + +extern const struct clk_ops clk_divider_regmap_ops; +extern const struct clk_ops clk_divider_regmap_ro_ops; +#endif + unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_= rate, unsigned int val, const struct clk_div_table *table, unsigned long flags, unsigned long width); @@ -972,6 +1065,33 @@ struct clk *clk_register_divider_table(struct device = *dev, const char *name, void clk_unregister_divider(struct clk *clk); void clk_hw_unregister_divider(struct clk_hw *hw); =20 +#ifdef CONFIG_COMMON_CLK_DIVIDER_REGMAP +struct clk_hw *__clk_hw_register_divider_regmap(struct device *dev, + struct device_node *np, const char *name, + const char *parent_name, const struct clk_hw *parent_hw, + const struct clk_parent_data *parent_data, unsigned long flags, + struct regmap *regmap, u8 map_offset, u8 shift, u8 width, + u8 clk_divider_flags, const struct clk_div_table *table, + spinlock_t *lock); + +struct clk_hw *__devm_clk_hw_register_divider_regmap(struct device *dev, + struct device_node *np, const char *name, + const char *parent_name, const struct clk_hw *parent_hw, + const struct clk_parent_data *parent_data, unsigned long flags, + struct regmap *regmap, u8 map_offset, u8 shift, u8 width, + u8 clk_divider_flags, const struct clk_div_table *table, + spinlock_t *lock); + +struct clk *clk_register_divider_regmap_table(struct device *dev, + const char *name, const char *parent_name, unsigned long flags, + struct regmap *regmap, u8 map_offset, u8 shift, u8 width, + u8 clk_divider_flags, const struct clk_div_table *table, + spinlock_t *lock); + +void clk_unregister_divider_regmap(struct clk *clk); +void clk_hw_unregister_divider_regmap(struct clk_hw *hw); +#endif + /** * struct clk_mux - multiplexer clock * --=20 2.45.2 From nobody Wed Oct 8 23:02:54 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34CD5253F12; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="uBWjM6uC" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C7E32C4CEF2; Mon, 23 Jun 2025 12:57:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750683443; bh=nDmXGid+HX75bqpdmYZ2WxwC0IlRF4aAoqhrrbUmWe8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uBWjM6uCOi7S9/o7F4oIwb/r48WO6CwD7lR4NY42WkXRDDcAJvqKyb/UR+zJ0eLG2 pbFAW7vuPkeiOJ5fuaT7YK7AMMZjif1wLdlsDo4oOAzpdn9nVa7y3o+3X1ihYp15l4 iWTXt21vk/urVSi6ZJyO+eSaEi5nHghGZ3Futk7cshRJHdsTAMFtq86TBkvqN3CcMS MjNf134gsEMkoPx6AQlwAgkxnfh+YbHAotstXyMdH95WZf23103Ozr61XSn54zOEKG LqLy6u2cvERWKe+mLoIfIOoFAZcqud3QJEgzajYMcm3XtMrTXXS8YqDElHQcXDK5eY Uu45OG345dkUg== From: Conor Dooley To: sboyd@kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 9/9] clk: microchip: mpfs: use regmap clock types Date: Mon, 23 Jun 2025 13:56:23 +0100 Message-ID: <20250623-battering-cable-b61e1047d180@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250623-levitate-nugget-08c9a01f401d@spud> References: <20250623-levitate-nugget-08c9a01f401d@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=10031; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=GO9ApPaEu2krjObe/V++g6BUriuEocKEs23aw1DaxIU=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDBmRfh9fmf8x9X92rMnWcMJVPh6T5U7R16u2W6U2R2gcs HnDkZTaUcrCIMbBICumyJJ4u69Fav0flx3OPW9h5rAygQxh4OIUgIkoTGL473HlqMmVgplXrJMX KfGLHln4dPO/0EltE+6f9N4q+mqq4VpGht95zwUFQxfZcXQ+Vpicl3ig3mODfZ9crf/i7Fm9au9 6WQA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Convert the PolarFire SoC clock driver to use regmap clock types as a preparatory work for supporting the new binding for this device that will only provide the second of the two register regions, and will require the use of syscon regmap to access the "cfg" and "periph" clocks currently supported by the driver. Signed-off-by: Conor Dooley --- drivers/clk/microchip/Kconfig | 4 + drivers/clk/microchip/clk-mpfs.c | 151 ++++++++++++++++++++----------- 2 files changed, 101 insertions(+), 54 deletions(-) diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig index 0724ce65898f3..cab9a909893b2 100644 --- a/drivers/clk/microchip/Kconfig +++ b/drivers/clk/microchip/Kconfig @@ -7,6 +7,10 @@ config MCHP_CLK_MPFS bool "Clk driver for PolarFire SoC" depends on ARCH_MICROCHIP_POLARFIRE || COMPILE_TEST default ARCH_MICROCHIP_POLARFIRE + depends on MFD_SYSCON select AUXILIARY_BUS + select COMMON_CLK_DIVIDER_REGMAP + select COMMON_CLK_GATE_REGMAP + select REGMAP_MMIO help Supports Clock Configuration for PolarFire SoC diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-m= pfs.c index c22632a7439c5..c7fec0fcbe379 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -6,8 +6,10 @@ */ #include #include +#include #include #include +#include #include #include =20 @@ -30,6 +32,14 @@ #define MSSPLL_POSTDIV_WIDTH 0x07u #define MSSPLL_FIXED_DIV 4u =20 +static const struct regmap_config clk_mpfs_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .val_format_endian =3D REGMAP_ENDIAN_LITTLE, + .max_register =3D REG_SUBBLK_CLOCK_CR, +}; + /* * This clock ID is defined here, rather than the binding headers, as it i= s an * internal clock only, and therefore has no consumers in other peripheral @@ -39,6 +49,7 @@ =20 struct mpfs_clock_data { struct device *dev; + struct regmap *regmap; void __iomem *base; void __iomem *msspll_base; struct clk_hw_onecell_data hw_data; @@ -68,14 +79,12 @@ struct mpfs_msspll_out_hw_clock { #define to_mpfs_msspll_out_clk(_hw) container_of(_hw, struct mpfs_msspll_o= ut_hw_clock, hw) =20 struct mpfs_cfg_hw_clock { - struct clk_divider cfg; - struct clk_init_data init; + struct clk_divider_regmap divider; unsigned int id; - u32 reg_offset; }; =20 struct mpfs_periph_hw_clock { - struct clk_gate periph; + struct clk_gate_regmap gate; unsigned int id; }; =20 @@ -172,15 +181,15 @@ static int mpfs_clk_register_mssplls(struct device *d= ev, struct mpfs_msspll_hw_c * MSS PLL output clocks */ =20 -#define CLK_PLL_OUT(_id, _name, _parent, _flags, _shift, _width, _offset) = { \ - .id =3D _id, \ - .output.shift =3D _shift, \ - .output.width =3D _width, \ - .output.table =3D NULL, \ - .reg_offset =3D _offset, \ - .output.flags =3D _flags, \ - .output.hw.init =3D CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \ - .output.lock =3D &mpfs_clk_lock, \ +#define CLK_PLL_OUT(_id, _name, _parent, _flags, _shift, _width, _offset) = { \ + .id =3D _id, \ + .output.shift =3D _shift, \ + .output.width =3D _width, \ + .output.table =3D NULL, \ + .reg_offset =3D _offset, \ + .output.flags =3D _flags, \ + .output.hw.init =3D CLK_HW_INIT(_name, _parent, &clk_divider_regmap_ops, = 0), \ + .output.lock =3D &mpfs_clk_lock, \ } =20 static struct mpfs_msspll_out_hw_clock mpfs_msspll_out_clks[] =3D { @@ -220,15 +229,14 @@ static int mpfs_clk_register_msspll_outs(struct devic= e *dev, * "CFG" clocks */ =20 -#define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offs= et) { \ - .id =3D _id, \ - .cfg.shift =3D _shift, \ - .cfg.width =3D _width, \ - .cfg.table =3D _table, \ - .reg_offset =3D _offset, \ - .cfg.flags =3D _flags, \ - .cfg.hw.init =3D CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \ - .cfg.lock =3D &mpfs_clk_lock, \ +#define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offs= et) { \ + .id =3D _id, \ + .divider.shift =3D _shift, \ + .divider.width =3D _width, \ + .divider.table =3D _table, \ + .divider.map_offset =3D _offset, \ + .divider.flags =3D _flags, \ + .divider.hw.init =3D CLK_HW_INIT(_name, _parent, &clk_divider_regmap_ops,= 0), \ } =20 #define CLK_CPU_OFFSET 0u @@ -245,13 +253,13 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] =3D { REG_CLOCK_CONFIG_CR), { .id =3D CLK_RTCREF, - .cfg.shift =3D 0, - .cfg.width =3D 12, - .cfg.table =3D mpfs_div_rtcref_table, - .reg_offset =3D REG_RTC_CLOCK_CR, - .cfg.flags =3D CLK_DIVIDER_ONE_BASED, - .cfg.hw.init =3D - CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_divider_ops, = 0), + .divider.shift =3D 0, + .divider.width =3D 12, + .divider.table =3D mpfs_div_rtcref_table, + .divider.map_offset =3D REG_RTC_CLOCK_CR, + .divider.flags =3D CLK_DIVIDER_ONE_BASED, + .divider.hw.init =3D + CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_divider_regma= p_ops, 0), } }; =20 @@ -264,14 +272,14 @@ static int mpfs_clk_register_cfgs(struct device *dev,= struct mpfs_cfg_hw_clock * for (i =3D 0; i < num_clks; i++) { struct mpfs_cfg_hw_clock *cfg_hw =3D &cfg_hws[i]; =20 - cfg_hw->cfg.reg =3D data->base + cfg_hw->reg_offset; - ret =3D devm_clk_hw_register(dev, &cfg_hw->cfg.hw); + cfg_hw->divider.regmap =3D data->regmap; + ret =3D devm_clk_hw_register(dev, &cfg_hw->divider.hw); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", cfg_hw->id); =20 id =3D cfg_hw->id; - data->hw_data.hws[id] =3D &cfg_hw->cfg.hw; + data->hw_data.hws[id] =3D &cfg_hw->divider.hw; } =20 return 0; @@ -281,15 +289,14 @@ static int mpfs_clk_register_cfgs(struct device *dev,= struct mpfs_cfg_hw_clock * * peripheral clocks - devices connected to axi or ahb buses. */ =20 -#define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ - .id =3D _id, \ - .periph.bit_idx =3D _shift, \ - .periph.hw.init =3D CLK_HW_INIT_HW(_name, _parent, &clk_gate_ops, \ - _flags), \ - .periph.lock =3D &mpfs_clk_lock, \ +#define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ + .id =3D _id, \ + .gate.map_offset =3D REG_SUBBLK_CLOCK_CR, \ + .gate.bit_idx =3D _shift, \ + .gate.hw.init =3D CLK_HW_INIT_HW(_name, _parent, &clk_gate_regmap_ops, _f= lags), \ } =20 -#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].cfg.hw) +#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].divider.= hw) =20 /* * Critical clocks: @@ -346,19 +353,60 @@ static int mpfs_clk_register_periphs(struct device *d= ev, struct mpfs_periph_hw_c for (i =3D 0; i < num_clks; i++) { struct mpfs_periph_hw_clock *periph_hw =3D &periph_hws[i]; =20 - periph_hw->periph.reg =3D data->base + REG_SUBBLK_CLOCK_CR; - ret =3D devm_clk_hw_register(dev, &periph_hw->periph.hw); + periph_hw->gate.map =3D data->regmap; + ret =3D devm_clk_hw_register(dev, &periph_hw->gate.hw); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", periph_hw->id); =20 id =3D periph_hws[i].id; - data->hw_data.hws[id] =3D &periph_hw->periph.hw; + data->hw_data.hws[id] =3D &periph_hw->gate.hw; } =20 return 0; } =20 +static inline int mpfs_clk_syscon_probe(struct mpfs_clock_data *clk_data, + struct platform_device *pdev) +{ + clk_data->regmap =3D syscon_regmap_lookup_by_compatible("microchip,mpfs-m= ss-top-sysreg"); + if (IS_ERR(clk_data->regmap)) + return PTR_ERR(clk_data->regmap); + + clk_data->msspll_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(clk_data->msspll_base)) + return PTR_ERR(clk_data->msspll_base); + + return 0; +} + +static inline int mpfs_clk_old_format_probe(struct mpfs_clock_data *clk_da= ta, + struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + int ret; + + dev_warn(&pdev->dev, "falling back to old devicetree format"); + + clk_data->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(clk_data->base)) + return PTR_ERR(clk_data->base); + + clk_data->msspll_base =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(clk_data->msspll_base)) + return PTR_ERR(clk_data->msspll_base); + + clk_data->regmap =3D devm_regmap_init_mmio(dev, clk_data->base, &clk_mpfs= _regmap_config); + if (IS_ERR(clk_data->regmap)) + return PTR_ERR(clk_data->regmap); + + ret =3D mpfs_reset_controller_register(dev, clk_data->base + REG_SUBBLK_R= ESET_CR); + if (ret) + return ret; + + return 0; +} + static int mpfs_clk_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -374,13 +422,12 @@ static int mpfs_clk_probe(struct platform_device *pde= v) if (!clk_data) return -ENOMEM; =20 - clk_data->base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(clk_data->base)) - return PTR_ERR(clk_data->base); - - clk_data->msspll_base =3D devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(clk_data->msspll_base)) - return PTR_ERR(clk_data->msspll_base); + ret =3D mpfs_clk_syscon_probe(clk_data, pdev); + if (ret) { + ret =3D mpfs_clk_old_format_probe(clk_data, pdev); + if (ret) + return ret; + } =20 clk_data->hw_data.num =3D num_clks; clk_data->dev =3D dev; @@ -406,11 +453,7 @@ static int mpfs_clk_probe(struct platform_device *pdev) if (ret) return ret; =20 - ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data= ->hw_data); - if (ret) - return ret; - - return mpfs_reset_controller_register(dev, clk_data->base + REG_SUBBLK_RE= SET_CR); + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data-= >hw_data); } =20 static const struct of_device_id mpfs_clk_of_match_table[] =3D { --=20 2.45.2