From nobody Wed Oct 8 23:45:33 2025 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63DDF244666 for ; Mon, 23 Jun 2025 11:44:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750679075; cv=none; b=dO925sw7HZgVii4l10jeAropr8O7aDdBBjq8X1poLzNyrUPw5ntaCdL7a9Ih7lvXY42odG196XP/Md14mk3mlV6HrDrO3Z3PJLZEnx1futeTzetW5y9nUQcqrc4oJVbrMMrQG5HBZ8PQcZ2u7Y9UhIeex3gim1w0cGZ/Tn5XCGQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750679075; c=relaxed/simple; bh=pVNLhqNDvIhCiYJPkL2G2BS6yViAr7qWLnWYCbwdFlk=; h=From:Date:Subject:MIME-Version:Message-Id:In-Reply-To:To:Cc: Content-Type:References; b=Vaf1NZ59HVKAduBwoiGgSQnNs5TPfZ/ygzsZ3mL24uci8fZEKRxSF7zfmbBXgxQZuSKMgKKEfDQ8K7sDWkCq64YDRa4sh2DUTF4/E14gqrIvFhJIU3K9l7mk9fzA6bWFeqhAXVY107Q9wp10sOUomM3/+p174sDgCqBjsSQZZ5Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=VgHprvwv; arc=none smtp.client-ip=210.118.77.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="VgHprvwv" Received: from eucas1p2.samsung.com (unknown [182.198.249.207]) by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id 20250623114431euoutp0245f684b612446f3aab39467ac07f780f~LqVbvWePE1765417654euoutp02I for ; Mon, 23 Jun 2025 11:44:31 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com 20250623114431euoutp0245f684b612446f3aab39467ac07f780f~LqVbvWePE1765417654euoutp02I DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1750679071; bh=CHY7JtLCmM9WXe/qJzMYeRnA6r8urLtqusF0buZM0dc=; h=From:Date:Subject:In-Reply-To:To:Cc:References:From; b=VgHprvwvUDhSQBMgHxstXpxErqV9cOO5dlMK0PfyVUdfwH2khz1CYuvqU6ahEogEg OmrihZJJ5IQcITC0hrQPbQkB1a0TN36Wa4gajXhlBeUeUQhbXvOg8X+u976q55OtjH QCH53cFweum60UP0as/ZFW5oLK2qoZcB9LP9wmkw= Received: from eusmtip1.samsung.com (unknown [203.254.199.221]) by eucas1p2.samsung.com (KnoxPortal) with ESMTPA id 20250623114430eucas1p2a5bb2bbc0049186ff25e1b3e1a131ca2~LqVbMzqXV1758917589eucas1p27; Mon, 23 Jun 2025 11:44:30 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250623114429eusmtip16bdb8d6c8ca58da83b3797f79dc5402d~LqVaIJBsY1396413964eusmtip1G; Mon, 23 Jun 2025 11:44:29 +0000 (GMT) From: Michal Wilczynski Date: Mon, 23 Jun 2025 13:42:39 +0200 Subject: [PATCH v6 1/8] power: sequencing: Add T-HEAD TH1520 GPU power sequencer driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20250623-apr_14_for_sending-v6-1-6583ce0f6c25@samsung.com> In-Reply-To: <20250623-apr_14_for_sending-v6-0-6583ce0f6c25@samsung.com> To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org X-Mailer: b4 0.15-dev X-CMS-MailID: 20250623114430eucas1p2a5bb2bbc0049186ff25e1b3e1a131ca2 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20250623114430eucas1p2a5bb2bbc0049186ff25e1b3e1a131ca2 X-EPHeader: CA X-CMS-RootMailID: 20250623114430eucas1p2a5bb2bbc0049186ff25e1b3e1a131ca2 References: <20250623-apr_14_for_sending-v6-0-6583ce0f6c25@samsung.com> Introduce the pwrseq-thead-gpu driver, a power sequencer provider for the Imagination BXM-4-64 GPU on the T-HEAD TH1520 SoC. This driver controls an auxiliary device instantiated by the AON power domain. The TH1520 GPU requires a specific sequence to correctly initialize and power down its resources: - Enable GPU clocks (core and sys). - De-assert the GPU clock generator reset (clkgen_reset). - Introduce a short hardware-required delay. - De-assert the GPU core reset. The power-down sequence performs these steps in reverse. Implement this sequence via the pwrseq_power_on and pwrseq_power_off callbacks. Crucially, the driver's match function is called when a consumer (the Imagination GPU driver) requests the "gpu-power" target. During this match, the sequencer uses clk_bulk_get() and reset_control_get_exclusive() on the consumer's device to obtain handles to the GPU's "core" and "sys" clocks, and the GPU core reset. These, along with clkgen_reset obtained from parent aon node, allow it to perform the complete sequence. Reviewed-by: Ulf Hansson Signed-off-by: Michal Wilczynski --- MAINTAINERS | 1 + drivers/power/sequencing/Kconfig | 8 + drivers/power/sequencing/Makefile | 1 + drivers/power/sequencing/pwrseq-thead-gpu.c | 247 ++++++++++++++++++++++++= ++++ 4 files changed, 257 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0183c028fa18c397d30ec82fd419894f1f50a448..3283ff592215249bcf702dbb4ab= 710477243477e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21395,6 +21395,7 @@ F: drivers/mailbox/mailbox-th1520.c F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c F: drivers/pinctrl/pinctrl-th1520.c F: drivers/pmdomain/thead/ +F: drivers/power/sequencing/pwrseq-thead-gpu.c F: drivers/reset/reset-th1520.c F: include/dt-bindings/clock/thead,th1520-clk-ap.h F: include/dt-bindings/power/thead,th1520-power.h diff --git a/drivers/power/sequencing/Kconfig b/drivers/power/sequencing/Kc= onfig index ddcc42a984921c55667c46ac586d259625e1f1a7..0f118d57c1ceddc03954c006f99= b5990acf546d4 100644 --- a/drivers/power/sequencing/Kconfig +++ b/drivers/power/sequencing/Kconfig @@ -27,4 +27,12 @@ config POWER_SEQUENCING_QCOM_WCN this driver is needed for correct power control or else we'd risk not respecting the required delays between enabling Bluetooth and WLAN. =20 +config POWER_SEQUENCING_TH1520_GPU + tristate "T-HEAD TH1520 GPU power sequencing driver" + depends on ARCH_THEAD && AUXILIARY_BUS + help + Say Y here to enable the power sequencing driver for the TH1520 SoC + GPU. This driver handles the complex clock and reset sequence + required to power on the Imagination BXM GPU on this platform. + endif diff --git a/drivers/power/sequencing/Makefile b/drivers/power/sequencing/M= akefile index 2eec2df7912d11827f9ba914177dd2c882e44bce..96c1cf0a98ac54c9c1d65a4bb4e= 34289a3550fa1 100644 --- a/drivers/power/sequencing/Makefile +++ b/drivers/power/sequencing/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_POWER_SEQUENCING) +=3D pwrseq-core.o pwrseq-core-y :=3D core.o =20 obj-$(CONFIG_POWER_SEQUENCING_QCOM_WCN) +=3D pwrseq-qcom-wcn.o +obj-$(CONFIG_POWER_SEQUENCING_TH1520_GPU) +=3D pwrseq-thead-gpu.o diff --git a/drivers/power/sequencing/pwrseq-thead-gpu.c b/drivers/power/se= quencing/pwrseq-thead-gpu.c new file mode 100644 index 0000000000000000000000000000000000000000..f267f95b5d0468b21eba15e633e= f39fce2cc503f --- /dev/null +++ b/drivers/power/sequencing/pwrseq-thead-gpu.c @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * T-HEAD TH1520 GPU Power Sequencer Driver + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + * + * This driver implements the power sequence for the Imagination BXM-4-64 + * GPU on the T-HEAD TH1520 SoC. The sequence requires coordinating resour= ces + * from both the sequencer's parent device node (clkgen_reset) and the GPU= 's + * device node (clocks and core reset). + * + * The `match` function is used to acquire the GPU's resources when the + * GPU driver requests the "gpu-power" sequence target. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +struct pwrseq_thead_gpu_ctx { + struct pwrseq_device *pwrseq; + struct reset_control *clkgen_reset; + struct device_node *aon_node; + + /* Consumer resources */ + struct device_node *consumer_node; + struct clk_bulk_data *clks; + int num_clks; + struct reset_control *gpu_reset; +}; + +static int pwrseq_thead_gpu_enable(struct pwrseq_device *pwrseq) +{ + struct pwrseq_thead_gpu_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + int ret; + + if (!ctx->clks || !ctx->gpu_reset) + return -ENODEV; + + ret =3D clk_bulk_prepare_enable(ctx->num_clks, ctx->clks); + if (ret) + return ret; + + ret =3D reset_control_deassert(ctx->clkgen_reset); + if (ret) + goto err_disable_clks; + + /* + * According to the hardware manual, a delay of at least 32 clock + * cycles is required between de-asserting the clkgen reset and + * de-asserting the GPU reset. Assuming a worst-case scenario with + * a very high GPU clock frequency, a delay of 1 microsecond is + * sufficient to ensure this requirement is met across all + * feasible GPU clock speeds. + */ + udelay(1); + + ret =3D reset_control_deassert(ctx->gpu_reset); + if (ret) + goto err_assert_clkgen; + + return 0; + +err_assert_clkgen: + reset_control_assert(ctx->clkgen_reset); +err_disable_clks: + clk_bulk_disable_unprepare(ctx->num_clks, ctx->clks); + return ret; +} + +static int pwrseq_thead_gpu_disable(struct pwrseq_device *pwrseq) +{ + struct pwrseq_thead_gpu_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + int ret =3D 0, err; + + if (!ctx->clks || !ctx->gpu_reset) + return -ENODEV; + + err =3D reset_control_assert(ctx->gpu_reset); + if (err) + ret =3D err; + + err =3D reset_control_assert(ctx->clkgen_reset); + if (err && !ret) + ret =3D err; + + clk_bulk_disable_unprepare(ctx->num_clks, ctx->clks); + + /* ret stores values of the first error code */ + return ret; +} + +static const struct pwrseq_unit_data pwrseq_thead_gpu_unit =3D { + .name =3D "gpu-power-sequence", + .enable =3D pwrseq_thead_gpu_enable, + .disable =3D pwrseq_thead_gpu_disable, +}; + +static const struct pwrseq_target_data pwrseq_thead_gpu_target =3D { + .name =3D "gpu-power", + .unit =3D &pwrseq_thead_gpu_unit, +}; + +static const struct pwrseq_target_data *pwrseq_thead_gpu_targets[] =3D { + &pwrseq_thead_gpu_target, + NULL +}; + +static int pwrseq_thead_gpu_match(struct pwrseq_device *pwrseq, + struct device *dev) +{ + struct pwrseq_thead_gpu_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + static const char *const clk_names[] =3D { "core", "sys" }; + struct of_phandle_args pwr_spec; + int i, ret; + + /* We only match the specific T-HEAD TH1520 GPU compatible */ + if (!of_device_is_compatible(dev->of_node, "thead,th1520-gpu")) + return 0; + + ret =3D of_parse_phandle_with_args(dev->of_node, "power-domains", + "#power-domain-cells", 0, &pwr_spec); + if (ret) + return 0; + + /* Additionally verify consumer device has AON as power-domain */ + if (pwr_spec.np !=3D ctx->aon_node || pwr_spec.args[0] !=3D TH1520_GPU_PD= ) { + of_node_put(pwr_spec.np); + return 0; + } + + of_node_put(pwr_spec.np); + + /* If a consumer is already bound, only allow a re-match from it */ + if (ctx->consumer_node) + return ctx->consumer_node =3D=3D dev->of_node; + + ctx->num_clks =3D ARRAY_SIZE(clk_names); + ctx->clks =3D kcalloc(ctx->num_clks, sizeof(*ctx->clks), GFP_KERNEL); + if (!ctx->clks) + return -ENOMEM; + + for (i =3D 0; i < ctx->num_clks; i++) + ctx->clks[i].id =3D clk_names[i]; + + ret =3D clk_bulk_get(dev, ctx->num_clks, ctx->clks); + if (ret) + goto err_free_clks; + + ctx->gpu_reset =3D reset_control_get_shared(dev, NULL); + if (IS_ERR(ctx->gpu_reset)) { + ret =3D PTR_ERR(ctx->gpu_reset); + goto err_put_clks; + } + + ctx->consumer_node =3D of_node_get(dev->of_node); + + return 1; + +err_put_clks: + clk_bulk_put(ctx->num_clks, ctx->clks); +err_free_clks: + kfree(ctx->clks); + ctx->clks =3D NULL; + + return ret; +} + +static int pwrseq_thead_gpu_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct device *dev =3D &adev->dev; + struct device *parent_dev =3D dev->parent; + struct pwrseq_thead_gpu_ctx *ctx; + struct pwrseq_config config =3D {}; + + ctx =3D devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->aon_node =3D parent_dev->of_node; + + ctx->clkgen_reset =3D + devm_reset_control_get_exclusive(parent_dev, "gpu-clkgen"); + if (IS_ERR(ctx->clkgen_reset)) + return dev_err_probe( + dev, PTR_ERR(ctx->clkgen_reset), + "Failed to get GPU clkgen reset from parent\n"); + + config.parent =3D dev; + config.owner =3D THIS_MODULE; + config.drvdata =3D ctx; + config.match =3D pwrseq_thead_gpu_match; + config.targets =3D pwrseq_thead_gpu_targets; + + ctx->pwrseq =3D devm_pwrseq_device_register(dev, &config); + if (IS_ERR(ctx->pwrseq)) + return dev_err_probe(dev, PTR_ERR(ctx->pwrseq), + "Failed to register power sequencer\n"); + + auxiliary_set_drvdata(adev, ctx); + + return 0; +} + +static void pwrseq_thead_gpu_remove(struct auxiliary_device *adev) +{ + struct pwrseq_thead_gpu_ctx *ctx =3D auxiliary_get_drvdata(adev); + + if (ctx->gpu_reset) + reset_control_put(ctx->gpu_reset); + + if (ctx->clks) { + clk_bulk_put(ctx->num_clks, ctx->clks); + kfree(ctx->clks); + } + + if (ctx->consumer_node) + of_node_put(ctx->consumer_node); +} + +static const struct auxiliary_device_id pwrseq_thead_gpu_id_table[] =3D { + { .name =3D "th1520_pm_domains.pwrseq-gpu" }, + {}, +}; +MODULE_DEVICE_TABLE(auxiliary, pwrseq_thead_gpu_id_table); + +static struct auxiliary_driver pwrseq_thead_gpu_driver =3D { + .driver =3D { + .name =3D "pwrseq-thead-gpu", + }, + .probe =3D pwrseq_thead_gpu_probe, + .remove =3D pwrseq_thead_gpu_remove, + .id_table =3D pwrseq_thead_gpu_id_table, +}; +module_auxiliary_driver(pwrseq_thead_gpu_driver); + +MODULE_AUTHOR("Michal Wilczynski "); +MODULE_DESCRIPTION("T-HEAD TH1520 GPU power sequencer driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Wed Oct 8 23:45:33 2025 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A55224468A for ; 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Mon, 23 Jun 2025 11:44:31 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250623114430eusmtip1b8811fa83d3fe7951975aa26c0c678b2~LqVbKVMve2309023090eusmtip19; Mon, 23 Jun 2025 11:44:30 +0000 (GMT) From: Michal Wilczynski Date: Mon, 23 Jun 2025 13:42:40 +0200 Subject: [PATCH v6 2/8] dt-bindings: firmware: thead,th1520: Add resets for GPU clkgen Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20250623-apr_14_for_sending-v6-2-6583ce0f6c25@samsung.com> In-Reply-To: <20250623-apr_14_for_sending-v6-0-6583ce0f6c25@samsung.com> To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org, Bartosz Golaszewski , Krzysztof Kozlowski X-Mailer: b4 0.15-dev X-CMS-MailID: 20250623114431eucas1p23e8afc09574e2c2026b0e05323db821f X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20250623114431eucas1p23e8afc09574e2c2026b0e05323db821f X-EPHeader: CA X-CMS-RootMailID: 20250623114431eucas1p23e8afc09574e2c2026b0e05323db821f References: <20250623-apr_14_for_sending-v6-0-6583ce0f6c25@samsung.com> Extend the TH1520 AON to describe the GPU clkgen reset line, required for proper GPU clock and reset sequencing. The T-HEAD TH1520 GPU requires coordinated management of two clocks (core and sys) and two resets (GPU core reset and GPU clkgen reset). Only the clkgen reset is exposed at the AON level, to support SoC specific initialization handled through a dedicated auxiliary power sequencing driver. The GPU core reset remains described in the GPU device node, as from the GPU driver's perspective, there is only a single reset line [1]. This follows upstream maintainers' recommendations [2] to abstract SoC specific details into the PM domain layer rather than exposing them to drivers directly. Link: https://lore.kernel.org/all/816db99d-7088-4c1a-af03-b9a825ac09dc@imgt= ec.com/ - [1] Link: https://lore.kernel.org/all/38d9650fc11a674c8b689d6bab937acf@kernel.o= rg/ - [2] Reviewed-by: Ulf Hansson Reviewed-by: Drew Fustini Reviewed-by: Bartosz Golaszewski Reviewed-by: Krzysztof Kozlowski Signed-off-by: Michal Wilczynski --- Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml | 7 +++++= ++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/thead,th1520-aon.ya= ml b/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml index bbc183200400de7aadbb21fea21911f6f4227b09..3365124c7fd4736922717bd31ca= a13272f4a4ea6 100644 --- a/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml +++ b/Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml @@ -32,6 +32,13 @@ properties: items: - const: aon =20 + resets: + maxItems: 1 + + reset-names: + items: + - const: gpu-clkgen + "#power-domain-cells": const: 1 =20 --=20 2.34.1 From nobody Wed Oct 8 23:45:33 2025 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6244424677D for ; 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Mon, 23 Jun 2025 11:44:32 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250623114431eusmtip17d8774218f038c94d99c5c902eb2247c~LqVcV2wB-1799017990eusmtip1j; Mon, 23 Jun 2025 11:44:31 +0000 (GMT) From: Michal Wilczynski Date: Mon, 23 Jun 2025 13:42:41 +0200 Subject: [PATCH v6 3/8] pmdomain: thead: Instantiate GPU power sequencer via auxiliary bus Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20250623-apr_14_for_sending-v6-3-6583ce0f6c25@samsung.com> In-Reply-To: <20250623-apr_14_for_sending-v6-0-6583ce0f6c25@samsung.com> To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org, Bartosz Golaszewski X-Mailer: b4 0.15-dev X-CMS-MailID: 20250623114432eucas1p2642e24f2dea577c211f26e2738210c4a X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20250623114432eucas1p2642e24f2dea577c211f26e2738210c4a X-EPHeader: CA X-CMS-RootMailID: 20250623114432eucas1p2642e24f2dea577c211f26e2738210c4a References: <20250623-apr_14_for_sending-v6-0-6583ce0f6c25@samsung.com> In order to support the complex power sequencing required by the TH1520 GPU, the AON power domain driver must be responsible for initiating the corresponding sequencer driver. This functionality is specific to platforms where the GPU power sequencing hardware is controlled by the AON block. Extend the AON power domain driver to check for the presence of the "gpu-clkgen" reset in its own device tree node. If the property is found, create and register a new auxiliary device. This device acts as a proxy that allows the dedicated `pwrseq-thead-gpu` auxiliary driver to bind and take control of the sequencing logic. Reviewed-by: Ulf Hansson Reviewed-by: Bartosz Golaszewski Signed-off-by: Michal Wilczynski --- drivers/pmdomain/thead/Kconfig | 1 + drivers/pmdomain/thead/th1520-pm-domains.c | 51 ++++++++++++++++++++++++++= ++++ 2 files changed, 52 insertions(+) diff --git a/drivers/pmdomain/thead/Kconfig b/drivers/pmdomain/thead/Kconfig index 7d52f8374b074167d508a80fd807929c53faef12..208828e0fa0dc91256bf808b905= bea32bb84250d 100644 --- a/drivers/pmdomain/thead/Kconfig +++ b/drivers/pmdomain/thead/Kconfig @@ -4,6 +4,7 @@ config TH1520_PM_DOMAINS tristate "Support TH1520 Power Domains" depends on TH1520_AON_PROTOCOL select REGMAP_MMIO + select AUXILIARY_BUS help This driver enables power domain management for the T-HEAD TH-1520 SoC. On this SoC there are number of power domains, diff --git a/drivers/pmdomain/thead/th1520-pm-domains.c b/drivers/pmdomain/= thead/th1520-pm-domains.c index f702e20306f469aeb0ed15e54bd4f8309f28018c..9040b698e7f7f2400163841530f= ecacfb0f917bc 100644 --- a/drivers/pmdomain/thead/th1520-pm-domains.c +++ b/drivers/pmdomain/thead/th1520-pm-domains.c @@ -5,6 +5,7 @@ * Author: Michal Wilczynski */ =20 +#include #include #include #include @@ -128,6 +129,50 @@ static void th1520_pd_init_all_off(struct generic_pm_d= omain **domains, } } =20 +static void th1520_pd_pwrseq_unregister_adev(void *adev) +{ + auxiliary_device_delete(adev); + auxiliary_device_uninit(adev); +} + +static int th1520_pd_pwrseq_gpu_init(struct device *dev) +{ + struct auxiliary_device *adev; + int ret; + + /* + * Correctly check only for the property's existence in the DT node. + * We don't need to get/claim the reset here; that is the job of + * the auxiliary driver that we are about to spawn. + */ + if (device_property_match_string(dev, "reset-names", "gpu-clkgen") < 0) + /* + * This is not an error. It simply means the optional sequencer + * is not described in the device tree. + */ + return 0; + + adev =3D devm_kzalloc(dev, sizeof(*adev), GFP_KERNEL); + if (!adev) + return -ENOMEM; + + adev->name =3D "pwrseq-gpu"; + adev->dev.parent =3D dev; + + ret =3D auxiliary_device_init(adev); + if (ret) + return ret; + + ret =3D auxiliary_device_add(adev); + if (ret) { + auxiliary_device_uninit(adev); + return ret; + } + + return devm_add_action_or_reset(dev, th1520_pd_pwrseq_unregister_adev, + adev); +} + static int th1520_pd_probe(struct platform_device *pdev) { struct generic_pm_domain **domains; @@ -186,8 +231,14 @@ static int th1520_pd_probe(struct platform_device *pde= v) if (ret) goto err_clean_genpd; =20 + ret =3D th1520_pd_pwrseq_gpu_init(dev); + if (ret) + goto err_clean_provider; + return 0; =20 +err_clean_provider: + of_genpd_del_provider(dev->of_node); err_clean_genpd: for (i--; i >=3D 0; i--) pm_genpd_remove(domains[i]); --=20 2.34.1 From nobody Wed Oct 8 23:45:33 2025 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3EAB6246BB2 for ; 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Mon, 23 Jun 2025 11:44:33 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250623114432eusmtip17cc43a0ff0d845139e39aa6b61cfe777~LqVdbwSyx1396413964eusmtip1I; Mon, 23 Jun 2025 11:44:32 +0000 (GMT) From: Michal Wilczynski Date: Mon, 23 Jun 2025 13:42:42 +0200 Subject: [PATCH v6 4/8] drm/imagination: Use pwrseq for TH1520 GPU power management Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20250623-apr_14_for_sending-v6-4-6583ce0f6c25@samsung.com> In-Reply-To: <20250623-apr_14_for_sending-v6-0-6583ce0f6c25@samsung.com> To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org, Bartosz Golaszewski X-Mailer: b4 0.15-dev X-CMS-MailID: 20250623114433eucas1p1659c22d6696f3eb51d4169eee80b7cb2 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20250623114433eucas1p1659c22d6696f3eb51d4169eee80b7cb2 X-EPHeader: CA X-CMS-RootMailID: 20250623114433eucas1p1659c22d6696f3eb51d4169eee80b7cb2 References: <20250623-apr_14_for_sending-v6-0-6583ce0f6c25@samsung.com> Update the Imagination PVR DRM driver to leverage the pwrseq framework for managing the power sequence of the GPU on the T-HEAD TH1520 SoC. To cleanly handle the TH1520's specific power requirements in the generic driver, this patch implements the "driver match data" pattern. The pvr_soc_data struct, associated with a compatible string in the of_device_id table, now holds pointers to platform-specific power_on and power_off functions. At probe time, the driver inspects the assigned power_on function pointer. If it points to the pwrseq variant, the driver calls devm_pwrseq_get("gpu-power"), requiring a valid sequencer and deferring probe on failure. Otherwise, it falls back to its standard manual reset initialization. The runtime PM callbacks, pvr_power_device_resume() and pvr_power_device_suspend(), call the power_on and power_off function pointers. Helper functions for both manual and pwrseq-based sequences are introduced to support this. Reviewed-by: Ulf Hansson Reviewed-by: Bartosz Golaszewski Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/imagination/Kconfig | 1 + drivers/gpu/drm/imagination/pvr_device.c | 31 +++++++-- drivers/gpu/drm/imagination/pvr_device.h | 19 ++++++ drivers/gpu/drm/imagination/pvr_drv.c | 30 ++++++++- drivers/gpu/drm/imagination/pvr_power.c | 112 ++++++++++++++++++++-------= ---- drivers/gpu/drm/imagination/pvr_power.h | 6 ++ 6 files changed, 152 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/imagination/Kconfig b/drivers/gpu/drm/imaginat= ion/Kconfig index 3bfa2ac212dccb73c53bdc2bc259bcba636e7cfc..5f9fff43d6baadc42ebf48d9172= 9bfbf27e06caa 100644 --- a/drivers/gpu/drm/imagination/Kconfig +++ b/drivers/gpu/drm/imagination/Kconfig @@ -11,6 +11,7 @@ config DRM_POWERVR select DRM_SCHED select DRM_GPUVM select FW_LOADER + select POWER_SEQUENCING help Choose this option if you have a system that has an Imagination Technologies PowerVR (Series 6 or later) or IMG GPU. diff --git a/drivers/gpu/drm/imagination/pvr_device.c b/drivers/gpu/drm/ima= gination/pvr_device.c index 8b9ba4983c4cb5bc40342fcafc4259078bc70547..c1c24c441c821ccce59f7cd3f14= 544a91ef54ea9 100644 --- a/drivers/gpu/drm/imagination/pvr_device.c +++ b/drivers/gpu/drm/imagination/pvr_device.c @@ -23,8 +23,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -618,6 +620,9 @@ pvr_device_init(struct pvr_device *pvr_dev) struct device *dev =3D drm_dev->dev; int err; =20 + /* Get the platform-specific data based on the compatible string. */ + pvr_dev->soc_data =3D of_device_get_match_data(dev); + /* * Setup device parameters. We do this first in case other steps * depend on them. @@ -631,10 +636,28 @@ pvr_device_init(struct pvr_device *pvr_dev) if (err) return err; =20 - /* Get the reset line for the GPU */ - err =3D pvr_device_reset_init(pvr_dev); - if (err) - return err; + /* + * For platforms that require it, get the power sequencer. + * For all others, perform manual reset initialization. + */ + if (pvr_dev->soc_data->power_on =3D=3D pvr_power_on_sequence_pwrseq) { + pvr_dev->pwrseq =3D devm_pwrseq_get(dev, "gpu-power"); + if (IS_ERR(pvr_dev->pwrseq)) { + /* + * This platform requires a sequencer. If we can't get + * it, we must return the error (including -EPROBE_DEFER + * to wait for the provider to appear) + */ + return dev_err_probe( + dev, PTR_ERR(pvr_dev->pwrseq), + "Failed to get required power sequencer\n"); + } + } else { + /* This platform does not use a sequencer, init reset manually. */ + err =3D pvr_device_reset_init(pvr_dev); + if (err) + return err; + } =20 /* Explicitly power the GPU so we can access control registers before the= FW is booted. */ err =3D pm_runtime_resume_and_get(dev); diff --git a/drivers/gpu/drm/imagination/pvr_device.h b/drivers/gpu/drm/ima= gination/pvr_device.h index 7cb01c38d2a9c3fc71effe789d4dfe54eddd93ee..3f35025e84efac031d3261c849e= f9fe105466423 100644 --- a/drivers/gpu/drm/imagination/pvr_device.h +++ b/drivers/gpu/drm/imagination/pvr_device.h @@ -37,6 +37,9 @@ struct clk; /* Forward declaration from . */ struct firmware; =20 +/* Forward declaration from #include #include +#include #include #include #include @@ -234,6 +235,71 @@ pvr_watchdog_init(struct pvr_device *pvr_dev) return 0; } =20 +int pvr_power_on_sequence_pwrseq(struct pvr_device *pvr_dev) +{ + return pwrseq_power_on(pvr_dev->pwrseq); +} + +int pvr_power_off_sequence_pwrseq(struct pvr_device *pvr_dev) +{ + return pwrseq_power_off(pvr_dev->pwrseq); +} + +int pvr_power_on_sequence_manual(struct pvr_device *pvr_dev) +{ + int err; + + err =3D clk_prepare_enable(pvr_dev->core_clk); + if (err) + return err; + + err =3D clk_prepare_enable(pvr_dev->sys_clk); + if (err) + goto err_core_clk_disable; + + err =3D clk_prepare_enable(pvr_dev->mem_clk); + if (err) + goto err_sys_clk_disable; + + /* + * According to the hardware manual, a delay of at least 32 clock + * cycles is required between de-asserting the clkgen reset and + * de-asserting the GPU reset. Assuming a worst-case scenario with + * a very high GPU clock frequency, a delay of 1 microsecond is + * sufficient to ensure this requirement is met across all + * feasible GPU clock speeds. + */ + udelay(1); + + err =3D reset_control_deassert(pvr_dev->reset); + if (err) + goto err_mem_clk_disable; + + return 0; + +err_mem_clk_disable: + clk_disable_unprepare(pvr_dev->mem_clk); +err_sys_clk_disable: + clk_disable_unprepare(pvr_dev->sys_clk); +err_core_clk_disable: + clk_disable_unprepare(pvr_dev->core_clk); + + return err; +} + +int pvr_power_off_sequence_manual(struct pvr_device *pvr_dev) +{ + int err; + + err =3D reset_control_assert(pvr_dev->reset); + + clk_disable_unprepare(pvr_dev->mem_clk); + clk_disable_unprepare(pvr_dev->sys_clk); + clk_disable_unprepare(pvr_dev->core_clk); + + return err; +} + int pvr_power_device_suspend(struct device *dev) { @@ -252,11 +318,7 @@ pvr_power_device_suspend(struct device *dev) goto err_drm_dev_exit; } =20 - clk_disable_unprepare(pvr_dev->mem_clk); - clk_disable_unprepare(pvr_dev->sys_clk); - clk_disable_unprepare(pvr_dev->core_clk); - - err =3D reset_control_assert(pvr_dev->reset); + err =3D pvr_dev->soc_data->power_off(pvr_dev); =20 err_drm_dev_exit: drm_dev_exit(idx); @@ -276,54 +338,22 @@ pvr_power_device_resume(struct device *dev) if (!drm_dev_enter(drm_dev, &idx)) return -EIO; =20 - err =3D clk_prepare_enable(pvr_dev->core_clk); + err =3D pvr_dev->soc_data->power_on(pvr_dev); if (err) goto err_drm_dev_exit; =20 - err =3D clk_prepare_enable(pvr_dev->sys_clk); - if (err) - goto err_core_clk_disable; - - err =3D clk_prepare_enable(pvr_dev->mem_clk); - if (err) - goto err_sys_clk_disable; - - /* - * According to the hardware manual, a delay of at least 32 clock - * cycles is required between de-asserting the clkgen reset and - * de-asserting the GPU reset. Assuming a worst-case scenario with - * a very high GPU clock frequency, a delay of 1 microsecond is - * sufficient to ensure this requirement is met across all - * feasible GPU clock speeds. - */ - udelay(1); - - err =3D reset_control_deassert(pvr_dev->reset); - if (err) - goto err_mem_clk_disable; - if (pvr_dev->fw_dev.booted) { err =3D pvr_power_fw_enable(pvr_dev); if (err) - goto err_reset_assert; + goto err_power_off; } =20 drm_dev_exit(idx); =20 return 0; =20 -err_reset_assert: - reset_control_assert(pvr_dev->reset); - -err_mem_clk_disable: - clk_disable_unprepare(pvr_dev->mem_clk); - -err_sys_clk_disable: - clk_disable_unprepare(pvr_dev->sys_clk); - -err_core_clk_disable: - clk_disable_unprepare(pvr_dev->core_clk); - +err_power_off: + pvr_dev->soc_data->power_off(pvr_dev); err_drm_dev_exit: drm_dev_exit(idx); =20 diff --git a/drivers/gpu/drm/imagination/pvr_power.h b/drivers/gpu/drm/imag= ination/pvr_power.h index ada85674a7ca762dcf92df40424230e1c3910342..d91d5f3f39b61f81121357f4187= b1a6e09b3dec0 100644 --- a/drivers/gpu/drm/imagination/pvr_power.h +++ b/drivers/gpu/drm/imagination/pvr_power.h @@ -41,4 +41,10 @@ pvr_power_put(struct pvr_device *pvr_dev) int pvr_power_domains_init(struct pvr_device *pvr_dev); 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Mon, 23 Jun 2025 11:44:34 +0000 (GMT) From: Michal Wilczynski Date: Mon, 23 Jun 2025 13:42:43 +0200 Subject: [PATCH v6 5/8] dt-bindings: gpu: img,powervr-rogue: Add TH1520 GPU compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20250623-apr_14_for_sending-v6-5-6583ce0f6c25@samsung.com> In-Reply-To: <20250623-apr_14_for_sending-v6-0-6583ce0f6c25@samsung.com> To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org, Krzysztof Kozlowski , Bartosz Golaszewski X-Mailer: b4 0.15-dev X-CMS-MailID: 20250623114436eucas1p1ab8455b32937a472f5f656086e38f428 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20250623114436eucas1p1ab8455b32937a472f5f656086e38f428 X-EPHeader: CA X-CMS-RootMailID: 20250623114436eucas1p1ab8455b32937a472f5f656086e38f428 References: <20250623-apr_14_for_sending-v6-0-6583ce0f6c25@samsung.com> Update the img,powervr-rogue.yaml to include the T-HEAD TH1520 SoC's specific GPU compatible string. The thead,th1520-gpu compatible, along with its full chain img,img-bxm-4-64, and img,img-rogue, is added to the list of recognized GPU types. The power-domains property requirement for img,img-bxm-4-64 is also ensured by adding it to the relevant allOf condition. Acked-by: Krzysztof Kozlowski Reviewed-by: Ulf Hansson Reviewed-by: Bartosz Golaszewski Signed-off-by: Michal Wilczynski --- Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b= /Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index 4450e2e73b3ccf74d29f0e31e2e6687d7cbe5d65..9b241a0c1f5941dc58a1e23970f= 6d3773d427c22 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -21,6 +21,11 @@ properties: # work with newer dts. - const: img,img-axe - const: img,img-rogue + - items: + - enum: + - thead,th1520-gpu + - const: img,img-bxm-4-64 + - const: img,img-rogue - items: - enum: - ti,j721s2-gpu @@ -93,7 +98,9 @@ allOf: properties: compatible: contains: - const: img,img-axe-1-16m + enum: + - img,img-axe-1-16m + - img,img-bxm-4-64 then: properties: power-domains: --=20 2.34.1 From nobody Wed Oct 8 23:45:33 2025 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 89997248861 for ; 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Mon, 23 Jun 2025 11:44:37 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250623114436eusmtip1881294de4a8782598c48caa73711624f~LqVgtjFwi2309023090eusmtip1-; Mon, 23 Jun 2025 11:44:36 +0000 (GMT) From: Michal Wilczynski Date: Mon, 23 Jun 2025 13:42:44 +0200 Subject: [PATCH v6 6/8] riscv: dts: thead: th1520: Add GPU clkgen reset to AON node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20250623-apr_14_for_sending-v6-6-6583ce0f6c25@samsung.com> In-Reply-To: <20250623-apr_14_for_sending-v6-0-6583ce0f6c25@samsung.com> To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org, Bartosz Golaszewski X-Mailer: b4 0.15-dev X-CMS-MailID: 20250623114437eucas1p153a063e2f6e34f349c5e5b12a5a32707 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20250623114437eucas1p153a063e2f6e34f349c5e5b12a5a32707 X-EPHeader: CA X-CMS-RootMailID: 20250623114437eucas1p153a063e2f6e34f349c5e5b12a5a32707 References: <20250623-apr_14_for_sending-v6-0-6583ce0f6c25@samsung.com> Add the "gpu-clkgen" reset property to the AON device tree node. This allows the AON power domain driver to detect the capability to power sequence the GPU and spawn the necessary pwrseq-thead-gpu auxiliary driver for managing the GPU's complex power sequence. This commit also adds the prerequisite dt-bindings/reset/thead,th1520-reset.h include to make the TH1520_RESET_ID_GPU_CLKGEN available. This include was previously dropped during a conflict resolution [1]. Link: https://lore.kernel.org/all/aAvfn2mq0Ksi8DF2@x1/ [1] Reviewed-by: Ulf Hansson Reviewed-by: Bartosz Golaszewski Reviewed-by: Drew Fustini Signed-off-by: Michal Wilczynski --- arch/riscv/boot/dts/thead/th1520.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index 1db0054c4e093400e9dbebcee5fcfa5b5cae6e32..f3f5db0201ab8c0306d4d63072a= 1573431e51893 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include =20 / { compatible =3D "thead,th1520"; @@ -234,6 +235,8 @@ aon: aon { compatible =3D "thead,th1520-aon"; mboxes =3D <&mbox_910t 1>; mbox-names =3D "aon"; + resets =3D <&rst TH1520_RESET_ID_GPU_CLKGEN>; + reset-names =3D "gpu-clkgen"; #power-domain-cells =3D <1>; }; =20 --=20 2.34.1 From nobody Wed Oct 8 23:45:33 2025 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBD44248F58 for ; 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Mon, 23 Jun 2025 11:44:38 +0000 (GMT) Received: from AMDC4942.eu.corp.samsungelectronics.net (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250623114437eusmtip11c14bfa1a673d341b8bcddad4c7aa9ec~LqVhycMO81631916319eusmtip1O; Mon, 23 Jun 2025 11:44:37 +0000 (GMT) From: Michal Wilczynski Date: Mon, 23 Jun 2025 13:42:45 +0200 Subject: [PATCH v6 7/8] riscv: dts: thead: th1520: Add IMG BXM-4-64 GPU node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20250623-apr_14_for_sending-v6-7-6583ce0f6c25@samsung.com> In-Reply-To: <20250623-apr_14_for_sending-v6-0-6583ce0f6c25@samsung.com> To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org, Bartosz Golaszewski X-Mailer: b4 0.15-dev X-CMS-MailID: 20250623114438eucas1p2fbb66bfe21ec19a0459eccc8cfe47849 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20250623114438eucas1p2fbb66bfe21ec19a0459eccc8cfe47849 X-EPHeader: CA X-CMS-RootMailID: 20250623114438eucas1p2fbb66bfe21ec19a0459eccc8cfe47849 References: <20250623-apr_14_for_sending-v6-0-6583ce0f6c25@samsung.com> Add a device tree node for the IMG BXM-4-64 GPU present in the T-HEAD TH1520 SoC used by the Lichee Pi 4A board. This node enables support for the GPU using the drm/imagination driver. By adding this node, the kernel can recognize and initialize the GPU, providing graphics acceleration capabilities on the Lichee Pi 4A and other boards based on the TH1520 SoC. Add fixed clock gpu_mem_clk, as the MEM clock on the T-HEAD SoC can't be controlled programatically. Reviewed-by: Ulf Hansson Reviewed-by: Drew Fustini Reviewed-by: Bartosz Golaszewski Signed-off-by: Michal Wilczynski --- arch/riscv/boot/dts/thead/th1520.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index f3f5db0201ab8c0306d4d63072a1573431e51893..c8447eef36c3a6e92d768658b6b= 19dfeb59a47c4 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -225,6 +225,13 @@ aonsys_clk: clock-73728000 { #clock-cells =3D <0>; }; =20 + gpu_mem_clk: mem-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <0>; + clock-output-names =3D "gpu_mem_clk"; + #clock-cells =3D <0>; + }; + stmmac_axi_config: stmmac-axi-config { snps,wr_osr_lmt =3D <15>; snps,rd_osr_lmt =3D <15>; @@ -500,6 +507,21 @@ clk: clock-controller@ffef010000 { #clock-cells =3D <1>; }; =20 + gpu: gpu@ffef400000 { + compatible =3D "thead,th1520-gpu", "img,img-bxm-4-64", + "img,img-rogue"; + reg =3D <0xff 0xef400000 0x0 0x100000>; + interrupt-parent =3D <&plic>; + interrupts =3D <102 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&clk_vo CLK_GPU_CORE>, + <&gpu_mem_clk>, + <&clk_vo CLK_GPU_CFG_ACLK>; + clock-names =3D "core", "mem", "sys"; + power-domains =3D <&aon TH1520_GPU_PD>; + power-domain-names =3D "a"; + resets =3D <&rst TH1520_RESET_ID_GPU>; + }; + rst: reset-controller@ffef528000 { compatible =3D "thead,th1520-reset"; reg =3D <0xff 0xef528000 0x0 0x4f>; --=20 2.34.1 From nobody Wed Oct 8 23:45:33 2025 Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com [210.118.77.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9BAF24A054 for ; Mon, 23 Jun 2025 11:44:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750679083; cv=none; b=giOpNkoDaUA5zgMfayQmEK/qgJoKgFO6ZcbW+n/hdAw7OIEKgqEaZTWyIcBe8nkfF/rDOgdjPCmrVCE7SRQvGjFomhO7PQfdWp8THeuC/pn3eOLmoBoCBH8PVVRW8AIdVVaA1IDSz4yoPlA7BLttHRW9W7YprjemXHzPD96fBUU= ARC-Message-Signature: i=1; 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Mon, 23 Jun 2025 11:44:38 +0000 (GMT) From: Michal Wilczynski Date: Mon, 23 Jun 2025 13:42:46 +0200 Subject: [PATCH v6 8/8] drm/imagination: Enable PowerVR driver for RISC-V Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Message-Id: <20250623-apr_14_for_sending-v6-8-6583ce0f6c25@samsung.com> In-Reply-To: <20250623-apr_14_for_sending-v6-0-6583ce0f6c25@samsung.com> To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Wilczynski , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org, Bartosz Golaszewski X-Mailer: b4 0.15-dev X-CMS-MailID: 20250623114439eucas1p17e4405b95a5693a972bf40a3b3ecdc11 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20250623114439eucas1p17e4405b95a5693a972bf40a3b3ecdc11 X-EPHeader: CA X-CMS-RootMailID: 20250623114439eucas1p17e4405b95a5693a972bf40a3b3ecdc11 References: <20250623-apr_14_for_sending-v6-0-6583ce0f6c25@samsung.com> Several RISC-V boards feature Imagination GPUs that are compatible with the PowerVR driver. An example is the IMG BXM-4-64 GPU on the Lichee Pi 4A board. This commit adjusts the driver's Kconfig dependencies to allow the PowerVR driver to be compiled on the RISC-V architecture. By enabling compilation on RISC-V, we expand support for these GPUs, providing graphics acceleration capabilities and enhancing hardware compatibility on RISC-V platforms. Add a dependency on MMU to fix a build warning on RISC-V configurations without an MMU. Reviewed-by: Ulf Hansson Reviewed-by: Bartosz Golaszewski Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/imagination/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/imagination/Kconfig b/drivers/gpu/drm/imaginat= ion/Kconfig index 5f9fff43d6baadc42ebf48d91729bfbf27e06caa..a7da858a5b301e8f088e3e22f56= 41feb2e078681 100644 --- a/drivers/gpu/drm/imagination/Kconfig +++ b/drivers/gpu/drm/imagination/Kconfig @@ -3,9 +3,10 @@ =20 config DRM_POWERVR tristate "Imagination Technologies PowerVR (Series 6 and later) & IMG Gra= phics" - depends on ARM64 + depends on (ARM64 || RISCV) depends on DRM depends on PM + depends on MMU select DRM_EXEC select DRM_GEM_SHMEM_HELPER select DRM_SCHED --=20 2.34.1