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Mon, 23 Jun 2025 09:37:48 -0700 (PDT) From: Jerome Brunet Date: Mon, 23 Jun 2025 18:37:39 +0200 Subject: [PATCH v4 3/3] clk: amlogic: s4: remove unused data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250623-amlogic-clk-drop-clk-regmap-tables-v4-3-ff04918211cc@baylibre.com> References: <20250623-amlogic-clk-drop-clk-regmap-tables-v4-0-ff04918211cc@baylibre.com> In-Reply-To: <20250623-amlogic-clk-drop-clk-regmap-tables-v4-0-ff04918211cc@baylibre.com> To: Michael Turquette , Stephen Boyd , Neil Armstrong , Kevin Hilman , Martin Blumenstingl Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Jerome Brunet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3973; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=lY/+jeINkrBTULMr0fgrgjWAsXe5te4CfoeDV9q3UOI=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBoWYLYO0zm2Ij1fDff8rSEVAszTwR1HrjavXeaU 0Uem7bF9VeJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaFmC2AAKCRDm/A8cN/La hc/CD/4m/uWRim24OFAgeUrpZSDUlhz+owSrV5ms30HqiIr49Tu/MkLik1fNxtOZoP7F3o7Vd9w I1ljZ786kW8PqUn9WvzghDsgbY2H1rmf7myPVPgO5cMxtzP8JXFozngMvwPnlm7xoZ1+6P0Bkdc PN47s/Ji69FMhx2JWbZVT/+0qfmpBKAlGn5Sbh2OOKCtkMazBWQRAU3jfjqLGpVpiQbwqVd8jPV gNF3JSxbQwnX8ghEC1HWQI4h/sq3w0UeLo68K3qGcJTLE3MSQARLwLdmn9VYdQqkKiGzGDrPRn+ J3xBs9BrRzWyanNumrpOXqPnZADZHYudv5rkwY4gvuFWpMyO9KlcLiOvihX7nmgDrruDdaK7hkR bbQ1br1vNnTrPZK4A62Jkxj/z8v7A3KjL89I7RuBdBlVTZi1UfM511q5UtYXSPQMvYW/VNJWqUK MiueAteGQhWVE7a2BSwOKqlhQoH55D5JXdSS/xmcdYkTAj/g5Z455Z9oY00R4VzDcCxyeoiwEEM uJHCFa6zgqTUKmuka6A3+RdRpVg7HHo+qG6u1n/AYvNT6eAFgqyPxWbG3RbuRV72dJcNpca+mJ1 4iNSzWhQuYvDOhufnvDkni/Yn/JiALR2mA9mC75E8Fu6x/LCJyq3tFDOwfQsOD6kH/RQUTM2bos H0LyBCHLEn47Unw== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Following the removal of the clk_regmap clock table from the s4-peripherals clock controller driver, it appears some clocks are unused, which means these are not exported or even registered. In all likelihood, these clocks have not been tested. Remove the unused clocks for now. These can added back later when they have been properly tested. Signed-off-by: Jerome Brunet --- drivers/clk/meson/s4-peripherals.c | 112 ---------------------------------= ---- 1 file changed, 112 deletions(-) diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peri= pherals.c index fd2d4d725f9e2595a865909db3c0c598309ef448..c9400cf54c84c3dc7c63d063693= 3951b0cac230c 100644 --- a/drivers/clk/meson/s4-peripherals.c +++ b/drivers/clk/meson/s4-peripherals.c @@ -3174,118 +3174,6 @@ static struct clk_regmap s4_gen_clk =3D { }, }; =20 -static const struct clk_parent_data s4_adc_extclk_in_parent_data[] =3D { - { .fw_name =3D "xtal", }, - { .fw_name =3D "fclk_div4", }, - { .fw_name =3D "fclk_div3", }, - { .fw_name =3D "fclk_div5", }, - { .fw_name =3D "fclk_div7", }, - { .fw_name =3D "mpll2", }, - { .fw_name =3D "gp0_pll", }, - { .fw_name =3D "hifi_pll", }, -}; - -static struct clk_regmap s4_adc_extclk_in_mux =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_DEMOD_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 25, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "adc_extclk_in_mux", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_adc_extclk_in_parent_data, - .num_parents =3D ARRAY_SIZE(s4_adc_extclk_in_parent_data), - .flags =3D 0, - }, -}; - -static struct clk_regmap s4_adc_extclk_in_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_DEMOD_CLK_CTRL, - .shift =3D 16, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "adc_extclk_in_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_adc_extclk_in_mux.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_adc_extclk_in_gate =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_DEMOD_CLK_CTRL, - .bit_idx =3D 24, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "adc_extclk_in", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_adc_extclk_in_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_demod_core_clk_mux =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_DEMOD_CLK_CTRL, - .mask =3D 0x3, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "demod_core_clk_mux", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D (const struct clk_parent_data []) { - { .fw_name =3D "xtal", }, - { .fw_name =3D "fclk_div7", }, - { .fw_name =3D "fclk_div4", }, - { .hw =3D &s4_adc_extclk_in_gate.hw } - }, - .num_parents =3D 4, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_demod_core_clk_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_DEMOD_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "demod_core_clk_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_demod_core_clk_mux.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_demod_core_clk_gate =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_DEMOD_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "demod_core_clk", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_demod_core_clk_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - #define MESON_GATE(_name, _reg, _bit) \ MESON_PCLK(_name, _reg, _bit, &s4_sys_clk.hw) =20 --=20 2.47.2