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Mon, 23 Jun 2025 09:37:46 -0700 (PDT) From: Jerome Brunet Date: Mon, 23 Jun 2025 18:37:37 +0200 Subject: [PATCH v4 1/3] clk: amlogic: get regmap with clk_regmap_init Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250623-amlogic-clk-drop-clk-regmap-tables-v4-1-ff04918211cc@baylibre.com> References: <20250623-amlogic-clk-drop-clk-regmap-tables-v4-0-ff04918211cc@baylibre.com> In-Reply-To: <20250623-amlogic-clk-drop-clk-regmap-tables-v4-0-ff04918211cc@baylibre.com> To: Michael Turquette , Stephen Boyd , Neil Armstrong , Kevin Hilman , Martin Blumenstingl Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Jerome Brunet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=12558; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=haY78uNrJ4Ey96lQHgkTqTLRLQNigrpN7McUZ9yvUI8=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBoWYLWTStrX8Vq0C/y4WEwnMx+xzJ5bfzACITN4 BpgCtCZtEyJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaFmC1gAKCRDm/A8cN/La hTlQD/9zJ+YCaovCXEkERY3jqQOHRcOj8CZlJLBlVLIMWBuSEZohaMnVLPoZO/6z+2YfLIaIMGd +Slj2ZL3/PSgkq5dUXXBmEkFpFG4FP1/XvYK+CE2TrYI7nQbQRPND/SIbI+zCEr/1JxxGkglv6L S5wXeLXASQdpxjV/09qhNtiEhwEZQdfdzzpGcMCCecaoQNYFapZpvOlmHzTltU2RcmPxatiAuCB 4mSVE4wXTI0B3O1OkxIqt/1NOjvaPPtV1QT1zL8O3Lu58EMNmdtV1D0wlkt7sxPCl0T/fTf+5Am iGiVSXm3LgRtlOR01wIbpiG+Xz0D18nAffHOEFB/DJ7buW4CUvzmVstx5cGPa6Y3bpgG1M4kv3i xl7RyF/M/w0j/PY57U5TLBaESDb7pd/aSZwpb0wxEFSrZjYYxQ3RtYZnaCLym6CpQu8T0h09ljv efHN7BczdaHu4JdnZrCCOZHlYPXImTtaiOqcKzhJKH9mEYAc8EOqSLpO/wmptMEkLetONiIZcW2 74W6m6/dPSNoX0SpLE/TA0b7BRxPx2F372y54B+s6y1Vx5kpwinZx5XLNuzY1+IN/FYCGNuLtPK Cf+HyrKUDt4Zt1evjChZobTrXcZ6w6DsLdroTSpTtT8NxVk2S6nvSB251E311mQN0ocd1SHUNhT jJmsJleg1esgoRg== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Add clk_regmap_init() and use it with all clock types which derive from clk_regmap. This helps initialise clk_regmap clocks without requiring tables to keep track of the clock using this type. The way it is done couples clk_regmap with the controllers, which is not ideal. This is a temporary solution to get rid of the tables. The situation will eventually be improved. Signed-off-by: Jerome Brunet --- drivers/clk/meson/Kconfig | 1 + drivers/clk/meson/clk-cpu-dyndiv.c | 1 + drivers/clk/meson/clk-dualdiv.c | 2 ++ drivers/clk/meson/clk-mpll.c | 6 +++++ drivers/clk/meson/clk-phase.c | 11 +++++++++ drivers/clk/meson/clk-pll.c | 7 ++++++ drivers/clk/meson/clk-regmap.c | 49 ++++++++++++++++++++++++++++++++++= ++++ drivers/clk/meson/clk-regmap.h | 4 ++++ drivers/clk/meson/sclk-div.c | 5 ++++ drivers/clk/meson/vclk.c | 2 ++ drivers/clk/meson/vid-pll-div.c | 1 + 11 files changed, 89 insertions(+) diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 5c669b2e2f268c7608c8d9c64bba3c5b54da39b2..7197d23543b8bb8a9020cde3161= 70b50bc359a6c 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -5,6 +5,7 @@ menu "Clock support for Amlogic platforms" config COMMON_CLK_MESON_REGMAP tristate select REGMAP + select MFD_SYSCON =20 config COMMON_CLK_MESON_DUALDIV tristate diff --git a/drivers/clk/meson/clk-cpu-dyndiv.c b/drivers/clk/meson/clk-cpu= -dyndiv.c index cb043b52b65d8a6ae0933935f07fb14c40855700..83aedbfd2891d1099d4fb5e25d2= 306a8328f29db 100644 --- a/drivers/clk/meson/clk-cpu-dyndiv.c +++ b/drivers/clk/meson/clk-cpu-dyndiv.c @@ -61,6 +61,7 @@ static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *h= w, unsigned long rate, }; =20 const struct clk_ops meson_clk_cpu_dyndiv_ops =3D { + .init =3D clk_regmap_init, .recalc_rate =3D meson_clk_cpu_dyndiv_recalc_rate, .determine_rate =3D meson_clk_cpu_dyndiv_determine_rate, .set_rate =3D meson_clk_cpu_dyndiv_set_rate, diff --git a/drivers/clk/meson/clk-dualdiv.c b/drivers/clk/meson/clk-dualdi= v.c index c896cf29b318ca3debf7447a9c44be01523abe47..787df6cdf841641982f20eed7dd= 276669e7b7b6e 100644 --- a/drivers/clk/meson/clk-dualdiv.c +++ b/drivers/clk/meson/clk-dualdiv.c @@ -126,6 +126,7 @@ static int meson_clk_dualdiv_set_rate(struct clk_hw *hw= , unsigned long rate, } =20 const struct clk_ops meson_clk_dualdiv_ops =3D { + .init =3D clk_regmap_init, .recalc_rate =3D meson_clk_dualdiv_recalc_rate, .determine_rate =3D meson_clk_dualdiv_determine_rate, .set_rate =3D meson_clk_dualdiv_set_rate, @@ -133,6 +134,7 @@ const struct clk_ops meson_clk_dualdiv_ops =3D { EXPORT_SYMBOL_NS_GPL(meson_clk_dualdiv_ops, "CLK_MESON"); =20 const struct clk_ops meson_clk_dualdiv_ro_ops =3D { + .init =3D clk_regmap_init, .recalc_rate =3D meson_clk_dualdiv_recalc_rate, }; EXPORT_SYMBOL_NS_GPL(meson_clk_dualdiv_ro_ops, "CLK_MESON"); diff --git a/drivers/clk/meson/clk-mpll.c b/drivers/clk/meson/clk-mpll.c index ee91e32b4050bf40cf6f19c8152ae11c2ab4ec11..7f8dada66e16fd33cb5d0e62857= 7c39fba5e4e25 100644 --- a/drivers/clk/meson/clk-mpll.c +++ b/drivers/clk/meson/clk-mpll.c @@ -128,6 +128,11 @@ static int mpll_init(struct clk_hw *hw) { struct clk_regmap *clk =3D to_clk_regmap(hw); struct meson_clk_mpll_data *mpll =3D meson_clk_mpll_data(clk); + int ret; + + ret =3D clk_regmap_init(hw); + if (ret) + return ret; =20 if (mpll->init_count) regmap_multi_reg_write(clk->map, mpll->init_regs, @@ -151,6 +156,7 @@ static int mpll_init(struct clk_hw *hw) } =20 const struct clk_ops meson_clk_mpll_ro_ops =3D { + .init =3D clk_regmap_init, .recalc_rate =3D mpll_recalc_rate, .determine_rate =3D mpll_determine_rate, }; diff --git a/drivers/clk/meson/clk-phase.c b/drivers/clk/meson/clk-phase.c index 7012111206107a25ca77a5c51cb5b19d9755f3c1..58dd982e6878afd481cdf6634f7= 0a69d5d2b5e5b 100644 --- a/drivers/clk/meson/clk-phase.c +++ b/drivers/clk/meson/clk-phase.c @@ -58,6 +58,7 @@ static int meson_clk_phase_set_phase(struct clk_hw *hw, i= nt degrees) } =20 const struct clk_ops meson_clk_phase_ops =3D { + .init =3D clk_regmap_init, .get_phase =3D meson_clk_phase_get_phase, .set_phase =3D meson_clk_phase_set_phase, }; @@ -83,6 +84,11 @@ static int meson_clk_triphase_sync(struct clk_hw *hw) struct clk_regmap *clk =3D to_clk_regmap(hw); struct meson_clk_triphase_data *tph =3D meson_clk_triphase_data(clk); unsigned int val; + int ret; + + ret =3D clk_regmap_init(hw); + if (ret) + return ret; =20 /* Get phase 0 and sync it to phase 1 and 2 */ val =3D meson_parm_read(clk->map, &tph->ph0); @@ -142,6 +148,11 @@ static int meson_sclk_ws_inv_sync(struct clk_hw *hw) struct clk_regmap *clk =3D to_clk_regmap(hw); struct meson_sclk_ws_inv_data *tph =3D meson_sclk_ws_inv_data(clk); unsigned int val; + int ret; + + ret =3D clk_regmap_init(hw); + if (ret) + return ret; =20 /* Get phase and sync the inverted value to ws */ val =3D meson_parm_read(clk->map, &tph->ph); diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index e8e53855b00a81bc8eaa4213173948c964debc8a..1ea6579a760f35fd669b5e7260d= f8edfa083bf29 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -311,6 +311,11 @@ static int meson_clk_pll_init(struct clk_hw *hw) { struct clk_regmap *clk =3D to_clk_regmap(hw); struct meson_clk_pll_data *pll =3D meson_clk_pll_data(clk); + int ret; + + ret =3D clk_regmap_init(hw); + if (ret) + return ret; =20 /* * Keep the clock running, which was already initialized and enabled @@ -468,6 +473,7 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, un= signed long rate, * the other ops except set_rate since the rate is fixed. */ const struct clk_ops meson_clk_pcie_pll_ops =3D { + .init =3D clk_regmap_init, .recalc_rate =3D meson_clk_pll_recalc_rate, .determine_rate =3D meson_clk_pll_determine_rate, .is_enabled =3D meson_clk_pll_is_enabled, @@ -488,6 +494,7 @@ const struct clk_ops meson_clk_pll_ops =3D { EXPORT_SYMBOL_NS_GPL(meson_clk_pll_ops, "CLK_MESON"); =20 const struct clk_ops meson_clk_pll_ro_ops =3D { + .init =3D clk_regmap_init, .recalc_rate =3D meson_clk_pll_recalc_rate, .is_enabled =3D meson_clk_pll_is_enabled, }; diff --git a/drivers/clk/meson/clk-regmap.c b/drivers/clk/meson/clk-regmap.c index f3e504f6757152868e60d5a9fac5c5e5bf3e2e56..1ed56fe63caedc16a332b28f211= d8b0a7663aaa5 100644 --- a/drivers/clk/meson/clk-regmap.c +++ b/drivers/clk/meson/clk-regmap.c @@ -4,9 +4,52 @@ * Author: Jerome Brunet */ =20 +#include #include +#include #include "clk-regmap.h" =20 +int clk_regmap_init(struct clk_hw *hw) +{ + struct clk_regmap *clk =3D to_clk_regmap(hw); + struct device_node *np, *parent_np; + struct device *dev; + + /* Allow regmap to be preset as it was historically done */ + if (clk->map) + return 0; + + /* + * FIXME: what follows couples the controller implementation + * and clk_regmap clock type. This situation is not desirable + * but temporary, until the controller is able to register + * a hook to initialize a clock type + */ + + /* Check the usual dev enabled controller with an basic IO regmap */ + dev =3D clk_hw_get_dev(hw); + if (dev) { + clk->map =3D dev_get_regmap(dev, NULL); + if (clk->map) + return 0; + } + + /* Move on to early and syscon based controllers */ + np =3D clk_hw_get_of_node(hw); + if (np) { + parent_np =3D of_get_parent(np); + clk->map =3D syscon_node_to_regmap(parent_np); + of_node_put(parent_np); + + if (!IS_ERR_OR_NULL(clk->map)) + return 0; + } + + /* Bail out if regmap can't be found */ + return -EINVAL; +} +EXPORT_SYMBOL_NS_GPL(clk_regmap_init, "CLK_MESON"); + static int clk_regmap_gate_endisable(struct clk_hw *hw, int enable) { struct clk_regmap *clk =3D to_clk_regmap(hw); @@ -45,6 +88,7 @@ static int clk_regmap_gate_is_enabled(struct clk_hw *hw) } =20 const struct clk_ops clk_regmap_gate_ops =3D { + .init =3D clk_regmap_init, .enable =3D clk_regmap_gate_enable, .disable =3D clk_regmap_gate_disable, .is_enabled =3D clk_regmap_gate_is_enabled, @@ -52,6 +96,7 @@ const struct clk_ops clk_regmap_gate_ops =3D { EXPORT_SYMBOL_NS_GPL(clk_regmap_gate_ops, "CLK_MESON"); =20 const struct clk_ops clk_regmap_gate_ro_ops =3D { + .init =3D clk_regmap_init, .is_enabled =3D clk_regmap_gate_is_enabled, }; EXPORT_SYMBOL_NS_GPL(clk_regmap_gate_ro_ops, "CLK_MESON"); @@ -121,6 +166,7 @@ static int clk_regmap_div_set_rate(struct clk_hw *hw, u= nsigned long rate, /* Would prefer clk_regmap_div_ro_ops but clashes with qcom */ =20 const struct clk_ops clk_regmap_divider_ops =3D { + .init =3D clk_regmap_init, .recalc_rate =3D clk_regmap_div_recalc_rate, .determine_rate =3D clk_regmap_div_determine_rate, .set_rate =3D clk_regmap_div_set_rate, @@ -128,6 +174,7 @@ const struct clk_ops clk_regmap_divider_ops =3D { EXPORT_SYMBOL_NS_GPL(clk_regmap_divider_ops, "CLK_MESON"); =20 const struct clk_ops clk_regmap_divider_ro_ops =3D { + .init =3D clk_regmap_init, .recalc_rate =3D clk_regmap_div_recalc_rate, .determine_rate =3D clk_regmap_div_determine_rate, }; @@ -170,6 +217,7 @@ static int clk_regmap_mux_determine_rate(struct clk_hw = *hw, } =20 const struct clk_ops clk_regmap_mux_ops =3D { + .init =3D clk_regmap_init, .get_parent =3D clk_regmap_mux_get_parent, .set_parent =3D clk_regmap_mux_set_parent, .determine_rate =3D clk_regmap_mux_determine_rate, @@ -177,6 +225,7 @@ const struct clk_ops clk_regmap_mux_ops =3D { EXPORT_SYMBOL_NS_GPL(clk_regmap_mux_ops, "CLK_MESON"); =20 const struct clk_ops clk_regmap_mux_ro_ops =3D { + .init =3D clk_regmap_init, .get_parent =3D clk_regmap_mux_get_parent, }; EXPORT_SYMBOL_NS_GPL(clk_regmap_mux_ro_ops, "CLK_MESON"); diff --git a/drivers/clk/meson/clk-regmap.h b/drivers/clk/meson/clk-regmap.h index e365312da54ece08098293b1a831c803415db814..f8cac2df5755b0f894570305604= 485f54c17ea49 100644 --- a/drivers/clk/meson/clk-regmap.h +++ b/drivers/clk/meson/clk-regmap.h @@ -7,6 +7,7 @@ #ifndef __CLK_REGMAP_H #define __CLK_REGMAP_H =20 +#include #include #include =20 @@ -31,6 +32,9 @@ static inline struct clk_regmap *to_clk_regmap(struct clk= _hw *hw) return container_of(hw, struct clk_regmap, hw); } =20 +/* clk_regmap init op to get and cache regmap from the controllers */ +int clk_regmap_init(struct clk_hw *hw); + /** * struct clk_regmap_gate_data - regmap backed gate specific data * diff --git a/drivers/clk/meson/sclk-div.c b/drivers/clk/meson/sclk-div.c index 9c4945234f2682ea4c4e9c2fc2158fe37dc46f74..4ba3d82810e8f2f456c349b3e56= e6b48e1c7290b 100644 --- a/drivers/clk/meson/sclk-div.c +++ b/drivers/clk/meson/sclk-div.c @@ -222,6 +222,11 @@ static int sclk_div_init(struct clk_hw *hw) struct clk_regmap *clk =3D to_clk_regmap(hw); struct meson_sclk_div_data *sclk =3D meson_sclk_div_data(clk); unsigned int val; + int ret; + + ret =3D clk_regmap_init(hw); + if (ret) + return ret; =20 val =3D meson_parm_read(clk->map, &sclk->div); =20 diff --git a/drivers/clk/meson/vclk.c b/drivers/clk/meson/vclk.c index 6a167ebdc8d74b9e5371100c6461ae395b7cc8af..009bd11930427f1f6465bf70acc= 35cd7de68d358 100644 --- a/drivers/clk/meson/vclk.c +++ b/drivers/clk/meson/vclk.c @@ -45,6 +45,7 @@ static int meson_vclk_gate_is_enabled(struct clk_hw *hw) } =20 const struct clk_ops meson_vclk_gate_ops =3D { + .init =3D clk_regmap_init, .enable =3D meson_vclk_gate_enable, .disable =3D meson_vclk_gate_disable, .is_enabled =3D meson_vclk_gate_is_enabled, @@ -127,6 +128,7 @@ static int meson_vclk_div_is_enabled(struct clk_hw *hw) } =20 const struct clk_ops meson_vclk_div_ops =3D { + .init =3D clk_regmap_init, .recalc_rate =3D meson_vclk_div_recalc_rate, .determine_rate =3D meson_vclk_div_determine_rate, .set_rate =3D meson_vclk_div_set_rate, diff --git a/drivers/clk/meson/vid-pll-div.c b/drivers/clk/meson/vid-pll-di= v.c index 965ed7281f57edf3c5d550dfdbe0c61b016e4684..2a3cdbe6d86a828a31724c49c59= e300ec5b1fa54 100644 --- a/drivers/clk/meson/vid-pll-div.c +++ b/drivers/clk/meson/vid-pll-div.c @@ -90,6 +90,7 @@ static unsigned long meson_vid_pll_div_recalc_rate(struct= clk_hw *hw, } =20 const struct clk_ops meson_vid_pll_div_ro_ops =3D { + .init =3D clk_regmap_init, .recalc_rate =3D meson_vid_pll_div_recalc_rate, }; EXPORT_SYMBOL_NS_GPL(meson_vid_pll_div_ro_ops, "CLK_MESON"); --=20 2.47.2