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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jun 2025 16:08:26.0325 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 09ac4a00-aa95-436e-0a4b-08ddb014b061 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DU6PEPF0000B622.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB6197 Content-Type: text/plain; charset="utf-8" Add support for GICv3 compat mode (FEAT_GCIE_LEGACY) which allows a GICv5 host to run GICv3-based VMs. This change enables the VHE/nVHE/hVHE/protected modes, but does not support nested virtualization. Co-authored-by: Timothy Hayes Signed-off-by: Timothy Hayes Signed-off-by: Sascha Bischoff --- arch/arm64/include/asm/kvm_asm.h | 2 ++ arch/arm64/include/asm/kvm_hyp.h | 2 ++ arch/arm64/kvm/Makefile | 3 +- arch/arm64/kvm/hyp/nvhe/hyp-main.c | 12 +++++++ arch/arm64/kvm/hyp/vgic-v3-sr.c | 51 +++++++++++++++++++++++++----- arch/arm64/kvm/sys_regs.c | 10 +++++- arch/arm64/kvm/vgic/vgic-init.c | 6 ++-- arch/arm64/kvm/vgic/vgic-v3.c | 6 ++++ arch/arm64/kvm/vgic/vgic-v5.c | 14 ++++++++ arch/arm64/kvm/vgic/vgic.h | 2 ++ include/kvm/arm_vgic.h | 9 +++++- 11 files changed, 104 insertions(+), 13 deletions(-) create mode 100644 arch/arm64/kvm/vgic/vgic-v5.c diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_= asm.h index bec227f9500a..ad1ef0460fd6 100644 --- a/arch/arm64/include/asm/kvm_asm.h +++ b/arch/arm64/include/asm/kvm_asm.h @@ -81,6 +81,8 @@ enum __kvm_host_smccc_func { __KVM_HOST_SMCCC_FUNC___kvm_timer_set_cntvoff, __KVM_HOST_SMCCC_FUNC___vgic_v3_save_vmcr_aprs, __KVM_HOST_SMCCC_FUNC___vgic_v3_restore_vmcr_aprs, + __KVM_HOST_SMCCC_FUNC___vgic_v3_compat_mode_enable, + __KVM_HOST_SMCCC_FUNC___vgic_v3_compat_mode_disable, __KVM_HOST_SMCCC_FUNC___pkvm_init_vm, __KVM_HOST_SMCCC_FUNC___pkvm_init_vcpu, __KVM_HOST_SMCCC_FUNC___pkvm_teardown_vm, diff --git a/arch/arm64/include/asm/kvm_hyp.h b/arch/arm64/include/asm/kvm_= hyp.h index e6be1f5d0967..9c8adc5186ec 100644 --- a/arch/arm64/include/asm/kvm_hyp.h +++ b/arch/arm64/include/asm/kvm_hyp.h @@ -85,6 +85,8 @@ void __vgic_v3_deactivate_traps(struct vgic_v3_cpu_if *cp= u_if); void __vgic_v3_save_vmcr_aprs(struct vgic_v3_cpu_if *cpu_if); void __vgic_v3_restore_vmcr_aprs(struct vgic_v3_cpu_if *cpu_if); int __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu); +void __vgic_v3_compat_mode_enable(void); +void __vgic_v3_compat_mode_disable(void); =20 #ifdef __KVM_NVHE_HYPERVISOR__ void __timer_enable_traps(struct kvm_vcpu *vcpu); diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile index 7c329e01c557..3ebc0570345c 100644 --- a/arch/arm64/kvm/Makefile +++ b/arch/arm64/kvm/Makefile @@ -23,7 +23,8 @@ kvm-y +=3D arm.o mmu.o mmio.o psci.o hypercalls.o pvtime.= o \ vgic/vgic-v3.o vgic/vgic-v4.o \ vgic/vgic-mmio.o vgic/vgic-mmio-v2.o \ vgic/vgic-mmio-v3.o vgic/vgic-kvm-device.o \ - vgic/vgic-its.o vgic/vgic-debug.o vgic/vgic-v3-nested.o + vgic/vgic-its.o vgic/vgic-debug.o vgic/vgic-v3-nested.o \ + vgic/vgic-v5.o =20 kvm-$(CONFIG_HW_PERF_EVENTS) +=3D pmu-emul.o pmu.o kvm-$(CONFIG_ARM64_PTR_AUTH) +=3D pauth.o diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-main.c b/arch/arm64/kvm/hyp/nvhe/h= yp-main.c index e9198e56e784..61af55df60a9 100644 --- a/arch/arm64/kvm/hyp/nvhe/hyp-main.c +++ b/arch/arm64/kvm/hyp/nvhe/hyp-main.c @@ -475,6 +475,16 @@ static void handle___vgic_v3_restore_vmcr_aprs(struct = kvm_cpu_context *host_ctxt __vgic_v3_restore_vmcr_aprs(kern_hyp_va(cpu_if)); } =20 +static void handle___vgic_v3_compat_mode_enable(struct kvm_cpu_context *ho= st_ctxt) +{ + __vgic_v3_compat_mode_enable(); +} + +static void handle___vgic_v3_compat_mode_disable(struct kvm_cpu_context *h= ost_ctxt) +{ + __vgic_v3_compat_mode_disable(); +} + static void handle___pkvm_init(struct kvm_cpu_context *host_ctxt) { DECLARE_REG(phys_addr_t, phys, host_ctxt, 1); @@ -603,6 +613,8 @@ static const hcall_t host_hcall[] =3D { HANDLE_FUNC(__kvm_timer_set_cntvoff), HANDLE_FUNC(__vgic_v3_save_vmcr_aprs), HANDLE_FUNC(__vgic_v3_restore_vmcr_aprs), + HANDLE_FUNC(__vgic_v3_compat_mode_enable), + HANDLE_FUNC(__vgic_v3_compat_mode_disable), HANDLE_FUNC(__pkvm_init_vm), HANDLE_FUNC(__pkvm_init_vcpu), HANDLE_FUNC(__pkvm_teardown_vm), diff --git a/arch/arm64/kvm/hyp/vgic-v3-sr.c b/arch/arm64/kvm/hyp/vgic-v3-s= r.c index f162b0df5cae..b03b5f012226 100644 --- a/arch/arm64/kvm/hyp/vgic-v3-sr.c +++ b/arch/arm64/kvm/hyp/vgic-v3-sr.c @@ -257,6 +257,18 @@ void __vgic_v3_restore_state(struct vgic_v3_cpu_if *cp= u_if) } } =20 +void __vgic_v3_compat_mode_enable(void) +{ + sysreg_clear_set_s(SYS_ICH_VCTLR_EL2, 0, ICH_VCTLR_EL2_V3); + isb(); +} + +void __vgic_v3_compat_mode_disable(void) +{ + sysreg_clear_set_s(SYS_ICH_VCTLR_EL2, ICH_VCTLR_EL2_V3, 0); + isb(); +} + void __vgic_v3_activate_traps(struct vgic_v3_cpu_if *cpu_if) { /* @@ -296,12 +308,19 @@ void __vgic_v3_activate_traps(struct vgic_v3_cpu_if *= cpu_if) } =20 /* - * Prevent the guest from touching the ICC_SRE_EL1 system - * register. Note that this may not have any effect, as - * ICC_SRE_EL2.Enable being RAO/WI is a valid implementation. + * GICv5 BET0 FEAT_GCIE_LEGACY doesn't include ICC_SRE_EL2. This is due + * to be relaxed in a future spec release, likely BET1, at which point + * this in condition can be dropped again. */ - write_gicreg(read_gicreg(ICC_SRE_EL2) & ~ICC_SRE_EL2_ENABLE, - ICC_SRE_EL2); + if (!static_branch_unlikely(&kvm_vgic_global_state.gicv5_cpuif)) { + /* + * Prevent the guest from touching the ICC_SRE_EL1 system + * register. Note that this may not have any effect, as + * ICC_SRE_EL2.Enable being RAO/WI is a valid implementation. + */ + write_gicreg(read_gicreg(ICC_SRE_EL2) & ~ICC_SRE_EL2_ENABLE, + ICC_SRE_EL2); + } =20 /* * If we need to trap system registers, we must write @@ -322,8 +341,14 @@ void __vgic_v3_deactivate_traps(struct vgic_v3_cpu_if = *cpu_if) cpu_if->vgic_vmcr =3D read_gicreg(ICH_VMCR_EL2); } =20 - val =3D read_gicreg(ICC_SRE_EL2); - write_gicreg(val | ICC_SRE_EL2_ENABLE, ICC_SRE_EL2); + /* + * Can be dropped in the future when GICv5 BET1 is released. See + * comment above. + */ + if (!static_branch_unlikely(&kvm_vgic_global_state.gicv5_cpuif)) { + val =3D read_gicreg(ICC_SRE_EL2); + write_gicreg(val | ICC_SRE_EL2_ENABLE, ICC_SRE_EL2); + } =20 if (!cpu_if->vgic_sre) { /* Make sure ENABLE is set at EL2 before setting SRE at EL1 */ @@ -423,9 +448,19 @@ void __vgic_v3_init_lrs(void) */ u64 __vgic_v3_get_gic_config(void) { - u64 val, sre =3D read_gicreg(ICC_SRE_EL1); + u64 val, sre; unsigned long flags =3D 0; =20 + /* + * In compat mode, we cannot access ICC_SRE_EL1 at any EL + * other than EL1 itself; just return the + * ICH_VTR_EL2. ICC_IDR0_EL1 is only implemented on a GICv5 + * system, so we first check if we have GICv5 support. + */ + if (static_branch_unlikely(&kvm_vgic_global_state.gicv5_cpuif)) + return read_gicreg(ICH_VTR_EL2); + + sre =3D read_gicreg(ICC_SRE_EL1); /* * To check whether we have a MMIO-based (GICv2 compatible) * CPU interface, we need to disable the system register diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 76c2f0da821f..de8297ccb31c 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1811,7 +1811,7 @@ static u64 sanitise_id_aa64pfr0_el1(const struct kvm_= vcpu *vcpu, u64 val) val |=3D SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV3, IMP); } =20 - if (kvm_vgic_global_state.type =3D=3D VGIC_V3) { + if (kvm_vgic_global_state.type =3D=3D VGIC_V3 || kvm_vgic_in_v3_compat_mo= de()) { val &=3D ~ID_AA64PFR0_EL1_GIC_MASK; val |=3D SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP); } @@ -1953,6 +1953,14 @@ static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, (vcpu_has_nv(vcpu) && !FIELD_GET(ID_AA64PFR0_EL1_EL2, user_val))) return -EINVAL; =20 + /* + * If we are running on a GICv5 host and support FEAT_GCIE_LEGACY, then + * we support GICv3. Fail attempts to do anything but set that to IMP. + */ + if (kvm_vgic_in_v3_compat_mode() && + FIELD_GET(ID_AA64PFR0_EL1_GIC_MASK, user_val) !=3D ID_AA64PFR0_EL1_GI= C_IMP) + return -EINVAL; + return set_id_reg(vcpu, rd, user_val); } =20 diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-ini= t.c index eb1205654ac8..5f6506e297c1 100644 --- a/arch/arm64/kvm/vgic/vgic-init.c +++ b/arch/arm64/kvm/vgic/vgic-init.c @@ -674,10 +674,12 @@ void kvm_vgic_init_cpu_hardware(void) * We want to make sure the list registers start out clear so that we * only have the program the used registers. */ - if (kvm_vgic_global_state.type =3D=3D VGIC_V2) + if (kvm_vgic_global_state.type =3D=3D VGIC_V2) { vgic_v2_init_lrs(); - else + } else if (kvm_vgic_global_state.type =3D=3D VGIC_V3 || + kvm_vgic_in_v3_compat_mode()) { kvm_call_hyp(__vgic_v3_init_lrs); + } } =20 /** diff --git a/arch/arm64/kvm/vgic/vgic-v3.c b/arch/arm64/kvm/vgic/vgic-v3.c index b9ad7c42c5b0..b5df4d36821d 100644 --- a/arch/arm64/kvm/vgic/vgic-v3.c +++ b/arch/arm64/kvm/vgic/vgic-v3.c @@ -734,6 +734,9 @@ void vgic_v3_load(struct kvm_vcpu *vcpu) { struct vgic_v3_cpu_if *cpu_if =3D &vcpu->arch.vgic_cpu.vgic_v3; =20 + if (static_branch_unlikely(&kvm_vgic_global_state.gicv5_cpuif)) + kvm_call_hyp(__vgic_v3_compat_mode_enable); + /* If the vgic is nested, perform the full state loading */ if (vgic_state_is_nested(vcpu)) { vgic_v3_load_nested(vcpu); @@ -764,4 +767,7 @@ void vgic_v3_put(struct kvm_vcpu *vcpu) =20 if (has_vhe()) __vgic_v3_deactivate_traps(cpu_if); + + if (static_branch_unlikely(&kvm_vgic_global_state.gicv5_cpuif)) + kvm_call_hyp(__vgic_v3_compat_mode_disable); } diff --git a/arch/arm64/kvm/vgic/vgic-v5.c b/arch/arm64/kvm/vgic/vgic-v5.c new file mode 100644 index 000000000000..57199449ca0f --- /dev/null +++ b/arch/arm64/kvm/vgic/vgic-v5.c @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include + +#include "vgic.h" + +inline bool kvm_vgic_in_v3_compat_mode(void) +{ + if (static_branch_unlikely(&kvm_vgic_global_state.gicv5_cpuif) && + kvm_vgic_global_state.has_gcie_v3_compat) + return true; + + return false; +} diff --git a/arch/arm64/kvm/vgic/vgic.h b/arch/arm64/kvm/vgic/vgic.h index 4349084cb9a6..5c78eb915a22 100644 --- a/arch/arm64/kvm/vgic/vgic.h +++ b/arch/arm64/kvm/vgic/vgic.h @@ -389,6 +389,8 @@ void vgic_v3_put_nested(struct kvm_vcpu *vcpu); void vgic_v3_handle_nested_maint_irq(struct kvm_vcpu *vcpu); void vgic_v3_nested_update_mi(struct kvm_vcpu *vcpu); =20 +inline bool kvm_vgic_in_v3_compat_mode(void); + int vgic_its_debug_init(struct kvm_device *dev); void vgic_its_debug_destroy(struct kvm_device *dev); =20 diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h index 4a34f7f0a864..6e16e303d80f 100644 --- a/include/kvm/arm_vgic.h +++ b/include/kvm/arm_vgic.h @@ -38,6 +38,7 @@ enum vgic_type { VGIC_V2, /* Good ol' GICv2 */ VGIC_V3, /* New fancy GICv3 */ + VGIC_V5, /* Newer, fancier GICv5 */ }; =20 /* same for all guests, as depending only on the _host's_ GIC model */ @@ -77,9 +78,15 @@ struct vgic_global { /* Pseudo GICv3 from outer space */ bool no_hw_deactivation; =20 - /* GIC system register CPU interface */ + /* GICv3 system register CPU interface */ struct static_key_false gicv3_cpuif; =20 + /* GICv5 host system */ + struct static_key_false gicv5_cpuif; + + /* GICv3 compat mode on a GICv5 host */ + bool has_gcie_v3_compat; + u32 ich_vtr_el2; }; =20 --=20 2.34.1