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Fri, 20 Jun 2025 05:10:55 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 1/3] arm64: dts: renesas: Add CN15 eMMC and SD overlays for RZ/V2N EVK Date: Fri, 20 Jun 2025 13:10:43 +0100 Message-ID: <20250620121045.56114-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250620121045.56114-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250620121045.56114-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Introduce device tree overlays to support the eMMC (RTK0EF0186B02000BJ) and microSD (RTK0EF0186B01000BJ) sub-boards via the CN15 connector on the RZ/V2N EVK. These overlays enable SDHI0 with appropriate pinctrl settings, regulator configurations, and GPIO handling. Shared DTSI fragments (rzv2-evk-cn15-emmc-common.dtsi and rzv2-evk-cn15-sd-common.dtsi) provide reusable configurations for both RZ/V2N and RZ/V2H EVKs, as both support the same CN15 sub-boards. Additionally, the base board DTS is updated to define an `mmc0` alias pointing to `&sdhi0`, and to add a fixed 1.8V regulator node (`reg_1p8v`) intended for use by the optional eMMC sub-board and, in the future, the ADV7535 HDMI encoder (not yet enabled in the DTS). Signed-off-by: Lad Prabhakar --- arch/arm64/boot/dts/renesas/Makefile | 4 ++ .../r9a09g056n48-rzv2n-evk-cn15-emmc.dtso | 15 +++++ .../r9a09g056n48-rzv2n-evk-cn15-sd.dtso | 16 +++++ .../dts/renesas/r9a09g056n48-rzv2n-evk.dts | 10 +++ .../renesas/rzv2-evk-cn15-emmc-common.dtsi | 46 +++++++++++++ .../dts/renesas/rzv2-evk-cn15-sd-common.dtsi | 67 +++++++++++++++++++ 6 files changed, 158 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk-cn15= -emmc.dtso create mode 100644 arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk-cn15= -sd.dtso create mode 100644 arch/arm64/boot/dts/renesas/rzv2-evk-cn15-emmc-common.d= tsi create mode 100644 arch/arm64/boot/dts/renesas/rzv2-evk-cn15-sd-common.dtsi diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/ren= esas/Makefile index 677ba3aa8931..130ef8f34d52 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -161,6 +161,10 @@ r9a09g047e57-smarc-cru-csi-ov5645-dtbs :=3D r9a09g047e= 57-smarc.dtb r9a09g047e57-sm dtb-$(CONFIG_ARCH_R9A09G047) +=3D r9a09g047e57-smarc-cru-csi-ov5645.dtb =20 dtb-$(CONFIG_ARCH_R9A09G056) +=3D r9a09g056n48-rzv2n-evk.dtb +dtb-$(CONFIG_ARCH_R9A09G056) +=3D r9a09g056n48-rzv2n-evk-cn15-emmc.dtbo +r9a09g056n48-rzv2n-evk-cn15-emmc.dts :=3D r9a09g056n48-rzv2n-evk.dtb r9a09= g056n48-rzv2n-evk-cn15-emmc.dtbo +dtb-$(CONFIG_ARCH_R9A09G056) +=3D r9a09g056n48-rzv2n-evk-cn15-sd.dtbo +r9a09g056n48-rzv2n-evk-cn15-sd.dts :=3D r9a09g056n48-rzv2n-evk.dtb r9a09g0= 56n48-rzv2n-evk-cn15-sd.dtbo =20 dtb-$(CONFIG_ARCH_R9A09G057) +=3D r9a09g057h44-rzv2h-evk.dtb dtb-$(CONFIG_ARCH_R9A09G057) +=3D r9a09g057h48-kakip.dtb diff --git a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk-cn15-emmc.d= tso b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk-cn15-emmc.dtso new file mode 100644 index 000000000000..c943150efcba --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk-cn15-emmc.dtso @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree overlay for the RZ/V2N EVK with the eMMC sub-board + * (RTK0EF0186802000BJ) connected to the CN15 connector. + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +/dts-v1/; +/plugin/; + +#define RZV2N_PA 10 +#define EMMC_GPIO(port, pin) RZG2L_GPIO(RZV2N_P##port, pin) + +#include "rzv2-evk-cn15-emmc-common.dtsi" diff --git a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk-cn15-sd.dts= o b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk-cn15-sd.dtso new file mode 100644 index 000000000000..6268dda138ab --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk-cn15-sd.dtso @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree overlay for the RZ/V2N EVK with the SD sub-board + * (RTK0EF0186B01000BJ) connected to the CN15 connector. + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +/dts-v1/; +/plugin/; + +#define RZV2N_PA 10 +#define SD_GPIO(port, pin) RZG2L_GPIO(RZV2N_P##port, pin) +#define SD_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZV2N_P##b, p, f) + +#include "rzv2-evk-cn15-sd-common.dtsi" diff --git a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts b/arch/= arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts index b63ee1ff18d5..795d9f6b9651 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts @@ -24,6 +24,7 @@ aliases { i2c6 =3D &i2c6; i2c7 =3D &i2c7; i2c8 =3D &i2c8; + mmc0 =3D &sdhi0; mmc1 =3D &sdhi1; serial0 =3D &scif; }; @@ -48,6 +49,15 @@ reg_0p8v: regulator-0p8v { regulator-always-on; }; =20 + reg_1p8v: regulator-1p8v { + compatible =3D "regulator-fixed"; + regulator-name =3D "fixed-1.8V"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + reg_3p3v: regulator-3p3v { compatible =3D "regulator-fixed"; regulator-name =3D "fixed-3.3V"; diff --git a/arch/arm64/boot/dts/renesas/rzv2-evk-cn15-emmc-common.dtsi b/a= rch/arm64/boot/dts/renesas/rzv2-evk-cn15-emmc-common.dtsi new file mode 100644 index 000000000000..7ac38f34d0b9 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzv2-evk-cn15-emmc-common.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Shared DT include for the eMMC Sub Board (RTK0EF0186B02000BJ), which + * is connected to the CN15 connector on the RZ/V2H and RZ/V2N EVKs. + * + * Contains common pinctrl and SDHI0 definitions. + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&pinctrl { + sdhi0_emmc_pins: emmc-pins { + sd0-clk { + pins =3D "SD0CLK"; + renesas,output-impedance =3D <3>; + slew-rate =3D <0>; + }; + + sd0-dat-cmd { + pins =3D "SD0DAT0", "SD0DAT1", "SD0DAT2", "SD0DAT3", "SD0DAT4", + "SD0DAT5", "SD0DAT6", "SD0DAT7", "SD0CMD"; + input-enable; + renesas,output-impedance =3D <3>; + slew-rate =3D <0>; + }; + }; +}; + +&sdhi0 { + pinctrl-0 =3D <&sdhi0_emmc_pins>; + pinctrl-1 =3D <&sdhi0_emmc_pins>; + pinctrl-names =3D "default", "state_uhs"; + vmmc-supply =3D <®_3p3v>; + vqmmc-supply =3D <®_1p8v>; + bus-width =3D <8>; + mmc-hs200-1_8v; + non-removable; + fixed-emmc-driver-type =3D <1>; + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/rzv2-evk-cn15-sd-common.dtsi b/arc= h/arm64/boot/dts/renesas/rzv2-evk-cn15-sd-common.dtsi new file mode 100644 index 000000000000..b402a6eaf61b --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzv2-evk-cn15-sd-common.dtsi @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Shared DT include for the microSD Sub Board (RTK0EF0186B01000BJ), which + * is connected to the CN15 connector on the RZ/V2H and RZ/V2N EVKs. + * + * Contains common pinctrl and SDHI0 definitions. + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + vqmmc_sdhi0: regulator-vqmmc-sdhi0 { + compatible =3D "regulator-gpio"; + regulator-name =3D "SDHI0 VqmmC"; + gpios =3D <&pinctrl SD_GPIO(A, 0) GPIO_ACTIVE_HIGH>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + gpios-states =3D <0>; + states =3D <3300000 0>, <1800000 1>; + }; +}; + +&pinctrl { + sdhi0-pwr-en-hog { + gpio-hog; + gpios =3D ; + output-high; + line-name =3D "sd0_pwr_en"; + }; + + sdhi0_pins: sd0 { + sd0-cd { + pinmux =3D ; /* SD0_CD */ + }; + + sd0-clk { + pins =3D "SD0CLK"; + renesas,output-impedance =3D <3>; + slew-rate =3D <0>; + }; + + sd0-dat-cmd { + pins =3D "SD0DAT0", "SD0DAT1", "SD0DAT2", "SD0DAT3", "SD0CMD"; + input-enable; + renesas,output-impedance =3D <3>; + slew-rate =3D <0>; + }; + }; +}; + +&sdhi0 { + pinctrl-0 =3D <&sdhi0_pins>; + pinctrl-1 =3D <&sdhi0_pins>; + pinctrl-names =3D "default", "state_uhs"; + vmmc-supply =3D <®_3p3v>; + vqmmc-supply =3D <&vqmmc_sdhi0>; + bus-width =3D <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status =3D "okay"; +}; --=20 2.49.0