From nobody Thu Oct 9 06:11:32 2025 Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0715F289342 for ; Fri, 20 Jun 2025 09:40:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.190 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750412441; cv=none; b=oVH7t3VygARNPVtAEEC2tBXjKAbpXpxpOnFSbFr/cpf14hCu7DvSj8kyelHECBSJoaPLeNxgEkaYwV1KAgUuzxIGWbqwe8wtvUGSHkZm9JBGLr1BJkZyaNvmUbK7bLGK2Ex0QR1vxk1k9mcTP1K0bYxJOt9EeqmqtmsgYGhdKGQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750412441; c=relaxed/simple; bh=dco+88cc+qOlIkE6vMe00lxJu53rq044z/EJKJb9neY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=SXzXUC/Zu9cRHkaQjftQJDEo3Zo69xWWOR6GGT/XVAYWMUMwQ6KFKEt4OfqCyUloHUThao3WTBnAylwvAryn7Qsu0KduTOPeMkZKTWlZwRe/MJh72rCdQz1a8s+WQcqhKG1VJ/t5tFWwbMOpckI/7I/SdqJ7b79tWeAHWG0b8xQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.190 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.163]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4bNsn52JYxz2Cd53; Fri, 20 Jun 2025 17:36:41 +0800 (CST) Received: from dggemv705-chm.china.huawei.com (unknown [10.3.19.32]) by mail.maildlp.com (Postfix) with ESMTPS id 9B685180043; Fri, 20 Jun 2025 17:40:36 +0800 (CST) Received: from kwepemq100007.china.huawei.com (7.202.195.175) by dggemv705-chm.china.huawei.com (10.3.19.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Fri, 20 Jun 2025 17:40:33 +0800 Received: from localhost.huawei.com (10.169.71.169) by kwepemq100007.china.huawei.com (7.202.195.175) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Fri, 20 Jun 2025 17:40:33 +0800 From: Yongbang Shi To: , , , , , , , , CC: , , , , , , , , , Subject: [PATCH v2 drm-dp 09/10] drm/hisilicon/hibmc: fix no showing problem with loading hibmc manually Date: Fri, 20 Jun 2025 17:31:03 +0800 Message-ID: <20250620093104.2016196-10-shiyongbang@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250620093104.2016196-1-shiyongbang@huawei.com> References: <20250620093104.2016196-1-shiyongbang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100002.china.huawei.com (7.221.188.206) To kwepemq100007.china.huawei.com (7.202.195.175) Content-Type: text/plain; charset="utf-8" From: Baihan Li When using command rmmod and insmod, there is no showing in second time insmoding. Because DP controller won't send HPD signals, if connection doesn't change or controller isn't reset. So add reset before unreset in hibmc_dp_hw_init(). Fixes: 3c7623fb5bb6 ("drm/hisilicon/hibmc: Enable this hot plug detect of i= rq feature") Fixes: 94ee73ee3020 ("drm/hisilicon/hibmc: add dp hw moduel in hibmc driver= ") Signed-off-by: Baihan Li Signed-off-by: Yongbang Shi --- ChangeLog: v1 -> v2: - fix the tag, suggested by Dmitry Baryshkov. - separate the patch, suggested by Dmitry Baryshkov. --- drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c b/drivers/gpu/drm/h= isilicon/hibmc/dp/dp_hw.c index 5b1f943b601c..edb7539d830e 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c @@ -178,6 +178,8 @@ int hibmc_dp_hw_init(struct hibmc_dp *dp) writel(0, dp_dev->base + HIBMC_DP_INTR_ENABLE); writel(HIBMC_DP_INT_RST, dp_dev->base + HIBMC_DP_INTR_ORIGINAL_STATUS); /* rst */ + writel(0, dp_dev->base + HIBMC_DP_DPTX_RST_CTRL); + usleep_range(30, 50); writel(HIBMC_DP_DPTX_RST, dp_dev->base + HIBMC_DP_DPTX_RST_CTRL); /* clock enable */ writel(HIBMC_DP_CLK_EN, dp_dev->base + HIBMC_DP_DPTX_CLK_CTRL); --=20 2.33.0