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charset="utf-8" Add VIRTIO_ID_SPI definition for virtio SPI. Signed-off-by: Haixu Cui --- include/uapi/linux/virtio_ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/uapi/linux/virtio_ids.h b/include/uapi/linux/virtio_id= s.h index 7aa2eb766205..6c12db16faa3 100644 --- a/include/uapi/linux/virtio_ids.h +++ b/include/uapi/linux/virtio_ids.h @@ -68,6 +68,7 @@ #define VIRTIO_ID_AUDIO_POLICY 39 /* virtio audio policy */ #define VIRTIO_ID_BT 40 /* virtio bluetooth */ #define VIRTIO_ID_GPIO 41 /* virtio gpio */ +#define VIRTIO_ID_SPI 45 /* virtio spi */ =20 /* * Virtio Transitional IDs --=20 2.34.1 From nobody Thu Oct 9 04:50:04 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCEAC202F9F; Fri, 20 Jun 2025 04:13:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; 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charset="utf-8" Add virtio-spi.h header for virtio SPI. Signed-off-by: Haixu Cui --- include/uapi/linux/virtio_spi.h | 185 ++++++++++++++++++++++++++++++++ 1 file changed, 185 insertions(+) create mode 100644 include/uapi/linux/virtio_spi.h diff --git a/include/uapi/linux/virtio_spi.h b/include/uapi/linux/virtio_sp= i.h new file mode 100644 index 000000000000..eece995449b6 --- /dev/null +++ b/include/uapi/linux/virtio_spi.h @@ -0,0 +1,185 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (C) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#ifndef _LINUX_VIRTIO_VIRTIO_SPI_H +#define _LINUX_VIRTIO_VIRTIO_SPI_H + +#include +#include +#include +#include + +/* Sample data on trailing clock edge */ +#define VIRTIO_SPI_CPHA BIT(0) +/* Clock is high when IDLE */ +#define VIRTIO_SPI_CPOL BIT(1) +/* Chip Select is active high */ +#define VIRTIO_SPI_CS_HIGH BIT(2) +/* Transmit LSB first */ +#define VIRTIO_SPI_MODE_LSB_FIRST BIT(3) +/* Loopback mode */ +#define VIRTIO_SPI_MODE_LOOP BIT(4) + +/* + * All config fields are read-only for the Virtio SPI driver + * + * @cs_max_number: maximum number of chipselect the host SPI controller + * supports. + * @cs_change_supported: indicates if the host SPI controller supports to = toggle + * chipselect after each transfer in one message: + * 0: unsupported, chipselect will be kept in active state throughout the + * message transaction; + * 1: supported. + * Note: Message here contains a sequence of SPI transfers. + * @tx_nbits_supported: indicates the supported number of bit for writing: + * bit 0: DUAL (2-bit transfer), 1 for supported + * bit 1: QUAD (4-bit transfer), 1 for supported + * bit 2: OCTAL (8-bit transfer), 1 for supported + * other bits are reserved as 0, 1-bit transfer is always supported. + * @rx_nbits_supported: indicates the supported number of bit for reading: + * bit 0: DUAL (2-bit transfer), 1 for supported + * bit 1: QUAD (4-bit transfer), 1 for supported + * bit 2: OCTAL (8-bit transfer), 1 for supported + * other bits are reserved as 0, 1-bit transfer is always supported. + * @bits_per_word_mask: mask indicating which values of bits_per_word are + * supported. If not set, no limitation for bits_per_word. + * @mode_func_supported: indicates the following features are supported or= not: + * bit 0-1: CPHA feature + * 0b00: invalid, should support as least one CPHA setting + * 0b01: supports CPHA=3D0 only + * 0b10: supports CPHA=3D1 only + * 0b11: supports CPHA=3D0 and CPHA=3D1. + * bit 2-3: CPOL feature + * 0b00: invalid, should support as least one CPOL setting + * 0b01: supports CPOL=3D0 only + * 0b10: supports CPOL=3D1 only + * 0b11: supports CPOL=3D0 and CPOL=3D1. + * bit 4: chipselect active high feature, 0 for unsupported and 1 for + * supported, chipselect active low is supported by default. + * bit 5: LSB first feature, 0 for unsupported and 1 for supported, + * MSB first is supported by default. + * bit 6: loopback mode feature, 0 for unsupported and 1 for supported, + * normal mode is supported by default. + * @max_freq_hz: the maximum clock rate supported in Hz unit, 0 means no + * limitation for transfer speed. + * @max_word_delay_ns: the maximum word delay supported in ns unit, + * 0 means word delay feature is unsupported. + * Note: Just as one message contains a sequence of transfers, + * one transfer may contain a sequence of words. + * @max_cs_setup_ns: the maximum delay supported after chipselect is asser= ted, + * in ns unit, 0 means delay is not supported to introduce after chipsel= ect is + * asserted. + * @max_cs_hold_ns: the maximum delay supported before chipselect is deass= erted, + * in ns unit, 0 means delay is not supported to introduce before chipse= lect + * is deasserted. + * @max_cs_incative_ns: maximum delay supported after chipselect is deasse= rted, + * in ns unit, 0 means delay is not supported to introduce after chipsel= ect is + * deasserted. + */ +struct virtio_spi_config { + /* # of /dev/spidev.CS with CS=3D0..chip_select_max_number -1 */ + __u8 cs_max_number; + __u8 cs_change_supported; +#define VIRTIO_SPI_RX_TX_SUPPORT_DUAL BIT(0) +#define VIRTIO_SPI_RX_TX_SUPPORT_QUAD BIT(1) +#define VIRTIO_SPI_RX_TX_SUPPORT_OCTAL BIT(2) + __u8 tx_nbits_supported; + __u8 rx_nbits_supported; + __le32 bits_per_word_mask; +#define VIRTIO_SPI_MF_SUPPORT_CPHA_0 BIT(0) +#define VIRTIO_SPI_MF_SUPPORT_CPHA_1 BIT(1) +#define VIRTIO_SPI_MF_SUPPORT_CPOL_0 BIT(2) +#define VIRTIO_SPI_MF_SUPPORT_CPOL_1 BIT(3) +#define VIRTIO_SPI_MF_SUPPORT_CS_HIGH BIT(4) +#define VIRTIO_SPI_MF_SUPPORT_LSB_FIRST BIT(5) +#define VIRTIO_SPI_MF_SUPPORT_LOOPBACK BIT(6) + __le32 mode_func_supported; + __le32 max_freq_hz; + __le32 max_word_delay_ns; + __le32 max_cs_setup_ns; + __le32 max_cs_hold_ns; + __le32 max_cs_inactive_ns; +}; + +/* + * @chip_select_id: chipselect index the SPI transfer used. + * + * @bits_per_word: the number of bits in each SPI transfer word. + * + * @cs_change: whether to deselect device after finishing this transfer + * before starting the next transfer, 0 means cs keep asserted and + * 1 means cs deasserted then asserted again. + * + * @tx_nbits: bus width for write transfer. + * 0,1: bus width is 1, also known as SINGLE + * 2 : bus width is 2, also known as DUAL + * 4 : bus width is 4, also known as QUAD + * 8 : bus width is 8, also known as OCTAL + * other values are invalid. + * + * @rx_nbits: bus width for read transfer. + * 0,1: bus width is 1, also known as SINGLE + * 2 : bus width is 2, also known as DUAL + * 4 : bus width is 4, also known as QUAD + * 8 : bus width is 8, also known as OCTAL + * other values are invalid. + * + * @reserved: for future use. + * + * @mode: SPI transfer mode. + * bit 0: CPHA, determines the timing (i.e. phase) of the data + * bits relative to the clock pulses.For CPHA=3D0, the + * "out" side changes the data on the trailing edge of the + * preceding clock cycle, while the "in" side captures the data + * on (or shortly after) the leading edge of the clock cycle. + * For CPHA=3D1, the "out" side changes the data on the leading + * edge of the current clock cycle, while the "in" side + * captures the data on (or shortly after) the trailing edge of + * the clock cycle. + * bit 1: CPOL, determines the polarity of the clock. CPOL=3D0 is a + * clock which idles at 0, and each cycle consists of a pulse + * of 1. CPOL=3D1 is a clock which idles at 1, and each cycle + * consists of a pulse of 0. + * bit 2: CS_HIGH, if 1, chip select active high, else active low. + * bit 3: LSB_FIRST, determines per-word bits-on-wire, if 0, MSB + * first, else LSB first. + * bit 4: LOOP, loopback mode. + * + * @freq: the transfer speed in Hz. + * + * @word_delay_ns: delay to be inserted between consecutive words of a + * transfer, in ns unit. + * + * @cs_setup_ns: delay to be introduced after CS is asserted, in ns + * unit. + * + * @cs_delay_hold_ns: delay to be introduced before CS is deasserted + * for each transfer, in ns unit. + * + * @cs_change_delay_inactive_ns: delay to be introduced after CS is + * deasserted and before next asserted, in ns unit. + */ +struct spi_transfer_head { + __u8 chip_select_id; + __u8 bits_per_word; + __u8 cs_change; + __u8 tx_nbits; + __u8 rx_nbits; + __u8 reserved[3]; + __le32 mode; + __le32 freq; + __le32 word_delay_ns; + __le32 cs_setup_ns; + __le32 cs_delay_hold_ns; + __le32 cs_change_delay_inactive_ns; +}; + +struct spi_transfer_result { +#define VIRTIO_SPI_TRANS_OK 0 +#define VIRTIO_SPI_PARAM_ERR 1 +#define VIRTIO_SPI_TRANS_ERR 2 + u8 result; +}; + +#endif /* #ifndef _LINUX_VIRTIO_VIRTIO_SPI_H */ --=20 2.34.1 From nobody Thu Oct 9 04:50:04 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE6CB2080E8; Fri, 20 Jun 2025 04:13:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750392805; cv=none; b=hO30LrFlJRNFrrrp9G+sUCLsbde1hrm5oRqQJ7TIPiVETaAi17W89Y8L6Xl5y2hsWyRi2ZBefJhDpEsnoYClsMEsttwtQfx+PGFZ65GfA3LNXlmxQ/zMF8Fzr/qr4PbXCZ/Fu8cEBf3ygLcp3f95P6jQhHIFPMf4ww4cNa3BUJs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750392805; c=relaxed/simple; bh=8FptSwWZyGtIpQLiBoAZ0n1O4sbPSyTxtyb9XRNOBJA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mzxsQi/vz1FtXuHmYjRQXJKI4HKcsB19fvQwstW005DZYGrSFzIiexjA1o1sX3htUCvS7MHm00oMWbmKDoC4HgcuJnDBQv2JWD7DcZWcWVoN+YrqqUFeQ8ZGSCKEHfLYXvrI7DJDNPfHtfMvbHDqf+RiLLQP8DgMJIa453WrES8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=e4fsLqjM; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="e4fsLqjM" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 55JL1pb3024412; Fri, 20 Jun 2025 04:13:15 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= /FzTP9jZqiTDmWoK/PEsyosrso3u7rJVOoh9iXGZMbo=; b=e4fsLqjMYnnM1aS0 LWRGsNGOmr3Be2ZukfL1R2RufyFM9Li7oZifYRO8F3+q86hodGFSnYuEXcRCW+y0 4ZnxgtF46pz8+w7lY/dq1XHeJISczBS04WPHqXnukZmqjHEYAjUreVaA3iZrm/Ym D3qqP4aBkA8nsq4Vs5Bf7HP7+fNBDREkBcG53VwxEcN6PfrpsjPDVY9m6SJQDSy6 IRJwdc68L5z+RNBaqx8x7phPET1xkXzJg6GeZKBv06QaPWGpmFPObvGrU+0p0XOb RiVR2Qq3ZCnodtklikDsw5Jq2eNJFRnq/5Rad3kNtN4l819JYvbXdxP3YCARl/cy PmnygQ== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 47bw13e09d-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 20 Jun 2025 04:13:14 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 55K4DEJ7008419 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 20 Jun 2025 04:13:14 GMT Received: from haixcui1-gv.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 19 Jun 2025 21:13:11 -0700 From: Haixu Cui To: , , , , , , , , CC: , Haixu Cui Subject: [RFC PATCH v5 3/3] SPI: Add virtio SPI driver. Date: Fri, 20 Jun 2025 12:12:30 +0800 Message-ID: <20250620041230.731504-4-quic_haixcui@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620041230.731504-1-quic_haixcui@quicinc.com> References: <20250620041230.731504-1-quic_haixcui@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=QbBmvtbv c=1 sm=1 tr=0 ts=6854dfda cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=6IFa9wvqVegA:10 a=COk6AnOGAAAA:8 a=VwQbUJbxAAAA:8 a=n0-Sf9z_k3ELN0rn3eUA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: C-uag0wmIJjfZwI2e8AvUjQKAREtZqmq X-Proofpoint-GUID: C-uag0wmIJjfZwI2e8AvUjQKAREtZqmq X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjIwMDAyOSBTYWx0ZWRfXz0WeGyZ9AqLu H2vSxrTyzYcnchOHpWZSYQ0SOz+IUy/SjfMBWM9fZPNWSLWnaZ88OhqUVaASPPclVgl9jsqCr2v u1/bBlUJ8eadAUeEXlkMtwRByjogU3hx+akwV8h8s1FRrJr1hk5eFN3rbAOH9ao8P8v0zmtW6zJ q6zsYlZkx+Cc4Ga5CjTS85OEu1vbXlnmCTgunpkLFKWgqIlYrs2ImTYyf3oyFq3KGuGMEYdEy/a G3T6NxWeTira7Uq2aO8M4gb+iY1jGgPoS+6DQWB6Ag1VF8bv6dTgDCa3HaaFxk/wR0EUM7sAe0H 8E7UffWuoYy2Z8hKJIoAMUMTvQPbeGoHJ5B0DtMX/0AFswgeIf4e9YzhExJQflGd1DZZPggZo+i NypG1s/zxeuUwteRwUADjFaenKywv8FRmpK2hlwcwREE+SObexEyeehO3Qr2DnqGiMuPWH5L X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-20_01,2025-06-18_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 malwarescore=0 mlxlogscore=999 bulkscore=0 adultscore=0 phishscore=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 mlxscore=0 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506200029 Content-Type: text/plain; charset="utf-8" This is the virtio SPI Linux kernel driver. Signed-off-by: Haixu Cui --- MAINTAINERS | 6 + drivers/spi/Kconfig | 11 + drivers/spi/Makefile | 1 + drivers/spi/spi-virtio.c | 444 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 462 insertions(+) create mode 100644 drivers/spi/spi-virtio.c diff --git a/MAINTAINERS b/MAINTAINERS index bf73c90a957a..32295c5c224f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -26342,6 +26342,12 @@ S: Maintained F: include/uapi/linux/virtio_snd.h F: sound/virtio/* =20 +VIRTIO SPI DRIVER +M: Haixu Cui +S: Maintained +F: drivers/spi/spi-virtio.c +F: include/uapi/linux/virtio_spi.h + VIRTUAL BOX GUEST DEVICE DRIVER M: Hans de Goede M: Arnd Bergmann diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index c51da3fc3604..63a0235ddfbb 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -1207,6 +1207,17 @@ config SPI_UNIPHIER =20 If your SoC supports SCSSI, say Y here. =20 +config SPI_VIRTIO + tristate "Virtio SPI Controller" + depends on SPI_MASTER && VIRTIO + help + If you say yes to this option, support will be included for the virtio + SPI controller driver. The hardware can be emulated by any device model + software according to the virtio protocol. + + This driver can also be built as a module. If so, the module + will be called spi-virtio. + config SPI_XCOMM tristate "Analog Devices AD-FMCOMMS1-EBZ SPI-I2C-bridge driver" depends on I2C diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 4ea89f6fc531..827a1e7e5ce8 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -156,6 +156,7 @@ spi-thunderx-objs :=3D spi-cavium.o spi-cavium-thunde= rx.o obj-$(CONFIG_SPI_THUNDERX) +=3D spi-thunderx.o obj-$(CONFIG_SPI_TOPCLIFF_PCH) +=3D spi-topcliff-pch.o obj-$(CONFIG_SPI_UNIPHIER) +=3D spi-uniphier.o +obj-$(CONFIG_SPI_VIRTIO) +=3D spi-virtio.o obj-$(CONFIG_SPI_XCOMM) +=3D spi-xcomm.o obj-$(CONFIG_SPI_XILINX) +=3D spi-xilinx.o obj-$(CONFIG_SPI_XLP) +=3D spi-xlp.o diff --git a/drivers/spi/spi-virtio.c b/drivers/spi/spi-virtio.c new file mode 100644 index 000000000000..f4f7faf62112 --- /dev/null +++ b/drivers/spi/spi-virtio.c @@ -0,0 +1,444 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * SPI bus driver for the Virtio SPI controller + * Copyright (C) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct virtio_spi_req { + struct completion completion; + struct spi_transfer_head transfer_head ____cacheline_aligned; + const uint8_t *tx_buf ____cacheline_aligned; + uint8_t *rx_buf ____cacheline_aligned; + struct spi_transfer_result result ____cacheline_aligned; +}; + +struct virtio_spi_priv { + /* Virtio SPI message */ + struct virtio_spi_req spi_req; + /* The virtio device we're associated with */ + struct virtio_device *vdev; + /* Pointer to the virtqueue */ + struct virtqueue *vq; + /* Copy of config space mode_func_supported */ + u32 mode_func_supported; + /* Copy of config space max_freq_hz */ + u32 max_freq_hz; +}; + +static void virtio_spi_msg_done(struct virtqueue *vq) +{ + struct virtio_spi_req *req; + unsigned int len; + + while ((req =3D virtqueue_get_buf(vq, &len))) + complete(&req->completion); +} + +/* + * virtio_spi_set_delays - Set delay parameters for SPI transfer + * + * This function sets various delay parameters for SPI transfer, + * including delay after CS asserted, timing intervals between + * adjacent words within a transfer, delay before and after CS + * deasserted. It converts these delay parameters to nanoseconds + * using spi_delay_to_ns and stores the results in spi_transfer_head + * structure. + * If the conversion fails, the function logs a warning message and + * returns an error code. + * . . . . . . . . . . + * Delay + A + + B + + C + D + E + F + A + + * . . . . . . . . . . + * ___. . . . . . .___.___. . + * CS# |___.______.____.____.___.___| . |___._____________ + * . . . . . . . . . . + * . . . . . . . . . . + * SCLK__.___.___NNN_____NNN__.___.___.___.___.___.___NNN_______ + * + * NOTE: 1st transfer has two words, the delay between these two words are + * 'B' in the diagram. + * + * A =3D> struct spi_device -> cs_setup + * B =3D> max{struct spi_transfer -> word_delay, struct spi_device -> word= _delay} + * Note: spi_device and spi_transfer both have word_delay, Linux + * choose the bigger one, refer to _spi_xfer_word_delay_update fun= ction + * C =3D> struct spi_transfer -> delay + * D =3D> struct spi_device -> cs_hold + * E =3D> struct spi_device -> cs_inactive + * F =3D> struct spi_transfer -> cs_change_delay + * + * So the corresponding relationship: + * A <=3D=3D=3D> cs_setup_ns (after CS asserted) + * B <=3D=3D=3D> word_delay_ns (delay between adjacent words within a tr= ansfer) + * C+D <=3D=3D=3D> cs_delay_hold_ns (before CS deasserted) + * E+F <=3D=3D=3D> cs_change_delay_inactive_ns (after CS deasserted, these= two + * values are also recommended in the Linux driver to be added up) + */ +static int virtio_spi_set_delays(struct spi_transfer_head *th, + struct spi_device *spi, + struct spi_transfer *xfer) +{ + int cs_setup; + int cs_word_delay_xfer; + int cs_word_delay_spi; + int delay; + int cs_hold; + int cs_inactive; + int cs_change_delay; + + cs_setup =3D spi_delay_to_ns(&spi->cs_setup, xfer); + if (cs_setup < 0) { + dev_warn(&spi->dev, "Cannot convert cs_setup\n"); + return cs_setup; + } + th->cs_setup_ns =3D cpu_to_le32((u32)cs_setup); + + cs_word_delay_xfer =3D spi_delay_to_ns(&xfer->word_delay, xfer); + if (cs_word_delay_xfer < 0) { + dev_warn(&spi->dev, "Cannot convert cs_word_delay_xfer\n"); + return cs_word_delay_xfer; + } + cs_word_delay_spi =3D spi_delay_to_ns(&spi->word_delay, xfer); + if (cs_word_delay_spi < 0) { + dev_warn(&spi->dev, "Cannot convert cs_word_delay_spi\n"); + return cs_word_delay_spi; + } + if (cs_word_delay_spi > cs_word_delay_xfer) + th->word_delay_ns =3D cpu_to_le32((u32)cs_word_delay_spi); + else + th->word_delay_ns =3D cpu_to_le32((u32)cs_word_delay_xfer); + + delay =3D spi_delay_to_ns(&xfer->delay, xfer); + if (delay < 0) { + dev_warn(&spi->dev, "Cannot convert delay\n"); + return delay; + } + cs_hold =3D spi_delay_to_ns(&spi->cs_hold, xfer); + if (cs_hold < 0) { + dev_warn(&spi->dev, "Cannot convert cs_hold\n"); + return cs_hold; + } + th->cs_delay_hold_ns =3D cpu_to_le32((u32)delay + (u32)cs_hold); + + cs_inactive =3D spi_delay_to_ns(&spi->cs_inactive, xfer); + if (cs_inactive < 0) { + dev_warn(&spi->dev, "Cannot convert cs_inactive\n"); + return cs_inactive; + } + cs_change_delay =3D spi_delay_to_ns(&xfer->cs_change_delay, xfer); + if (cs_change_delay < 0) { + dev_warn(&spi->dev, "Cannot convert cs_change_delay\n"); + return cs_change_delay; + } + th->cs_change_delay_inactive_ns =3D + cpu_to_le32((u32)cs_inactive + (u32)cs_change_delay); + + return 0; +} + +static int virtio_spi_transfer_one(struct spi_controller *ctrl, + struct spi_device *spi, + struct spi_transfer *xfer) +{ + struct virtio_spi_priv *priv =3D spi_controller_get_devdata(ctrl); + struct virtio_spi_req *spi_req =3D &priv->spi_req; + struct spi_transfer_head *th; + struct scatterlist sg_out_head, sg_out_payload; + struct scatterlist sg_in_result, sg_in_payload; + struct scatterlist *sgs[4]; + unsigned int outcnt =3D 0u; + unsigned int incnt =3D 0u; + int ret; + + th =3D &spi_req->transfer_head; + + /* Fill struct spi_transfer_head */ + th->chip_select_id =3D spi_get_chipselect(spi, 0); + th->bits_per_word =3D spi->bits_per_word; + th->cs_change =3D xfer->cs_change; + th->tx_nbits =3D xfer->tx_nbits; + th->rx_nbits =3D xfer->rx_nbits; + th->reserved[0] =3D 0; + th->reserved[1] =3D 0; + th->reserved[2] =3D 0; + + BUILD_BUG_ON(VIRTIO_SPI_CPHA !=3D SPI_CPHA); + BUILD_BUG_ON(VIRTIO_SPI_CPOL !=3D SPI_CPOL); + BUILD_BUG_ON(VIRTIO_SPI_CS_HIGH !=3D SPI_CS_HIGH); + BUILD_BUG_ON(VIRTIO_SPI_MODE_LSB_FIRST !=3D SPI_LSB_FIRST); + + th->mode =3D cpu_to_le32(spi->mode & (SPI_LSB_FIRST | SPI_CS_HIGH | + SPI_CPOL | SPI_CPHA)); + if ((spi->mode & SPI_LOOP) !=3D 0) + th->mode |=3D cpu_to_le32(VIRTIO_SPI_MODE_LOOP); + + th->freq =3D cpu_to_le32(xfer->speed_hz); + + ret =3D virtio_spi_set_delays(th, spi, xfer); + if (ret) + goto msg_done; + + /* Set buffers */ + spi_req->tx_buf =3D xfer->tx_buf; + spi_req->rx_buf =3D xfer->rx_buf; + + /* Prepare sending of virtio message */ + init_completion(&spi_req->completion); + + sg_init_one(&sg_out_head, th, sizeof(*th)); + sgs[outcnt] =3D &sg_out_head; + outcnt++; + + if (spi_req->tx_buf) { + sg_init_one(&sg_out_payload, spi_req->tx_buf, xfer->len); + sgs[outcnt] =3D &sg_out_payload; + outcnt++; + } + + if (spi_req->rx_buf) { + sg_init_one(&sg_in_payload, spi_req->rx_buf, xfer->len); + sgs[outcnt] =3D &sg_in_payload; + incnt++; + } + + sg_init_one(&sg_in_result, &spi_req->result, + sizeof(struct spi_transfer_result)); + sgs[outcnt + incnt] =3D &sg_in_result; + incnt++; + + ret =3D virtqueue_add_sgs(priv->vq, sgs, outcnt, incnt, spi_req, + GFP_KERNEL); + if (ret) + goto msg_done; + + /* Simple implementation: There can be only one transfer in flight */ + virtqueue_kick(priv->vq); + + wait_for_completion(&priv->spi_req.completion); + + /* Read result from message and translate return code */ + switch (priv->spi_req.result.result) { + case VIRTIO_SPI_TRANS_OK: + /* ret is 0 */ + break; + case VIRTIO_SPI_PARAM_ERR: + ret =3D -EINVAL; + break; + case VIRTIO_SPI_TRANS_ERR: + ret =3D -EIO; + break; + default: /* Protocol violation */ + ret =3D -EIO; + break; + } + +msg_done: + if (ret) + ctrl->cur_msg->status =3D ret; + + return ret; +} + +static void virtio_spi_read_config(struct virtio_device *vdev) +{ + struct spi_controller *ctrl =3D dev_get_drvdata(&vdev->dev); + struct virtio_spi_priv *priv =3D vdev->priv; + u8 cs_max_number; + u8 tx_nbits_supported; + u8 rx_nbits_supported; + + cs_max_number =3D virtio_cread8(vdev, offsetof(struct virtio_spi_config, + cs_max_number)); + ctrl->num_chipselect =3D cs_max_number; + + /* Set the mode bits which are understood by this driver */ + priv->mode_func_supported =3D + virtio_cread32(vdev, offsetof(struct virtio_spi_config, + mode_func_supported)); + ctrl->mode_bits =3D priv->mode_func_supported & + (VIRTIO_SPI_CS_HIGH | VIRTIO_SPI_MODE_LSB_FIRST); + if ((priv->mode_func_supported & VIRTIO_SPI_MF_SUPPORT_CPHA_1) !=3D 0) + ctrl->mode_bits |=3D VIRTIO_SPI_CPHA; + if ((priv->mode_func_supported & VIRTIO_SPI_MF_SUPPORT_CPOL_1) !=3D 0) + ctrl->mode_bits |=3D VIRTIO_SPI_CPOL; + if ((priv->mode_func_supported & VIRTIO_SPI_MF_SUPPORT_LSB_FIRST) !=3D 0) + ctrl->mode_bits |=3D SPI_LSB_FIRST; + if ((priv->mode_func_supported & VIRTIO_SPI_MF_SUPPORT_LOOPBACK) !=3D 0) + ctrl->mode_bits |=3D SPI_LOOP; + tx_nbits_supported =3D + virtio_cread8(vdev, offsetof(struct virtio_spi_config, + tx_nbits_supported)); + if ((tx_nbits_supported & VIRTIO_SPI_RX_TX_SUPPORT_DUAL) !=3D 0) + ctrl->mode_bits |=3D SPI_TX_DUAL; + if ((tx_nbits_supported & VIRTIO_SPI_RX_TX_SUPPORT_QUAD) !=3D 0) + ctrl->mode_bits |=3D SPI_TX_QUAD; + if ((tx_nbits_supported & VIRTIO_SPI_RX_TX_SUPPORT_OCTAL) !=3D 0) + ctrl->mode_bits |=3D SPI_TX_OCTAL; + rx_nbits_supported =3D + virtio_cread8(vdev, offsetof(struct virtio_spi_config, + rx_nbits_supported)); + if ((rx_nbits_supported & VIRTIO_SPI_RX_TX_SUPPORT_DUAL) !=3D 0) + ctrl->mode_bits |=3D SPI_RX_DUAL; + if ((rx_nbits_supported & VIRTIO_SPI_RX_TX_SUPPORT_QUAD) !=3D 0) + ctrl->mode_bits |=3D SPI_RX_QUAD; + if ((rx_nbits_supported & VIRTIO_SPI_RX_TX_SUPPORT_OCTAL) !=3D 0) + ctrl->mode_bits |=3D SPI_RX_OCTAL; + + ctrl->bits_per_word_mask =3D + virtio_cread32(vdev, offsetof(struct virtio_spi_config, + bits_per_word_mask)); + + priv->max_freq_hz =3D + virtio_cread32(vdev, offsetof(struct virtio_spi_config, + max_freq_hz)); +} + +static int virtio_spi_find_vqs(struct virtio_spi_priv *priv) +{ + struct virtqueue *vq; + + vq =3D virtio_find_single_vq(priv->vdev, virtio_spi_msg_done, "spi-rq"); + if (IS_ERR(vq)) + return (int)PTR_ERR(vq); + priv->vq =3D vq; + return 0; +} + +/* Function must not be called before virtio_spi_find_vqs() has been run */ +static void virtio_spi_del_vq(struct virtio_device *vdev) +{ + virtio_reset_device(vdev); + vdev->config->del_vqs(vdev); +} + +static int virtio_spi_probe(struct virtio_device *vdev) +{ + struct virtio_spi_priv *priv; + struct spi_controller *ctrl; + int err; + u32 bus_num; + + ctrl =3D devm_spi_alloc_host(&vdev->dev, sizeof(*priv)); + if (!ctrl) + return -ENOMEM; + + priv =3D spi_controller_get_devdata(ctrl); + priv->vdev =3D vdev; + vdev->priv =3D priv; + ctrl->dev.of_node =3D vdev->dev.of_node; + + /* + * Setup ACPI node for controlled devices which will be probed through + * ACPI. + */ + ACPI_COMPANION_SET(&vdev->dev, ACPI_COMPANION(vdev->dev.parent)); + + dev_set_drvdata(&vdev->dev, ctrl); + + init_completion(&priv->spi_req.completion); + + err =3D device_property_read_u32(&ctrl->dev, "spi,bus-num", &bus_num); + if (!err && bus_num <=3D S16_MAX) + ctrl->bus_num =3D (s16)bus_num; + else + ctrl->bus_num =3D -1; + + virtio_spi_read_config(vdev); + + ctrl->transfer_one =3D virtio_spi_transfer_one; + + err =3D virtio_spi_find_vqs(priv); + if (err) { + dev_err_probe(&vdev->dev, err, "Cannot setup virtqueues\n"); + return err; + } + + err =3D spi_register_controller(ctrl); + if (err) { + dev_err_probe(&vdev->dev, err, "Cannot register controller\n"); + goto err_return; + } + + return 0; + +err_return: + vdev->config->del_vqs(vdev); + return err; +} + +static void virtio_spi_remove(struct virtio_device *vdev) +{ + struct spi_controller *ctrl =3D dev_get_drvdata(&vdev->dev); + + /* Order: 1.) unregister controller, 2.) remove virtqueue */ + spi_unregister_controller(ctrl); + virtio_spi_del_vq(vdev); +} + +static int virtio_spi_freeze(struct virtio_device *vdev) +{ + struct device *dev =3D &vdev->dev; + struct spi_controller *ctrl =3D dev_get_drvdata(dev); + int ret; + + ret =3D spi_controller_suspend(ctrl); + if (ret) { + dev_warn(dev, "cannot suspend controller (%d)\n", ret); + return ret; + } + + virtio_spi_del_vq(vdev); + return 0; +} + +static int virtio_spi_restore(struct virtio_device *vdev) +{ + struct device *dev =3D &vdev->dev; + struct spi_controller *ctrl =3D dev_get_drvdata(dev); + int ret; + + ret =3D virtio_spi_find_vqs(vdev->priv); + if (ret) { + dev_err(dev, "problem starting vqueue (%d)\n", ret); + return ret; + } + + ret =3D spi_controller_resume(ctrl); + if (ret) + dev_err(dev, "problem resuming controller (%d)\n", ret); + + return ret; +} + +static struct virtio_device_id virtio_spi_id_table[] =3D { + { VIRTIO_ID_SPI, VIRTIO_DEV_ANY_ID }, + { 0 }, +}; + +static struct virtio_driver virtio_spi_driver =3D { + .driver.name =3D KBUILD_MODNAME, + .driver.owner =3D THIS_MODULE, + .id_table =3D virtio_spi_id_table, + .probe =3D virtio_spi_probe, + .remove =3D virtio_spi_remove, + .freeze =3D pm_sleep_ptr(virtio_spi_freeze), + .restore =3D pm_sleep_ptr(virtio_spi_restore), +}; + +module_virtio_driver(virtio_spi_driver); +MODULE_DEVICE_TABLE(virtio, virtio_spi_id_table); + +MODULE_AUTHOR("Haixu Cui "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Virtio SPI bus driver"); --=20 2.34.1