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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b31f1258932sm410011a12.64.2025.06.19.17.19.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jun 2025 17:19:26 -0700 (PDT) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, stefan.schmidt@linaro.org, quic_tsoni@quicinc.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org, dmitry.baryshkov@oss.qualcomm.com Subject: [PATCH v5 5/5] thermal: qcom-spmi-temp-alarm: add support for LITE PMIC peripherals Date: Thu, 19 Jun 2025 17:19:18 -0700 Message-Id: <20250620001918.4090853-6-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620001918.4090853-1-anjelique.melendez@oss.qualcomm.com> References: <20250620001918.4090853-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: WkLvI9wT3xFcRs3BICD2M14d8wIUeECD X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjIwMDAwMCBTYWx0ZWRfX/eKgEWRyuPRR 3B9N9og/1ugqJD63nnRs2vYvpzoQw618M3ibwqm6fO3QM9GpcEyY9sWz8yjgIxuOZqfGjJ1NiUn urWfKNScsnQq4LJIFTN32FBC7PckskGHnYoZysD2+14vIEgbx5UnA3SSUHB1s6KR92F3SknAfFt dDYUvKgvnUILGZLjE8fa7ekW1utWGQ5zLpeq+io8lojJYMkkNJcbCPf3EBC6BRS9PMCXJm88Kn5 DrYYSNF9H3QQaEfocwv2RaYKIV3/NF3Xb/qxVNBfDgSzJbqYLaku4APYwc8Xr1FJUjnvn/ThRM5 jABY8VygCB4ORngP59Y7iknlHSyfocAHXr//xbeJZD5Bk0OvFHkiaAo1X1B6CJ1tqvnQjV68c4o LGdC65n7KU+OkpMo3Regiedfs2KBcYJrMMySoS7l9H3Z1t8YJRmff4J0wEC+g1nuTKiSmiSo X-Authority-Analysis: v=2.4 cv=UL/dHDfy c=1 sm=1 tr=0 ts=6854a911 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=6IFa9wvqVegA:10 a=EUspDBNiAAAA:8 a=rhdsTsYyw6L1dzp8dgcA:9 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-GUID: WkLvI9wT3xFcRs3BICD2M14d8wIUeECD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-19_08,2025-06-18_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 phishscore=0 mlxlogscore=999 malwarescore=0 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506200000 Content-Type: text/plain; charset="utf-8" Add support for TEMP_ALARM LITE PMIC peripherals. This subtype utilizes a pair of registers to configure a warning interrupt threshold temperature and an automatic hardware shutdown threshold temperature. Signed-off-by: David Collins Signed-off-by: Anjelique Melendez Reviewed-by: Dmitry Baryshkov --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 208 +++++++++++++++++++- 1 file changed, 207 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/= qcom/qcom-spmi-temp-alarm.c index 0e0b0a8b2367..71310f67f59a 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -23,6 +23,7 @@ #define QPNP_TM_REG_TYPE 0x04 #define QPNP_TM_REG_SUBTYPE 0x05 #define QPNP_TM_REG_STATUS 0x08 +#define QPNP_TM_REG_IRQ_STATUS 0x10 #define QPNP_TM_REG_SHUTDOWN_CTRL1 0x40 #define QPNP_TM_REG_ALARM_CTRL 0x46 =20 @@ -30,14 +31,20 @@ #define QPNP_TM_REG_TEMP_DAC_STG1 0x47 #define QPNP_TM_REG_TEMP_DAC_STG2 0x48 #define QPNP_TM_REG_TEMP_DAC_STG3 0x49 +#define QPNP_TM_REG_LITE_TEMP_CFG1 0x50 +#define QPNP_TM_REG_LITE_TEMP_CFG2 0x51 =20 #define QPNP_TM_TYPE 0x09 #define QPNP_TM_SUBTYPE_GEN1 0x08 #define QPNP_TM_SUBTYPE_GEN2 0x09 +#define QPNP_TM_SUBTYPE_LITE 0xC0 =20 #define STATUS_GEN1_STAGE_MASK GENMASK(1, 0) #define STATUS_GEN2_STATE_MASK GENMASK(6, 4) =20 +/* IRQ status only needed for TEMP_ALARM_LITE */ +#define IRQ_STATUS_MASK BIT(0) + #define SHUTDOWN_CTRL1_OVERRIDE_S2 BIT(6) #define SHUTDOWN_CTRL1_THRESHOLD_MASK GENMASK(1, 0) =20 @@ -45,6 +52,8 @@ =20 #define ALARM_CTRL_FORCE_ENABLE BIT(7) =20 +#define LITE_TEMP_CFG_THRESHOLD_MASK GENMASK(3, 2) + #define THRESH_COUNT 4 #define STAGE_COUNT 3 =20 @@ -89,6 +98,19 @@ static const long temp_dac_max[STAGE_COUNT] =3D { 119375, 159375, 159375 }; =20 +/* + * TEMP_ALARM_LITE has two stages: warning and shutdown with independently + * configured threshold temperatures. + */ + +static const long temp_lite_warning_map[THRESH_COUNT] =3D { + 115000, 125000, 135000, 145000 +}; + +static const long temp_lite_shutdown_map[THRESH_COUNT] =3D { + 135000, 145000, 160000, 175000 +}; + /* Temperature in Milli Celsius reported during stage 0 if no ADC is prese= nt */ #define DEFAULT_TEMP 37000 =20 @@ -196,6 +218,24 @@ static int qpnp_tm_gen2_get_temp_stage(struct qpnp_tm_= chip *chip) return alarm_state_map[ret]; } =20 +/** + * qpnp_tm_lite_get_temp_stage() - return over-temperature stage + * @chip: Pointer to the qpnp_tm chip + * + * Return: alarm interrupt state on success, or errno on failure. + */ +static int qpnp_tm_lite_get_temp_stage(struct qpnp_tm_chip *chip) +{ + u8 reg =3D 0; + int ret; + + ret =3D qpnp_tm_read(chip, QPNP_TM_REG_IRQ_STATUS, ®); + if (ret < 0) + return ret; + + return reg & IRQ_STATUS_MASK; +} + /* * This function updates the internal temp value based on the * current thermal stage and threshold as well as the previous stage @@ -377,6 +417,98 @@ static const struct thermal_zone_device_ops qpnp_tm_ge= n2_rev2_sensor_ops =3D { .set_trip_temp =3D qpnp_tm_gen2_rev2_set_trip_temp, }; =20 +static int qpnp_tm_lite_set_temp_thresh(struct qpnp_tm_chip *chip, unsigne= d int trip, int temp) +{ + int ret, temp_cfg, i; + const long *temp_map; + u8 reg, thresh; + u16 addr; + + WARN_ON(!mutex_is_locked(&chip->lock)); + + if (trip >=3D STAGE_COUNT) { + dev_err(chip->dev, "invalid TEMP_LITE trip =3D %d\n", trip); + return -EINVAL; + } + + switch (trip) { + case 0: + temp_map =3D temp_lite_warning_map; + addr =3D QPNP_TM_REG_LITE_TEMP_CFG1; + break; + case 1: + /* + * The second trip point is purely in software to facilitate + * a controlled shutdown after the warning threshold is crossed + * but before the automatic hardware shutdown threshold is + * crossed. + */ + return 0; + case 2: + temp_map =3D temp_lite_shutdown_map; + addr =3D QPNP_TM_REG_LITE_TEMP_CFG2; + break; + default: + return 0; + } + + if (temp < temp_map[THRESH_MIN] || temp > temp_map[THRESH_MAX]) { + dev_err(chip->dev, "invalid TEMP_LITE temp =3D %d\n", temp); + return -EINVAL; + } + + thresh =3D 0; + temp_cfg =3D temp_map[thresh]; + for (i =3D THRESH_MAX; i >=3D THRESH_MIN; i--) { + if (temp >=3D temp_map[i]) { + thresh =3D i; + temp_cfg =3D temp_map[i]; + break; + } + } + + if (temp_cfg =3D=3D chip->temp_thresh_map[trip]) + return 0; + + ret =3D qpnp_tm_read(chip, addr, ®); + if (ret < 0) { + dev_err(chip->dev, "LITE_TEMP_CFG read failed, ret=3D%d\n", ret); + return ret; + } + + reg &=3D ~LITE_TEMP_CFG_THRESHOLD_MASK; + reg |=3D FIELD_PREP(LITE_TEMP_CFG_THRESHOLD_MASK, thresh); + + ret =3D qpnp_tm_write(chip, addr, reg); + if (ret < 0) { + dev_err(chip->dev, "LITE_TEMP_CFG write failed, ret=3D%d\n", ret); + return ret; + } + + chip->temp_thresh_map[trip] =3D temp_cfg; + + return 0; +} + +static int qpnp_tm_lite_set_trip_temp(struct thermal_zone_device *tz, + const struct thermal_trip *trip, int temp) +{ + unsigned int trip_index =3D THERMAL_TRIP_PRIV_TO_INT(trip->priv); + struct qpnp_tm_chip *chip =3D thermal_zone_device_priv(tz); + int ret; + + mutex_lock(&chip->lock); + ret =3D qpnp_tm_lite_set_temp_thresh(chip, trip_index, temp); + mutex_unlock(&chip->lock); + + return ret; +} + +static const struct thermal_zone_device_ops qpnp_tm_lite_sensor_ops =3D { + .get_temp =3D qpnp_tm_get_temp, + .set_trip_temp =3D qpnp_tm_lite_set_trip_temp, +}; + static irqreturn_t qpnp_tm_isr(int irq, void *data) { struct qpnp_tm_chip *chip =3D data; @@ -472,6 +604,70 @@ static int qpnp_tm_gen2_rev2_sync_thresholds(struct qp= np_tm_chip *chip) return 0; } =20 +/* Configure TEMP_LITE registers based on DT thermal_zone trips */ +static int qpnp_tm_lite_configure_trip_temps_cb(struct thermal_trip *trip,= void *data) +{ + struct qpnp_tm_chip *chip =3D data; + int ret; + + mutex_lock(&chip->lock); + trip->priv =3D THERMAL_INT_TO_TRIP_PRIV(chip->ntrips); + ret =3D qpnp_tm_lite_set_temp_thresh(chip, chip->ntrips, trip->temperatur= e); + chip->ntrips++; + mutex_unlock(&chip->lock); + + return ret; +} + +static int qpnp_tm_lite_configure_trip_temps(struct qpnp_tm_chip *chip) +{ + int ret; + + ret =3D thermal_zone_for_each_trip(chip->tz_dev, qpnp_tm_lite_configure_t= rip_temps_cb, chip); + if (ret < 0) + return ret; + + /* Verify that trips are strictly increasing. */ + if (chip->temp_thresh_map[2] <=3D chip->temp_thresh_map[0]) { + dev_err(chip->dev, "Threshold 2=3D%ld <=3D threshold 0=3D%ld\n", + chip->temp_thresh_map[2], chip->temp_thresh_map[0]); + return -EINVAL; + } + + return 0; +} + +/* Read the hardware default TEMP_LITE stage threshold temperatures */ +static int qpnp_tm_lite_sync_thresholds(struct qpnp_tm_chip *chip) +{ + int ret, thresh; + u8 reg =3D 0; + + /* + * Store the warning trip temp in temp_thresh_map[0] and the shutdown trip + * temp in temp_thresh_map[2]. The second trip point is purely in softwa= re + * to facilitate a controlled shutdown after the warning threshold is + * crossed but before the automatic hardware shutdown threshold is + * crossed. Thus, there is no register to read for the second trip + * point. + */ + ret =3D qpnp_tm_read(chip, QPNP_TM_REG_LITE_TEMP_CFG1, ®); + if (ret < 0) + return ret; + + thresh =3D FIELD_GET(LITE_TEMP_CFG_THRESHOLD_MASK, reg); + chip->temp_thresh_map[0] =3D temp_lite_warning_map[thresh]; + + ret =3D qpnp_tm_read(chip, QPNP_TM_REG_LITE_TEMP_CFG2, ®); + if (ret < 0) + return ret; + + thresh =3D FIELD_GET(LITE_TEMP_CFG_THRESHOLD_MASK, reg); + chip->temp_thresh_map[2] =3D temp_lite_shutdown_map[thresh]; + + return 0; +} + static const struct spmi_temp_alarm_data spmi_temp_alarm_data =3D { .ops =3D &qpnp_tm_sensor_ops, .temp_map =3D &temp_map_gen1, @@ -503,6 +699,13 @@ static const struct spmi_temp_alarm_data spmi_temp_ala= rm_gen2_rev2_data =3D { .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, }; =20 +static const struct spmi_temp_alarm_data spmi_temp_alarm_lite_data =3D { + .ops =3D &qpnp_tm_lite_sensor_ops, + .sync_thresholds =3D qpnp_tm_lite_sync_thresholds, + .configure_trip_temps =3D qpnp_tm_lite_configure_trip_temps, + .get_temp_stage =3D qpnp_tm_lite_get_temp_stage, +}; + /* * This function intializes the internal temp value based on only the * current thermal stage and threshold. @@ -611,7 +814,8 @@ static int qpnp_tm_probe(struct platform_device *pdev) } =20 if (type !=3D QPNP_TM_TYPE || (subtype !=3D QPNP_TM_SUBTYPE_GEN1 - && subtype !=3D QPNP_TM_SUBTYPE_GEN2)) { + && subtype !=3D QPNP_TM_SUBTYPE_GEN2 + && subtype !=3D QPNP_TM_SUBTYPE_LITE)) { dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n", type, subtype); return -ENODEV; @@ -626,6 +830,8 @@ static int qpnp_tm_probe(struct platform_device *pdev) chip->data =3D &spmi_temp_alarm_gen2_rev1_data; else if (subtype =3D=3D QPNP_TM_SUBTYPE_GEN2) chip->data =3D &spmi_temp_alarm_gen2_data; + else if (subtype =3D=3D QPNP_TM_SUBTYPE_LITE) + chip->data =3D &spmi_temp_alarm_lite_data; else return -ENODEV; =20 --=20 2.34.1