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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b31f1258932sm410011a12.64.2025.06.19.17.19.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jun 2025 17:19:20 -0700 (PDT) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, stefan.schmidt@linaro.org, quic_tsoni@quicinc.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org, dmitry.baryshkov@oss.qualcomm.com Subject: [PATCH v5 1/5] thermal: qcom-spmi-temp-alarm: enable stage 2 shutdown when required Date: Thu, 19 Jun 2025 17:19:14 -0700 Message-Id: <20250620001918.4090853-2-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620001918.4090853-1-anjelique.melendez@oss.qualcomm.com> References: <20250620001918.4090853-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjIwMDAwMCBTYWx0ZWRfXy2N0K10OBDp3 hVUY2d9o2/r6XgjAWqwxPyYvTS0EWRyOrmLFFHc5XRHD9BwKLny2kTky7DA31c6uOhSYxVlC0Tc u49/T+Ef+dLWt7qy3Iwzd6B3SzMr6TZ6kQluhwTXuL6QFnfLpF+k9r22877uKXewwgAi8wZMlOZ 9opz+s1iYvEn0xZ7sJWnyi2lROBZBa/wI3/QqjSyaYbwxCoKutbRb4RawxPUipjcfSPLAHrHXze 63TsGJ3izhAmVdXEFdf+FtBmMLi1o1ZSb+Pr3oowWoeCIW3EprLNKbkzmYmAjhwAFJJ/89Vb4Zd DDCerhKKQjpjxU/bZQvwDeRMlXuOk0EfmJJVVYrs5ndk6seHxZXvn5SZpMFn2XmYchh6Kk6K5ID EKfvC8Q6M4C+loDLVFqj3em/AE16lm+nR8O8fjYw0gJ4sUMTt9+BAVTl+Tg8vof1EPnDmSpS X-Proofpoint-GUID: N_sHw69ubflbeSrIu_o1RzXOl5klCYLt X-Proofpoint-ORIG-GUID: N_sHw69ubflbeSrIu_o1RzXOl5klCYLt X-Authority-Analysis: v=2.4 cv=FrIF/3rq c=1 sm=1 tr=0 ts=6854a90b cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=6IFa9wvqVegA:10 a=EUspDBNiAAAA:8 a=e8SBnR8fKgZMydxn7aMA:9 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-19_08,2025-06-18_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 mlxlogscore=999 bulkscore=0 impostorscore=0 malwarescore=0 phishscore=0 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506200000 Content-Type: text/plain; charset="utf-8" From: David Collins Certain TEMP_ALARM GEN2 PMIC peripherals need over-temperature stage 2 automatic PMIC partial shutdown to be enabled in order to avoid repeated faults in the event of reaching over-temperature stage 3. Modify the stage 2 shutdown control logic to ensure that stage 2 shutdown is enabled on all affected PMICs. Read the digital major and minor revision registers to identify these PMICs. Signed-off-by: David Collins Signed-off-by: Anjelique Melendez --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 32 +++++++++++++++++++-- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/= qcom/qcom-spmi-temp-alarm.c index a81e7d6e865f..47248a843591 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2011-2015, 2017, 2020, The Linux Foundation. All rights r= eserved. + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 #include @@ -16,6 +17,7 @@ =20 #include "../thermal_hwmon.h" =20 +#define QPNP_TM_REG_DIG_MINOR 0x00 #define QPNP_TM_REG_DIG_MAJOR 0x01 #define QPNP_TM_REG_TYPE 0x04 #define QPNP_TM_REG_SUBTYPE 0x05 @@ -78,6 +80,7 @@ struct qpnp_tm_chip { /* protects .thresh, .stage and chip registers */ struct mutex lock; bool initialized; + bool require_s2_shutdown; =20 struct iio_channel *adc; const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; @@ -255,7 +258,7 @@ static int qpnp_tm_update_critical_trip_temp(struct qpn= p_tm_chip *chip, =20 skip: reg |=3D chip->thresh; - if (disable_s2_shutdown) + if (disable_s2_shutdown && !chip->require_s2_shutdown) reg |=3D SHUTDOWN_CTRL1_OVERRIDE_S2; =20 return qpnp_tm_write(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, reg); @@ -350,8 +353,8 @@ static int qpnp_tm_probe(struct platform_device *pdev) { struct qpnp_tm_chip *chip; struct device_node *node; - u8 type, subtype, dig_major; - u32 res; + u8 type, subtype, dig_major, dig_minor; + u32 res, dig_revision; int ret, irq; =20 node =3D pdev->dev.of_node; @@ -402,6 +405,12 @@ static int qpnp_tm_probe(struct platform_device *pdev) return dev_err_probe(&pdev->dev, ret, "could not read dig_major\n"); =20 + ret =3D qpnp_tm_read(chip, QPNP_TM_REG_DIG_MINOR, &dig_minor); + if (ret < 0) { + dev_err(&pdev->dev, "could not read dig_minor\n"); + return ret; + } + if (type !=3D QPNP_TM_TYPE || (subtype !=3D QPNP_TM_SUBTYPE_GEN1 && subtype !=3D QPNP_TM_SUBTYPE_GEN2)) { dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n", @@ -415,6 +424,23 @@ static int qpnp_tm_probe(struct platform_device *pdev) else chip->temp_map =3D &temp_map_gen1; =20 + if (chip->subtype =3D=3D QPNP_TM_SUBTYPE_GEN2) { + dig_revision =3D (dig_major << 8) | dig_minor; + /* + * Check if stage 2 automatic partial shutdown must remain + * enabled to avoid potential repeated faults upon reaching + * over-temperature stage 3. + */ + switch (dig_revision) { + case 0x0001: + case 0x0002: + case 0x0100: + case 0x0101: + chip->require_s2_shutdown =3D true; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b31f1258932sm410011a12.64.2025.06.19.17.19.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jun 2025 17:19:22 -0700 (PDT) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, stefan.schmidt@linaro.org, quic_tsoni@quicinc.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org, dmitry.baryshkov@oss.qualcomm.com Subject: [PATCH v5 2/5] thermal: qcom-spmi-temp-alarm: Add temp alarm data struct based on HW subtype Date: Thu, 19 Jun 2025 17:19:15 -0700 Message-Id: <20250620001918.4090853-3-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620001918.4090853-1-anjelique.melendez@oss.qualcomm.com> References: <20250620001918.4090853-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: Lbmr9ZxcrNI92N3PKlFLTw23J6mlj1Ip X-Authority-Analysis: v=2.4 cv=D6RHKuRj c=1 sm=1 tr=0 ts=6854a90c cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=6IFa9wvqVegA:10 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=P94jSCoFVATTS2qIwVMA:9 a=_Vgx9l1VpLgwpw_dHYaR:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: Lbmr9ZxcrNI92N3PKlFLTw23J6mlj1Ip X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjIwMDAwMCBTYWx0ZWRfX3KQRg6/0mNcI 2b4aT5BGuushvQ6DrYC7n/SuNtrDk4gf2pWm2PxjAIx3/Up/ElBCKZz50nwS/AcQjx5wn3FizVr VA1I4ceWkRF+Zvp1f+kHTJANEVraOLfnnFHZ0lYuqV6iQYMAXexo7gRdVSyyuTLgCFcAPvpJe4K T0K31PxVKrygGV5sD9Fp3KKPCO+i5cN5jG/I0Eo3cFw1uvbWNqqoOksamEH7p/rjtsRVJAW4esK nUVMtuwtAxexdkWDN2ZQlVPqHoYuocft6iU3PTiOX11R+imRNQgbuRk+a2OM0vsIJvOTXPujKru oTBk+n+dkIUTObXnNveFGKJwxJMA0wntlaQoy4f/g+g9bmrATyznDJfoHwKpWB7QQKhoslTIAFX VtmFjVLUemtCKPHFpE8wVx2SfI8ytixDOl1iNTQFm0ZF9NjNjo2PIfCg3JN91j85zAwUVZyA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-19_08,2025-06-18_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 impostorscore=0 phishscore=0 adultscore=0 suspectscore=0 mlxlogscore=999 clxscore=1015 mlxscore=0 lowpriorityscore=0 spamscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506200000 Content-Type: text/plain; charset="utf-8" Currently multiple if/else statements are used in functions to decipher between SPMI temp alarm Gen 1, Gen 2 and Gen 2 Rev 1 functionality. Instead refactor the driver so that SPMI temp alarm chips will have reference to a spmi_temp_alarm_data struct which defines data and function callbacks based on the HW subtype. Signed-off-by: Anjelique Melendez Reviewed-by: Dmitry Baryshkov --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 127 +++++++++++++------- 1 file changed, 81 insertions(+), 46 deletions(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/= qcom/qcom-spmi-temp-alarm.c index 47248a843591..fdabde39a7e5 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -4,6 +4,7 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 +#include #include #include #include @@ -31,7 +32,6 @@ =20 #define STATUS_GEN1_STAGE_MASK GENMASK(1, 0) #define STATUS_GEN2_STATE_MASK GENMASK(6, 4) -#define STATUS_GEN2_STATE_SHIFT 4 =20 #define SHUTDOWN_CTRL1_OVERRIDE_S2 BIT(6) #define SHUTDOWN_CTRL1_THRESHOLD_MASK GENMASK(1, 0) @@ -68,22 +68,29 @@ static const long temp_map_gen2_v1[THRESH_COUNT][STAGE_= COUNT] =3D { /* Temperature in Milli Celsius reported during stage 0 if no ADC is prese= nt */ #define DEFAULT_TEMP 37000 =20 +struct qpnp_tm_chip; + +struct spmi_temp_alarm_data { + const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; + int (*get_temp_stage)(struct qpnp_tm_chip *chip); +}; + struct qpnp_tm_chip { struct regmap *map; struct device *dev; struct thermal_zone_device *tz_dev; + const struct spmi_temp_alarm_data *data; unsigned int subtype; long temp; - unsigned int thresh; unsigned int stage; unsigned int base; /* protects .thresh, .stage and chip registers */ struct mutex lock; bool initialized; bool require_s2_shutdown; + long temp_thresh_map[STAGE_COUNT]; =20 struct iio_channel *adc; - const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; }; =20 /* This array maps from GEN2 alarm state to GEN1 alarm stage */ @@ -117,20 +124,19 @@ static int qpnp_tm_write(struct qpnp_tm_chip *chip, u= 16 addr, u8 data) */ static long qpnp_tm_decode_temp(struct qpnp_tm_chip *chip, unsigned int st= age) { - if (!chip->temp_map || chip->thresh >=3D THRESH_COUNT || stage =3D=3D 0 || - stage > STAGE_COUNT) + if (stage =3D=3D 0 || stage > STAGE_COUNT) return 0; =20 - return (*chip->temp_map)[chip->thresh][stage - 1]; + return chip->temp_thresh_map[stage - 1]; } =20 /** - * qpnp_tm_get_temp_stage() - return over-temperature stage + * qpnp_tm_gen1_get_temp_stage() - return over-temperature stage * @chip: Pointer to the qpnp_tm chip * - * Return: stage (GEN1) or state (GEN2) on success, or errno on failure. + * Return: stage on success, or errno on failure. */ -static int qpnp_tm_get_temp_stage(struct qpnp_tm_chip *chip) +static int qpnp_tm_gen1_get_temp_stage(struct qpnp_tm_chip *chip) { int ret; u8 reg =3D 0; @@ -139,12 +145,27 @@ static int qpnp_tm_get_temp_stage(struct qpnp_tm_chip= *chip) if (ret < 0) return ret; =20 - if (chip->subtype =3D=3D QPNP_TM_SUBTYPE_GEN1) - ret =3D reg & STATUS_GEN1_STAGE_MASK; - else - ret =3D (reg & STATUS_GEN2_STATE_MASK) >> STATUS_GEN2_STATE_SHIFT; + return FIELD_GET(STATUS_GEN1_STAGE_MASK, reg); +} =20 - return ret; +/** + * qpnp_tm_gen2_get_temp_stage() - return over-temperature stage + * @chip: Pointer to the qpnp_tm chip + * + * Return: stage on success, or errno on failure. + */ +static int qpnp_tm_gen2_get_temp_stage(struct qpnp_tm_chip *chip) +{ + u8 reg =3D 0; + int ret; + + ret =3D qpnp_tm_read(chip, QPNP_TM_REG_STATUS, ®); + if (ret < 0) + return ret; + + ret =3D FIELD_GET(STATUS_GEN2_STATE_MASK, reg); + + return alarm_state_map[ret]; } =20 /* @@ -153,23 +174,16 @@ static int qpnp_tm_get_temp_stage(struct qpnp_tm_chip= *chip) */ static int qpnp_tm_update_temp_no_adc(struct qpnp_tm_chip *chip) { - unsigned int stage, stage_new, stage_old; + unsigned int stage_new, stage_old; int ret; =20 WARN_ON(!mutex_is_locked(&chip->lock)); =20 - ret =3D qpnp_tm_get_temp_stage(chip); + ret =3D chip->data->get_temp_stage(chip); if (ret < 0) return ret; - stage =3D ret; - - if (chip->subtype =3D=3D QPNP_TM_SUBTYPE_GEN1) { - stage_new =3D stage; - stage_old =3D chip->stage; - } else { - stage_new =3D alarm_state_map[stage]; - stage_old =3D alarm_state_map[chip->stage]; - } + stage_new =3D ret; + stage_old =3D chip->stage; =20 if (stage_new > stage_old) { /* increasing stage, use lower bound */ @@ -181,7 +195,7 @@ static int qpnp_tm_update_temp_no_adc(struct qpnp_tm_ch= ip *chip) - TEMP_STAGE_HYSTERESIS; } =20 - chip->stage =3D stage; + chip->stage =3D stage_new; =20 return 0; } @@ -221,10 +235,10 @@ static int qpnp_tm_get_temp(struct thermal_zone_devic= e *tz, int *temp) static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip, int temp) { - long stage2_threshold_min =3D (*chip->temp_map)[THRESH_MIN][1]; - long stage2_threshold_max =3D (*chip->temp_map)[THRESH_MAX][1]; + long stage2_threshold_min =3D (*chip->data->temp_map)[THRESH_MIN][1]; + long stage2_threshold_max =3D (*chip->data->temp_map)[THRESH_MAX][1]; bool disable_s2_shutdown =3D false; - u8 reg; + u8 reg, threshold; =20 WARN_ON(!mutex_is_locked(&chip->lock)); =20 @@ -236,17 +250,17 @@ static int qpnp_tm_update_critical_trip_temp(struct q= pnp_tm_chip *chip, =20 if (temp =3D=3D THERMAL_TEMP_INVALID || temp < stage2_threshold_min) { - chip->thresh =3D THRESH_MIN; + threshold =3D THRESH_MIN; goto skip; } =20 if (temp <=3D stage2_threshold_max) { - chip->thresh =3D THRESH_MAX - + threshold =3D THRESH_MAX - ((stage2_threshold_max - temp) / TEMP_THRESH_STEP); disable_s2_shutdown =3D true; } else { - chip->thresh =3D THRESH_MAX; + threshold =3D THRESH_MAX; =20 if (chip->adc) disable_s2_shutdown =3D true; @@ -257,7 +271,9 @@ static int qpnp_tm_update_critical_trip_temp(struct qpn= p_tm_chip *chip, } =20 skip: - reg |=3D chip->thresh; + memcpy(chip->temp_thresh_map, chip->data->temp_map[threshold], + sizeof(chip->temp_thresh_map)); + reg |=3D threshold; if (disable_s2_shutdown && !chip->require_s2_shutdown) reg |=3D SHUTDOWN_CTRL1_OVERRIDE_S2; =20 @@ -294,6 +310,21 @@ static irqreturn_t qpnp_tm_isr(int irq, void *data) return IRQ_HANDLED; } =20 +static const struct spmi_temp_alarm_data spmi_temp_alarm_data =3D { + .temp_map =3D &temp_map_gen1, + .get_temp_stage =3D qpnp_tm_gen1_get_temp_stage, +}; + +static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_data =3D { + .temp_map =3D &temp_map_gen1, + .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, +}; + +static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_rev1_data = =3D { + .temp_map =3D &temp_map_gen2_v1, + .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, +}; + /* * This function initializes the internal temp value based on only the * current thermal stage and threshold. Setup threshold control and @@ -301,10 +332,10 @@ static irqreturn_t qpnp_tm_isr(int irq, void *data) */ static int qpnp_tm_init(struct qpnp_tm_chip *chip) { - unsigned int stage; - int ret; - u8 reg =3D 0; int crit_temp; + u8 threshold; + u8 reg =3D 0; + int ret; =20 mutex_lock(&chip->lock); =20 @@ -312,19 +343,19 @@ static int qpnp_tm_init(struct qpnp_tm_chip *chip) if (ret < 0) goto out; =20 - chip->thresh =3D reg & SHUTDOWN_CTRL1_THRESHOLD_MASK; + threshold =3D reg & SHUTDOWN_CTRL1_THRESHOLD_MASK; + memcpy(chip->temp_thresh_map, chip->data->temp_map[threshold], + sizeof(chip->temp_thresh_map)); + chip->temp =3D DEFAULT_TEMP; =20 - ret =3D qpnp_tm_get_temp_stage(chip); + ret =3D chip->data->get_temp_stage(chip); if (ret < 0) goto out; chip->stage =3D ret; =20 - stage =3D chip->subtype =3D=3D QPNP_TM_SUBTYPE_GEN1 - ? chip->stage : alarm_state_map[chip->stage]; - - if (stage) - chip->temp =3D qpnp_tm_decode_temp(chip, stage); + if (chip->stage) + chip->temp =3D qpnp_tm_decode_temp(chip, chip->stage); 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b31f1258932sm410011a12.64.2025.06.19.17.19.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jun 2025 17:19:23 -0700 (PDT) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, stefan.schmidt@linaro.org, quic_tsoni@quicinc.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org, dmitry.baryshkov@oss.qualcomm.com Subject: [PATCH v5 3/5] thermal: qcom-spmi-temp-alarm: Prepare to support additional Temp Alarm subtypes Date: Thu, 19 Jun 2025 17:19:16 -0700 Message-Id: <20250620001918.4090853-4-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620001918.4090853-1-anjelique.melendez@oss.qualcomm.com> References: <20250620001918.4090853-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: V7TcV5aI6A64_bx-Y1zHroL05a2pB4U9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjIwMDAwMCBTYWx0ZWRfX3RZs1e9olLl/ VpsM4jGDB1zwGrRDBY/BpIRL69KQsxCWOXw5VAuzbiX935TwOAoj4pjLqm7vwWSo2V8ltTPneU1 5DbzmbHunLNVHVNev0uV58LVS4Gib3yebe9s0yF2GM6z7+xjsBcXyQckPbOxXnkXNAF7qbBKEd9 prr0w8uFM5apzJRIQZHbWxaAlWSKV/w/qdgFl8HwqB5VH7hAspFcm0/LCFCfmB3Ma41j+FZVHSo pz4yp8+P9M/c1HlwkV4drbeaWc1Jd7AgNpk6TotZftiNwvzegxlU76XEXGYX57c3R5xGUFJmh48 ySqJMBZzQ7KhPjskouyhmCSNFpQX3amXmib10L/wRlDvdE+je1glO4Ek+KOawADvmjaQ/MMcTAO naEx9WVjdbTf6mAzva4AdxXQeMk9K0QHIs6rXHjaQi/Gb3Yi0CxS4ISfRWr0Glr41L6PnUcH X-Authority-Analysis: v=2.4 cv=UL/dHDfy c=1 sm=1 tr=0 ts=6854a90e cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=6IFa9wvqVegA:10 a=EUspDBNiAAAA:8 a=VcnGJyyLPHPoHGOjSs8A:9 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-GUID: V7TcV5aI6A64_bx-Y1zHroL05a2pB4U9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-19_08,2025-06-18_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 phishscore=0 mlxlogscore=999 malwarescore=0 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506200000 Content-Type: text/plain; charset="utf-8" In preparation to support newer temp alarm subtypes, add the "ops", "sync_thresholds" and "configure_trip_temps" references to spmi_temp_alarm_data. This will allow for each Temp Alarm subtype to define its own thermal_zone_device_ops and properly initialize and configure thermal trip temperature. Signed-off-by: Anjelique Melendez Acked-by: Konrad Dybcio --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 96 ++++++++++++++------- 1 file changed, 67 insertions(+), 29 deletions(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/= qcom/qcom-spmi-temp-alarm.c index fdabde39a7e5..5991067d3484 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -71,8 +71,11 @@ static const long temp_map_gen2_v1[THRESH_COUNT][STAGE_C= OUNT] =3D { struct qpnp_tm_chip; =20 struct spmi_temp_alarm_data { + const struct thermal_zone_device_ops *ops; const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; + int (*sync_thresholds)(struct qpnp_tm_chip *chip); int (*get_temp_stage)(struct qpnp_tm_chip *chip); + int (*configure_trip_temps)(struct qpnp_tm_chip *chip); }; =20 struct qpnp_tm_chip { @@ -310,64 +313,97 @@ static irqreturn_t qpnp_tm_isr(int irq, void *data) return IRQ_HANDLED; } =20 +/* Read the hardware default stage threshold temperatures */ +static int qpnp_tm_sync_thresholds(struct qpnp_tm_chip *chip) +{ + u8 reg, threshold; + int ret; + + ret =3D qpnp_tm_read(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, ®); + if (ret < 0) + return ret; + + threshold =3D reg & SHUTDOWN_CTRL1_THRESHOLD_MASK; + memcpy(chip->temp_thresh_map, chip->data->temp_map[threshold], + sizeof(chip->temp_thresh_map)); + + return ret; +} + +static int qpnp_tm_configure_trip_temp(struct qpnp_tm_chip *chip) +{ + int crit_temp, ret; + + ret =3D thermal_zone_get_crit_temp(chip->tz_dev, &crit_temp); + if (ret) + crit_temp =3D THERMAL_TEMP_INVALID; + + mutex_lock(&chip->lock); + ret =3D qpnp_tm_update_critical_trip_temp(chip, crit_temp); + mutex_unlock(&chip->lock); + + return ret; +} + static const struct spmi_temp_alarm_data spmi_temp_alarm_data =3D { + .ops =3D &qpnp_tm_sensor_ops, .temp_map =3D &temp_map_gen1, + .sync_thresholds =3D qpnp_tm_sync_thresholds, + .configure_trip_temps =3D qpnp_tm_configure_trip_temp, .get_temp_stage =3D qpnp_tm_gen1_get_temp_stage, }; =20 static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_data =3D { + .ops =3D &qpnp_tm_sensor_ops, .temp_map =3D &temp_map_gen1, + .sync_thresholds =3D qpnp_tm_sync_thresholds, + .configure_trip_temps =3D qpnp_tm_configure_trip_temp, .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, }; =20 static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_rev1_data = =3D { + .ops =3D &qpnp_tm_sensor_ops, .temp_map =3D &temp_map_gen2_v1, + .sync_thresholds =3D qpnp_tm_sync_thresholds, + .configure_trip_temps =3D qpnp_tm_configure_trip_temp, .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, }; =20 /* - * This function initializes the internal temp value based on only the - * current thermal stage and threshold. Setup threshold control and - * disable shutdown override. + * This function intializes the internal temp value based on only the + * current thermal stage and threshold. */ -static int qpnp_tm_init(struct qpnp_tm_chip *chip) +static int qpnp_tm_threshold_init(struct qpnp_tm_chip *chip) { - int crit_temp; - u8 threshold; - u8 reg =3D 0; int ret; =20 - mutex_lock(&chip->lock); - - ret =3D qpnp_tm_read(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, ®); + ret =3D chip->data->sync_thresholds(chip); if (ret < 0) - goto out; - - threshold =3D reg & SHUTDOWN_CTRL1_THRESHOLD_MASK; - memcpy(chip->temp_thresh_map, chip->data->temp_map[threshold], - sizeof(chip->temp_thresh_map)); - - chip->temp =3D DEFAULT_TEMP; + return ret; =20 ret =3D chip->data->get_temp_stage(chip); if (ret < 0) - goto out; + return ret; chip->stage =3D ret; + chip->temp =3D DEFAULT_TEMP; =20 if (chip->stage) chip->temp =3D qpnp_tm_decode_temp(chip, chip->stage); =20 - mutex_unlock(&chip->lock); - - ret =3D thermal_zone_get_crit_temp(chip->tz_dev, &crit_temp); - if (ret) - crit_temp =3D THERMAL_TEMP_INVALID; + return ret; +} =20 - mutex_lock(&chip->lock); +/* + * This function intalizes threshold control and disables shutdown overrid= e. + */ +static int qpnp_tm_init(struct qpnp_tm_chip *chip) +{ + int ret; + u8 reg =3D 0; =20 - ret =3D qpnp_tm_update_critical_trip_temp(chip, crit_temp); + ret =3D chip->data->configure_trip_temps(chip); if (ret < 0) - goto out; + return ret; =20 /* Enable the thermal alarm PMIC module in always-on mode. */ reg =3D ALARM_CTRL_FORCE_ENABLE; @@ -375,8 +411,6 @@ static int qpnp_tm_init(struct qpnp_tm_chip *chip) =20 chip->initialized =3D true; =20 -out: - mutex_unlock(&chip->lock); return ret; } =20 @@ -476,13 +510,17 @@ static int qpnp_tm_probe(struct platform_device *pdev) } } =20 + ret =3D qpnp_tm_threshold_init(chip); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "threshold init failed\n"); + /* * Register the sensor before initializing the hardware to be able to * read the trip points. get_temp() returns the default temperature * before the hardware initialization is completed. */ chip->tz_dev =3D devm_thermal_of_zone_register( - &pdev->dev, 0, chip, &qpnp_tm_sensor_ops); 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b31f1258932sm410011a12.64.2025.06.19.17.19.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jun 2025 17:19:25 -0700 (PDT) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, stefan.schmidt@linaro.org, quic_tsoni@quicinc.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org, dmitry.baryshkov@oss.qualcomm.com Subject: [PATCH v5 4/5] thermal: qcom-spmi-temp-alarm: add support for GEN2 rev 2 PMIC peripherals Date: Thu, 19 Jun 2025 17:19:17 -0700 Message-Id: <20250620001918.4090853-5-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620001918.4090853-1-anjelique.melendez@oss.qualcomm.com> References: <20250620001918.4090853-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjIwMDAwMCBTYWx0ZWRfX91qsQMY7x/FB 3w/bWVMLD8P40BZc4yHf0XyTPskDjlS6kK1qvUvszpcm2rzjY0xW2LDvcmMV9Nwyitehzd+h1kd Dn7dHP0KdBO9l7KkvIMi0ayRqeUIdizszlkKg9Gp3rqUWkdtVeqGe4TXNXhgB7wWR1VwILvXyoo uvHyRK/D3gd+AEbHlN9XmATiB5fj8/ewjs5vqvbod1vQgdK0JGZGBbZ5/uG7iZRFcCsxDolw1bO w74NAEBdW5mD5Z6O+PX83XqqDw+GW3XZhAlHGCjmX23HnSCi85n41hROvWLwZy/Q1h77UKWI3DY xtsQXPSMBKkPa58gCsMk2IDYjKyoXzIx9oLND+EnQvnLRRSX1BdZ0+mCzb0eJanij3si1qN6y91 GbFRz4MPJ3/BC0PpJuP3ZuuRPjzI+NOYr9cD6TwTAiLpujV/ifnacM/1RWIxP5+aVgYq29DX X-Proofpoint-GUID: XKN_JZDlt7dztZYAwhDo7s_pyCo2jNhR X-Authority-Analysis: v=2.4 cv=btJMBFai c=1 sm=1 tr=0 ts=6854a90f cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=6IFa9wvqVegA:10 a=EUspDBNiAAAA:8 a=N9IR0GguogMVy2wE49AA:9 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-ORIG-GUID: XKN_JZDlt7dztZYAwhDo7s_pyCo2jNhR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-19_08,2025-06-18_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 adultscore=0 lowpriorityscore=0 mlxscore=0 suspectscore=0 clxscore=1015 malwarescore=0 spamscore=0 mlxlogscore=999 bulkscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506200000 Content-Type: text/plain; charset="utf-8" Add support for TEMP_ALARM GEN2 PMIC peripherals with digital major revision 2. This revision utilizes individual temp DAC registers to set the threshold temperature for over-temperature stages 1 (warning), 2 (system shutdown), and 3 (emergency shutdown) instead of a single register to specify a set of thresholds. Signed-off-by: David Collins Signed-off-by: Anjelique Melendez --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 136 ++++++++++++++++++++ 1 file changed, 136 insertions(+) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/= qcom/qcom-spmi-temp-alarm.c index 5991067d3484..0e0b0a8b2367 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -26,6 +26,11 @@ #define QPNP_TM_REG_SHUTDOWN_CTRL1 0x40 #define QPNP_TM_REG_ALARM_CTRL 0x46 =20 +/* TEMP_DAC_STGx registers are only present for TEMP_GEN2 v2.0 */ +#define QPNP_TM_REG_TEMP_DAC_STG1 0x47 +#define QPNP_TM_REG_TEMP_DAC_STG2 0x48 +#define QPNP_TM_REG_TEMP_DAC_STG3 0x49 + #define QPNP_TM_TYPE 0x09 #define QPNP_TM_SUBTYPE_GEN1 0x08 #define QPNP_TM_SUBTYPE_GEN2 0x09 @@ -65,6 +70,25 @@ static const long temp_map_gen2_v1[THRESH_COUNT][STAGE_C= OUNT] =3D { =20 #define TEMP_STAGE_HYSTERESIS 2000 =20 +/* + * For TEMP_GEN2 v2.0, TEMP_DAC_STG1/2/3 registers are used to set the thr= eshold + * for each stage independently. + * TEMP_DAC_STG* =3D 0 --> 80 C + * Each 8 step increase in TEMP_DAC_STG* value corresponds to 5 C (5000 mC= ). + */ +#define TEMP_DAC_MIN 80000 +#define TEMP_DAC_SCALE_NUM 8 +#define TEMP_DAC_SCALE_DEN 5000 + +#define TEMP_DAC_TEMP_TO_REG(temp) \ + (((temp) - TEMP_DAC_MIN) * TEMP_DAC_SCALE_NUM / TEMP_DAC_SCALE_DEN) +#define TEMP_DAC_REG_TO_TEMP(reg) \ + (TEMP_DAC_MIN + (reg) * TEMP_DAC_SCALE_DEN / TEMP_DAC_SCALE_NUM) + +static const long temp_dac_max[STAGE_COUNT] =3D { + 119375, 159375, 159375 +}; + /* Temperature in Milli Celsius reported during stage 0 if no ADC is prese= nt */ #define DEFAULT_TEMP 37000 =20 @@ -87,6 +111,7 @@ struct qpnp_tm_chip { long temp; unsigned int stage; unsigned int base; + unsigned int ntrips; /* protects .thresh, .stage and chip registers */ struct mutex lock; bool initialized; @@ -304,6 +329,54 @@ static const struct thermal_zone_device_ops qpnp_tm_se= nsor_ops =3D { .set_trip_temp =3D qpnp_tm_set_trip_temp, }; =20 +static int qpnp_tm_gen2_rev2_set_temp_thresh(struct qpnp_tm_chip *chip, un= signed int trip, int temp) +{ + int ret, temp_cfg; + u8 reg; + + WARN_ON(!mutex_is_locked(&chip->lock)); + + if (trip >=3D STAGE_COUNT) { + dev_err(chip->dev, "invalid TEMP_DAC trip =3D %d\n", trip); + return -EINVAL; + } else if (temp < TEMP_DAC_MIN || temp > temp_dac_max[trip]) { + dev_err(chip->dev, "invalid TEMP_DAC temp =3D %d\n", temp); + return -EINVAL; + } + + reg =3D TEMP_DAC_TEMP_TO_REG(temp); + temp_cfg =3D TEMP_DAC_REG_TO_TEMP(reg); + + ret =3D qpnp_tm_write(chip, QPNP_TM_REG_TEMP_DAC_STG1 + trip, reg); + if (ret < 0) { + dev_err(chip->dev, "TEMP_DAC_STG write failed, ret=3D%d\n", ret); + return ret; + } + + chip->temp_thresh_map[trip] =3D temp_cfg; + + return 0; +} + +static int qpnp_tm_gen2_rev2_set_trip_temp(struct thermal_zone_device *tz, + const struct thermal_trip *trip, int temp) +{ + unsigned int trip_index =3D THERMAL_TRIP_PRIV_TO_INT(trip->priv); + struct qpnp_tm_chip *chip =3D thermal_zone_device_priv(tz); + int ret; + + mutex_lock(&chip->lock); + ret =3D qpnp_tm_gen2_rev2_set_temp_thresh(chip, trip_index, temp); + mutex_unlock(&chip->lock); + + return ret; +} + +static const struct thermal_zone_device_ops qpnp_tm_gen2_rev2_sensor_ops = =3D { + .get_temp =3D qpnp_tm_get_temp, + .set_trip_temp =3D qpnp_tm_gen2_rev2_set_trip_temp, +}; + static irqreturn_t qpnp_tm_isr(int irq, void *data) { struct qpnp_tm_chip *chip =3D data; @@ -345,6 +418,60 @@ static int qpnp_tm_configure_trip_temp(struct qpnp_tm_= chip *chip) return ret; } =20 +/* Configure TEMP_DAC registers based on DT thermal_zone trips */ +static int qpnp_tm_gen2_rev2_configure_trip_temps_cb(struct thermal_trip *= trip, void *data) +{ + struct qpnp_tm_chip *chip =3D data; + int ret; + + mutex_lock(&chip->lock); + trip->priv =3D THERMAL_INT_TO_TRIP_PRIV(chip->ntrips); + ret =3D qpnp_tm_gen2_rev2_set_temp_thresh(chip, chip->ntrips, trip->tempe= rature); + chip->ntrips++; + mutex_unlock(&chip->lock); + + return ret; +} + +static int qpnp_tm_gen2_rev2_configure_trip_temps(struct qpnp_tm_chip *chi= p) +{ + int ret, i; + + ret =3D thermal_zone_for_each_trip(chip->tz_dev, + qpnp_tm_gen2_rev2_configure_trip_temps_cb, chip); + if (ret < 0) + return ret; + + /* Verify that trips are strictly increasing. */ + for (i =3D 1; i < STAGE_COUNT; i++) { + if (chip->temp_thresh_map[i] <=3D chip->temp_thresh_map[i - 1]) { + dev_err(chip->dev, "Threshold %d=3D%ld <=3D threshold %d=3D%ld\n", + i, chip->temp_thresh_map[i], i - 1, + chip->temp_thresh_map[i - 1]); + return -EINVAL; + } + } + + return 0; +} + +/* Read the hardware default TEMP_DAC stage threshold temperatures */ +static int qpnp_tm_gen2_rev2_sync_thresholds(struct qpnp_tm_chip *chip) +{ + int ret, i; + u8 reg =3D 0; + + for (i =3D 0; i < STAGE_COUNT; i++) { + ret =3D qpnp_tm_read(chip, QPNP_TM_REG_TEMP_DAC_STG1 + i, ®); + if (ret < 0) + return ret; + + chip->temp_thresh_map[i] =3D TEMP_DAC_REG_TO_TEMP(reg); + } + + return 0; +} + static const struct spmi_temp_alarm_data spmi_temp_alarm_data =3D { .ops =3D &qpnp_tm_sensor_ops, .temp_map =3D &temp_map_gen1, @@ -369,6 +496,13 @@ static const struct spmi_temp_alarm_data spmi_temp_ala= rm_gen2_rev1_data =3D { .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, }; =20 +static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_rev2_data = =3D { + .ops =3D &qpnp_tm_gen2_rev2_sensor_ops, + .sync_thresholds =3D qpnp_tm_gen2_rev2_sync_thresholds, + .configure_trip_temps =3D qpnp_tm_gen2_rev2_configure_trip_temps, + .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, +}; + /* * This function intializes the internal temp value based on only the * current thermal stage and threshold. @@ -486,6 +620,8 @@ static int qpnp_tm_probe(struct platform_device *pdev) chip->subtype =3D subtype; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b31f1258932sm410011a12.64.2025.06.19.17.19.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jun 2025 17:19:26 -0700 (PDT) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, stefan.schmidt@linaro.org, quic_tsoni@quicinc.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org, dmitry.baryshkov@oss.qualcomm.com Subject: [PATCH v5 5/5] thermal: qcom-spmi-temp-alarm: add support for LITE PMIC peripherals Date: Thu, 19 Jun 2025 17:19:18 -0700 Message-Id: <20250620001918.4090853-6-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620001918.4090853-1-anjelique.melendez@oss.qualcomm.com> References: <20250620001918.4090853-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: WkLvI9wT3xFcRs3BICD2M14d8wIUeECD X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjIwMDAwMCBTYWx0ZWRfX/eKgEWRyuPRR 3B9N9og/1ugqJD63nnRs2vYvpzoQw618M3ibwqm6fO3QM9GpcEyY9sWz8yjgIxuOZqfGjJ1NiUn urWfKNScsnQq4LJIFTN32FBC7PckskGHnYoZysD2+14vIEgbx5UnA3SSUHB1s6KR92F3SknAfFt dDYUvKgvnUILGZLjE8fa7ekW1utWGQ5zLpeq+io8lojJYMkkNJcbCPf3EBC6BRS9PMCXJm88Kn5 DrYYSNF9H3QQaEfocwv2RaYKIV3/NF3Xb/qxVNBfDgSzJbqYLaku4APYwc8Xr1FJUjnvn/ThRM5 jABY8VygCB4ORngP59Y7iknlHSyfocAHXr//xbeJZD5Bk0OvFHkiaAo1X1B6CJ1tqvnQjV68c4o LGdC65n7KU+OkpMo3Regiedfs2KBcYJrMMySoS7l9H3Z1t8YJRmff4J0wEC+g1nuTKiSmiSo X-Authority-Analysis: v=2.4 cv=UL/dHDfy c=1 sm=1 tr=0 ts=6854a911 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=6IFa9wvqVegA:10 a=EUspDBNiAAAA:8 a=rhdsTsYyw6L1dzp8dgcA:9 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-GUID: WkLvI9wT3xFcRs3BICD2M14d8wIUeECD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-19_08,2025-06-18_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 phishscore=0 mlxlogscore=999 malwarescore=0 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506200000 Content-Type: text/plain; charset="utf-8" Add support for TEMP_ALARM LITE PMIC peripherals. This subtype utilizes a pair of registers to configure a warning interrupt threshold temperature and an automatic hardware shutdown threshold temperature. Signed-off-by: David Collins Signed-off-by: Anjelique Melendez Reviewed-by: Dmitry Baryshkov --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 208 +++++++++++++++++++- 1 file changed, 207 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/= qcom/qcom-spmi-temp-alarm.c index 0e0b0a8b2367..71310f67f59a 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -23,6 +23,7 @@ #define QPNP_TM_REG_TYPE 0x04 #define QPNP_TM_REG_SUBTYPE 0x05 #define QPNP_TM_REG_STATUS 0x08 +#define QPNP_TM_REG_IRQ_STATUS 0x10 #define QPNP_TM_REG_SHUTDOWN_CTRL1 0x40 #define QPNP_TM_REG_ALARM_CTRL 0x46 =20 @@ -30,14 +31,20 @@ #define QPNP_TM_REG_TEMP_DAC_STG1 0x47 #define QPNP_TM_REG_TEMP_DAC_STG2 0x48 #define QPNP_TM_REG_TEMP_DAC_STG3 0x49 +#define QPNP_TM_REG_LITE_TEMP_CFG1 0x50 +#define QPNP_TM_REG_LITE_TEMP_CFG2 0x51 =20 #define QPNP_TM_TYPE 0x09 #define QPNP_TM_SUBTYPE_GEN1 0x08 #define QPNP_TM_SUBTYPE_GEN2 0x09 +#define QPNP_TM_SUBTYPE_LITE 0xC0 =20 #define STATUS_GEN1_STAGE_MASK GENMASK(1, 0) #define STATUS_GEN2_STATE_MASK GENMASK(6, 4) =20 +/* IRQ status only needed for TEMP_ALARM_LITE */ +#define IRQ_STATUS_MASK BIT(0) + #define SHUTDOWN_CTRL1_OVERRIDE_S2 BIT(6) #define SHUTDOWN_CTRL1_THRESHOLD_MASK GENMASK(1, 0) =20 @@ -45,6 +52,8 @@ =20 #define ALARM_CTRL_FORCE_ENABLE BIT(7) =20 +#define LITE_TEMP_CFG_THRESHOLD_MASK GENMASK(3, 2) + #define THRESH_COUNT 4 #define STAGE_COUNT 3 =20 @@ -89,6 +98,19 @@ static const long temp_dac_max[STAGE_COUNT] =3D { 119375, 159375, 159375 }; =20 +/* + * TEMP_ALARM_LITE has two stages: warning and shutdown with independently + * configured threshold temperatures. + */ + +static const long temp_lite_warning_map[THRESH_COUNT] =3D { + 115000, 125000, 135000, 145000 +}; + +static const long temp_lite_shutdown_map[THRESH_COUNT] =3D { + 135000, 145000, 160000, 175000 +}; + /* Temperature in Milli Celsius reported during stage 0 if no ADC is prese= nt */ #define DEFAULT_TEMP 37000 =20 @@ -196,6 +218,24 @@ static int qpnp_tm_gen2_get_temp_stage(struct qpnp_tm_= chip *chip) return alarm_state_map[ret]; } =20 +/** + * qpnp_tm_lite_get_temp_stage() - return over-temperature stage + * @chip: Pointer to the qpnp_tm chip + * + * Return: alarm interrupt state on success, or errno on failure. + */ +static int qpnp_tm_lite_get_temp_stage(struct qpnp_tm_chip *chip) +{ + u8 reg =3D 0; + int ret; + + ret =3D qpnp_tm_read(chip, QPNP_TM_REG_IRQ_STATUS, ®); + if (ret < 0) + return ret; + + return reg & IRQ_STATUS_MASK; +} + /* * This function updates the internal temp value based on the * current thermal stage and threshold as well as the previous stage @@ -377,6 +417,98 @@ static const struct thermal_zone_device_ops qpnp_tm_ge= n2_rev2_sensor_ops =3D { .set_trip_temp =3D qpnp_tm_gen2_rev2_set_trip_temp, }; =20 +static int qpnp_tm_lite_set_temp_thresh(struct qpnp_tm_chip *chip, unsigne= d int trip, int temp) +{ + int ret, temp_cfg, i; + const long *temp_map; + u8 reg, thresh; + u16 addr; + + WARN_ON(!mutex_is_locked(&chip->lock)); + + if (trip >=3D STAGE_COUNT) { + dev_err(chip->dev, "invalid TEMP_LITE trip =3D %d\n", trip); + return -EINVAL; + } + + switch (trip) { + case 0: + temp_map =3D temp_lite_warning_map; + addr =3D QPNP_TM_REG_LITE_TEMP_CFG1; + break; + case 1: + /* + * The second trip point is purely in software to facilitate + * a controlled shutdown after the warning threshold is crossed + * but before the automatic hardware shutdown threshold is + * crossed. + */ + return 0; + case 2: + temp_map =3D temp_lite_shutdown_map; + addr =3D QPNP_TM_REG_LITE_TEMP_CFG2; + break; + default: + return 0; + } + + if (temp < temp_map[THRESH_MIN] || temp > temp_map[THRESH_MAX]) { + dev_err(chip->dev, "invalid TEMP_LITE temp =3D %d\n", temp); + return -EINVAL; + } + + thresh =3D 0; + temp_cfg =3D temp_map[thresh]; + for (i =3D THRESH_MAX; i >=3D THRESH_MIN; i--) { + if (temp >=3D temp_map[i]) { + thresh =3D i; + temp_cfg =3D temp_map[i]; + break; + } + } + + if (temp_cfg =3D=3D chip->temp_thresh_map[trip]) + return 0; + + ret =3D qpnp_tm_read(chip, addr, ®); + if (ret < 0) { + dev_err(chip->dev, "LITE_TEMP_CFG read failed, ret=3D%d\n", ret); + return ret; + } + + reg &=3D ~LITE_TEMP_CFG_THRESHOLD_MASK; + reg |=3D FIELD_PREP(LITE_TEMP_CFG_THRESHOLD_MASK, thresh); + + ret =3D qpnp_tm_write(chip, addr, reg); + if (ret < 0) { + dev_err(chip->dev, "LITE_TEMP_CFG write failed, ret=3D%d\n", ret); + return ret; + } + + chip->temp_thresh_map[trip] =3D temp_cfg; + + return 0; +} + +static int qpnp_tm_lite_set_trip_temp(struct thermal_zone_device *tz, + const struct thermal_trip *trip, int temp) +{ + unsigned int trip_index =3D THERMAL_TRIP_PRIV_TO_INT(trip->priv); + struct qpnp_tm_chip *chip =3D thermal_zone_device_priv(tz); + int ret; + + mutex_lock(&chip->lock); + ret =3D qpnp_tm_lite_set_temp_thresh(chip, trip_index, temp); + mutex_unlock(&chip->lock); + + return ret; +} + +static const struct thermal_zone_device_ops qpnp_tm_lite_sensor_ops =3D { + .get_temp =3D qpnp_tm_get_temp, + .set_trip_temp =3D qpnp_tm_lite_set_trip_temp, +}; + static irqreturn_t qpnp_tm_isr(int irq, void *data) { struct qpnp_tm_chip *chip =3D data; @@ -472,6 +604,70 @@ static int qpnp_tm_gen2_rev2_sync_thresholds(struct qp= np_tm_chip *chip) return 0; } =20 +/* Configure TEMP_LITE registers based on DT thermal_zone trips */ +static int qpnp_tm_lite_configure_trip_temps_cb(struct thermal_trip *trip,= void *data) +{ + struct qpnp_tm_chip *chip =3D data; + int ret; + + mutex_lock(&chip->lock); + trip->priv =3D THERMAL_INT_TO_TRIP_PRIV(chip->ntrips); + ret =3D qpnp_tm_lite_set_temp_thresh(chip, chip->ntrips, trip->temperatur= e); + chip->ntrips++; + mutex_unlock(&chip->lock); + + return ret; +} + +static int qpnp_tm_lite_configure_trip_temps(struct qpnp_tm_chip *chip) +{ + int ret; + + ret =3D thermal_zone_for_each_trip(chip->tz_dev, qpnp_tm_lite_configure_t= rip_temps_cb, chip); + if (ret < 0) + return ret; + + /* Verify that trips are strictly increasing. */ + if (chip->temp_thresh_map[2] <=3D chip->temp_thresh_map[0]) { + dev_err(chip->dev, "Threshold 2=3D%ld <=3D threshold 0=3D%ld\n", + chip->temp_thresh_map[2], chip->temp_thresh_map[0]); + return -EINVAL; + } + + return 0; +} + +/* Read the hardware default TEMP_LITE stage threshold temperatures */ +static int qpnp_tm_lite_sync_thresholds(struct qpnp_tm_chip *chip) +{ + int ret, thresh; + u8 reg =3D 0; + + /* + * Store the warning trip temp in temp_thresh_map[0] and the shutdown trip + * temp in temp_thresh_map[2]. The second trip point is purely in softwa= re + * to facilitate a controlled shutdown after the warning threshold is + * crossed but before the automatic hardware shutdown threshold is + * crossed. Thus, there is no register to read for the second trip + * point. + */ + ret =3D qpnp_tm_read(chip, QPNP_TM_REG_LITE_TEMP_CFG1, ®); + if (ret < 0) + return ret; + + thresh =3D FIELD_GET(LITE_TEMP_CFG_THRESHOLD_MASK, reg); + chip->temp_thresh_map[0] =3D temp_lite_warning_map[thresh]; + + ret =3D qpnp_tm_read(chip, QPNP_TM_REG_LITE_TEMP_CFG2, ®); + if (ret < 0) + return ret; + + thresh =3D FIELD_GET(LITE_TEMP_CFG_THRESHOLD_MASK, reg); + chip->temp_thresh_map[2] =3D temp_lite_shutdown_map[thresh]; + + return 0; +} + static const struct spmi_temp_alarm_data spmi_temp_alarm_data =3D { .ops =3D &qpnp_tm_sensor_ops, .temp_map =3D &temp_map_gen1, @@ -503,6 +699,13 @@ static const struct spmi_temp_alarm_data spmi_temp_ala= rm_gen2_rev2_data =3D { .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, }; =20 +static const struct spmi_temp_alarm_data spmi_temp_alarm_lite_data =3D { + .ops =3D &qpnp_tm_lite_sensor_ops, + .sync_thresholds =3D qpnp_tm_lite_sync_thresholds, + .configure_trip_temps =3D qpnp_tm_lite_configure_trip_temps, + .get_temp_stage =3D qpnp_tm_lite_get_temp_stage, +}; + /* * This function intializes the internal temp value based on only the * current thermal stage and threshold. @@ -611,7 +814,8 @@ static int qpnp_tm_probe(struct platform_device *pdev) } =20 if (type !=3D QPNP_TM_TYPE || (subtype !=3D QPNP_TM_SUBTYPE_GEN1 - && subtype !=3D QPNP_TM_SUBTYPE_GEN2)) { + && subtype !=3D QPNP_TM_SUBTYPE_GEN2 + && subtype !=3D QPNP_TM_SUBTYPE_LITE)) { dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n", type, subtype); return -ENODEV; @@ -626,6 +830,8 @@ static int qpnp_tm_probe(struct platform_device *pdev) chip->data =3D &spmi_temp_alarm_gen2_rev1_data; else if (subtype =3D=3D QPNP_TM_SUBTYPE_GEN2) chip->data =3D &spmi_temp_alarm_gen2_data; + else if (subtype =3D=3D QPNP_TM_SUBTYPE_LITE) + chip->data =3D &spmi_temp_alarm_lite_data; else return -ENODEV; =20 --=20 2.34.1