From nobody Thu Oct 9 06:34:08 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C968928B7DF; Thu, 19 Jun 2025 17:30:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750354214; cv=none; b=Bbxq05f44zkH9DtbiwnKc5BSgMRun8BTDPIEXyr0Bu/PuLsrp+5g7ts07IJeX6hJq0JN4TydOK8U/+y03B6CNEZCUqZqsdsAsWs/M1swPGdNk4FY1d9ROvezR86mTG39cELOGvUy20xRPU8zJAycBu2rJM0d5dQtURTekD5XCE0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750354214; c=relaxed/simple; bh=q6nrjT2Dpercv5DoePpH+dBXKOMzG9sjRP9CjTTCRFQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=sTRUcDEg5/eKZ7VUGg9rZ8LbcKlEkPY4L27yeOapWZyWKIrSBWCP/7yla8GNyz4jLAR9e8GSCeGbCfmukGwBhpEQqo4ey1TdQeLb/rz9Bico5HVMZ6Qn68dH8tpqEvWQhKussnNVDCjGOjjop5YYCeIFMjY8l9x0x/duxW/IWFg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pT9Ouj/J; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pT9Ouj/J" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 369AEC4CEEA; Thu, 19 Jun 2025 17:30:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750354214; bh=q6nrjT2Dpercv5DoePpH+dBXKOMzG9sjRP9CjTTCRFQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pT9Ouj/JeTRfyA+9Nv+N2klirdDENDpWxZMDFqGzbQzxJaKbewkF05a1GUWrJ4NUq ziWjJqcoKvIbVk83Ze0XqjdkJUHZ8o+oUuKy60SZQBlHeEGeQfKrL7iJRbHgg2xD8M XucpkGHYAe3h0hvGC5VL0wzZkYVmNChU20yFmqIxpf9s9OTICKf9ZYPBhrO6e76hoZ /xQPRGr5YrkdZg5P/JI64s6arkvyCF6Pm/hVTRR2W3hS0IeG1dMmThtlOTPAAiI42i rZ82WhiFUPnM2cMdv3rVz2CwAj9f6NXXrkyqxdobNI0rPPHOS8eX4QuUuZNULVSpc+ cS/y5yZtL3Q9A== Received: by wens.tw (Postfix, from userid 1000) id 1BFD85FE81; Fri, 20 Jun 2025 01:30:12 +0800 (CST) From: Chen-Yu Tsai To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH 1/5] dt-bindings: arm: sunxi: Add Xunlong OrangePi 4A board Date: Fri, 20 Jun 2025 01:30:03 +0800 Message-Id: <20250619173007.3367034-2-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250619173007.3367034-1-wens@kernel.org> References: <20250619173007.3367034-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The OrangePi 4A is a typical Raspberry Pi model B sized development board from Xunlong designed around an Allwinner T527 SoC. Add its compatible name to the list of valid ones. Signed-off-by: Chen-Yu Tsai Acked-by: Conor Dooley Reviewed-by: Andre Przywara --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentati= on/devicetree/bindings/arm/sunxi.yaml index 7807ea613258..c41d0a0b89e6 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -996,6 +996,11 @@ properties: - const: xunlong,orangepi-3 - const: allwinner,sun50i-h6 =20 + - description: Xunlong OrangePi 4A + items: + - const: xunlong,orangepi-4a + - const: allwinner,sun55i-t527 + - description: Xunlong OrangePi Lite items: - const: xunlong,orangepi-lite --=20 2.39.5 From nobody Thu Oct 9 06:34:08 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0057923C8D3; Thu, 19 Jun 2025 17:30:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750354215; cv=none; b=XdVjuHRBti9EcfXsEDsNG5CodjRQMBSthWD5bb63H54guM8kKwQudG34HwijRnDI6yh/1p6tMcJvgkliYZGmDGj/Upo+L1vELm2isLwkafz7fUJuaJUly9AcP+FAKV5w5qNogmdP6zqvHh70eFjuaBVoYAi9cI0O+JG6dVA7+FE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750354215; c=relaxed/simple; bh=wCB6x+x+rj6RDpHRZY4HD76LxIfQ6M7f4ACdL/qmmIg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=S9orCDDm/HtGWMgkxPbVbUCQeA54aPn6ndfUrysc0WaTA+ZGW2r7OcfcEkHBpOa+cV2kbxlW/pFhD0HGqnEcb+F+5ywcr12Y9yffZo11d4ISb8cd2pasK6GDcpafGAC7htbmu+lJHK5UStFqB7sFqMoBr4nwqK23L2WThR2XagI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=LbGvVzdH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="LbGvVzdH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 661DDC4CEF2; Thu, 19 Jun 2025 17:30:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750354214; bh=wCB6x+x+rj6RDpHRZY4HD76LxIfQ6M7f4ACdL/qmmIg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LbGvVzdHbUtWcUe5zogrNMWHrikLfYW7CiqIm9magQRZamU51Bz3bIPrs08YON8eY MsAoHl/0ZxMBtYfxmP6gpDhQOGriw/kmXXA70phtpov5VunsRmNKxK4LpDzO9J2KUs muXcN51nqvp3hfBVBnrahfk9Gno1ozMskt+/8FJJ4jA0KU9FJFIWA01jg2PbsHs2Wh V/39gC/0Kv1CkQi7eqNEp9DzlEj4Gv+wDi3nvH9DXvJbZMK24FRalFsKC+9lm0myg0 NUKXryWBH3zpxt1b8vE1r7Gc9VOjGliFOeYVzmI2oosATVZhuPMWY7aYCoTHzIxCut dFUoH07Ie8DmQ== Received: by wens.tw (Postfix, from userid 1000) id 23E095FF4F; Fri, 20 Jun 2025 01:30:12 +0800 (CST) From: Chen-Yu Tsai To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH 2/5] arm64: dts: allwinner: a523: Move mmc nodes to correct position Date: Fri, 20 Jun 2025 01:30:04 +0800 Message-Id: <20250619173007.3367034-3-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250619173007.3367034-1-wens@kernel.org> References: <20250619173007.3367034-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai When the mmc nodes were added to the dtsi file, they were inserted in the incorrect position. Move them to the correct place. Signed-off-by: Chen-Yu Tsai Reviewed-by: Andre Przywara --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 126 +++++++++--------- 1 file changed, 63 insertions(+), 63 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index 8b7cbc2e78f5..458d7ecedacd 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -181,69 +181,6 @@ ccu: clock-controller@2001000 { #reset-cells =3D <1>; }; =20 - mmc0: mmc@4020000 { - compatible =3D "allwinner,sun55i-a523-mmc", - "allwinner,sun20i-d1-mmc"; - reg =3D <0x04020000 0x1000>; - clocks =3D <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; - clock-names =3D "ahb", "mmc"; - resets =3D <&ccu RST_BUS_MMC0>; - reset-names =3D "ahb"; - interrupts =3D ; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&mmc0_pins>; - status =3D "disabled"; - - max-frequency =3D <150000000>; - cap-sd-highspeed; - cap-mmc-highspeed; - cap-sdio-irq; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - - mmc1: mmc@4021000 { - compatible =3D "allwinner,sun55i-a523-mmc", - "allwinner,sun20i-d1-mmc"; - reg =3D <0x04021000 0x1000>; - clocks =3D <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; - clock-names =3D "ahb", "mmc"; - resets =3D <&ccu RST_BUS_MMC1>; - reset-names =3D "ahb"; - interrupts =3D ; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&mmc1_pins>; - status =3D "disabled"; - - max-frequency =3D <150000000>; - cap-sd-highspeed; - cap-mmc-highspeed; - cap-sdio-irq; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - - mmc2: mmc@4022000 { - compatible =3D "allwinner,sun55i-a523-mmc", - "allwinner,sun20i-d1-mmc"; - reg =3D <0x04022000 0x1000>; - clocks =3D <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; - clock-names =3D "ahb", "mmc"; - resets =3D <&ccu RST_BUS_MMC2>; - reset-names =3D "ahb"; - interrupts =3D ; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&mmc2_pins>; - status =3D "disabled"; - - max-frequency =3D <150000000>; - cap-sd-highspeed; - cap-mmc-highspeed; - cap-sdio-irq; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - wdt: watchdog@2050000 { compatible =3D "allwinner,sun55i-a523-wdt"; reg =3D <0x2050000 0x20>; @@ -449,6 +386,69 @@ its: msi-controller@3440000 { }; }; =20 + mmc0: mmc@4020000 { + compatible =3D "allwinner,sun55i-a523-mmc", + "allwinner,sun20i-d1-mmc"; + reg =3D <0x04020000 0x1000>; + clocks =3D <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names =3D "ahb", "mmc"; + resets =3D <&ccu RST_BUS_MMC0>; + reset-names =3D "ahb"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmc0_pins>; + status =3D "disabled"; + + max-frequency =3D <150000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + cap-sdio-irq; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mmc1: mmc@4021000 { + compatible =3D "allwinner,sun55i-a523-mmc", + "allwinner,sun20i-d1-mmc"; + reg =3D <0x04021000 0x1000>; + clocks =3D <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names =3D "ahb", "mmc"; + resets =3D <&ccu RST_BUS_MMC1>; + reset-names =3D "ahb"; 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charset="utf-8" From: Chen-Yu Tsai Nodes are supposed to be sorted by address, or if no addresses apply, by node name. The rgmii0 pins are out of order, possibly due to multiple patches adding pin mux settings conflicting. Move the rgmii0 pins to the correct location. Signed-off-by: Chen-Yu Tsai Reviewed-by: Andre Przywara --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index 458d7ecedacd..30613a0b1124 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -126,16 +126,6 @@ pio: pinctrl@2000000 { interrupt-controller; #interrupt-cells =3D <3>; =20 - rgmii0_pins: rgmii0-pins { - pins =3D "PH0", "PH1", "PH2", "PH3", "PH4", - "PH5", "PH6", "PH7", "PH9", "PH10", - "PH14", "PH15", "PH16", "PH17", "PH18"; - allwinner,pinmux =3D <5>; - function =3D "emac0"; - drive-strength =3D <40>; - bias-disable; - }; - mmc0_pins: mmc0-pins { pins =3D "PF0" ,"PF1", "PF2", "PF3", "PF4", "PF5"; allwinner,pinmux =3D <2>; @@ -163,6 +153,16 @@ mmc2_pins: mmc2-pins { bias-pull-up; }; =20 + rgmii0_pins: rgmii0-pins { + pins =3D "PH0", "PH1", "PH2", "PH3", "PH4", + "PH5", "PH6", "PH7", "PH9", "PH10", + "PH14", "PH15", "PH16", "PH17", "PH18"; + allwinner,pinmux =3D <5>; + function =3D "emac0"; + drive-strength =3D <40>; + bias-disable; + }; + uart0_pb_pins: uart0-pb-pins { pins =3D "PB9", "PB10"; allwinner,pinmux =3D <2>; --=20 2.39.5 From nobody Thu Oct 9 06:34:08 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C961D241CB7; Thu, 19 Jun 2025 17:30:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750354214; cv=none; b=o5dlCJTUQ644s2vgdgSx5kDwRlYBihZeuA00jlEZVteNaIraJJbWdlQbYjVfo85iXnujBFJz2pCFLbdM96lA4auD1boWrm5rGJ+skirq6sE3mVZn9mkeRiynLlOaJBfvNqc1vyM6q6nYKuwCLNyXYhNgRLyDAHxc6qI1gFcXK44= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750354214; c=relaxed/simple; bh=rz1gZsh7A4S3qN6IuAlTDtQuCkgP2vb88SwwNf0Nq2U=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=PxDQWiCeuYZqEnzNTlErXPVdYUbbWyv58WoOewbRGqFwHx644fguvTGKkdzP68W+HKYgLnXgXoofJwfTuMSOlQX6qs9sibcnLN1bfM5YfAQVCS4p1nT77z2srIoqHxfUv851yCqHtoLY6SOpfHhqdxRP3ZY0lcq7CmqnCNdO6Dw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dlYkaJ3O; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dlYkaJ3O" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5BD7EC4AF09; Thu, 19 Jun 2025 17:30:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750354214; bh=rz1gZsh7A4S3qN6IuAlTDtQuCkgP2vb88SwwNf0Nq2U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dlYkaJ3OTDpwCeKrBYMhpeu+Ctm4JFHWkf4GpF969PbSB+fdQ3tpM18wnHtoc8KjY xAYlT47yv+7DfOgDuEysznix7QLCwPW+4LnFwKlu0/2rKeYy8Btu1J8CmbhbaLXLcb 3GQJRKhKaq7YU/2u0mvxiqcs7E75AIF22W2k7exrZp22dLt8chij53y1xkf+Y+Nrfh 9uNVBG2mAqgVY6D5jOU7xJJ5U60M18PmHR0JRCYCpVMJC/oE7isV96yFpIXPNY7wKe 5MbaAbfFAwoipZgGPgfT9WX5lqyCaFBa6/JcpOBj83DIyEYhx8syjhkfOpoTPw0OY9 RAQpn3zhGs2bA== Received: by wens.tw (Postfix, from userid 1000) id 3703F5FFF4; Fri, 20 Jun 2025 01:30:12 +0800 (CST) From: Chen-Yu Tsai To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH 4/5] arm64: dts: allwinner: a523: Add UART1 pins Date: Fri, 20 Jun 2025 01:30:06 +0800 Message-Id: <20250619173007.3367034-5-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250619173007.3367034-1-wens@kernel.org> References: <20250619173007.3367034-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai UART1 is normally used to connect to the Bluetooth side of a Broadcom WiFi+BT combo chip. The connection uses 4 pins. Add pinmux nodes for UART1, one for the RX/TX pins, and one for the RTS/CTS pins. Signed-off-by: Chen-Yu Tsai Reviewed-by: Andre Przywara --- arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index 30613a0b1124..6f62201fd739 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -168,6 +168,20 @@ uart0_pb_pins: uart0-pb-pins { allwinner,pinmux =3D <2>; function =3D "uart0"; }; + + /omit-if-no-ref/ + uart1_pins: uart1-pins { + pins =3D "PG6", "PG7"; + function =3D "uart1"; + allwinner,pinmux =3D <2>; + }; + + /omit-if-no-ref/ + uart1_rts_cts_pins: uart1-rts-cts-pins { + pins =3D "PG8", "PG9"; + function =3D "uart1"; + allwinner,pinmux =3D <2>; + }; }; =20 ccu: clock-controller@2001000 { --=20 2.39.5 From nobody Thu Oct 9 06:34:08 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05E6828F94E; Thu, 19 Jun 2025 17:30:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750354217; cv=none; b=BImYlUdHCXt5t567udb+oGtUVHxTxXApT4C9dcs6ULYQHbln/vNbPxsgI32F2yTGTXhcyrG56CIreVjm6A00X7UmohP3bVy7fVMlKMa5ba9dZ5PHjolJCux7p3WKkoKctWNN23ZjvZmt7scmCO2QB1LVS7fOAw0KG/6V7DqbQeA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750354217; c=relaxed/simple; bh=8qN3ZWTgWx6RQQNb7WkxIy/wj+YIJ7Mkr+3TW7ilrvo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=u5nmHNLNxwqiN/bFTynhYBBIRdu89k8XxUUa8C+YNpdL5IJmvWDHI8IsVCbkUA1mG5Iay1036tAikS0a52K7xCckmlspOaAae0G3hlPD48zX/oVay2C/HzxGeMoqAVsKV2QDPfQMo8iiBcgregpUjtZztHZ0EuQKkshDrre7hMA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XYEltRB7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XYEltRB7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8995AC4CEED; Thu, 19 Jun 2025 17:30:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750354216; bh=8qN3ZWTgWx6RQQNb7WkxIy/wj+YIJ7Mkr+3TW7ilrvo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XYEltRB7LR8oIdO4EIZXbS8brVFUGLsfxH3Ib2litRT2FXROnKKyFI2BrLy4kksk+ 4YZJtcZnpT/eGQsUs8qcjMJteXHZhHw+NuNhEeNIghZTW+KswVxD+9L/f9tinVpED6 e4lJ2gaA1dlRgJeDb+zEEO4IhJvGcQeR73hjyUcYWoDjQOJYFWKMrDwnTRPUB5Wp4O Zw8SrrQS+1uy3/718qb2SbgU7/QLydtaCR4J5A6Cutl38nIjUnN5Z+H3E8ZEOOAs17 ihNHFswdy14Vk0hge41UQ2hGbTHnIF5R/see86t5PY1+s5OI1ANeA46yNnrZcqUhM+ 8arqND0syJRpQ== Received: by wens.tw (Postfix, from userid 1000) id 3FE655FFF5; Fri, 20 Jun 2025 01:30:12 +0800 (CST) From: Chen-Yu Tsai To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH 5/5] arm64: dts: allwinner: t527: Add OrangePi 4A board Date: Fri, 20 Jun 2025 01:30:07 +0800 Message-Id: <20250619173007.3367034-6-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250619173007.3367034-1-wens@kernel.org> References: <20250619173007.3367034-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The OrangePi 4A is a typical Raspberry Pi model B sized development board from Xunlong designed around an Allwinner T527 SoC. The board has the following features: - Allwinner T527 SoC - AXP717B + AXP323 PMICs - Up to 4GB LPDDR4 DRAM - micro SD slot - optional eMMC module - M.2 slot for PCIe 2.0 x1 - 16 MB SPI-NOR flash - 4x USB 2.0 type-A ports (one can be used in gadget mode) - 1x Gigabit ethernet w/ Motorcomm PHY (through yet to be supported GMAC200) - 3.5mm audio jack via internal audio codec - HDMI 2.0 output - eDP, MIPI CSI (2-lane and 4-lane) and MIPI DSI (4-lane) connectors - USB type-C port purely for power - AP6256 (Broadcom BCM4345) WiFi 5.0 + BT 5.0 - unsoldered headers for ADC and an additional USB 2.0 host port - 40-pin GPIO header Add a device tree for it, enabling all peripherals currently supported. Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../dts/allwinner/sun55i-t527-orangepi-4a.dts | 378 ++++++++++++++++++ 2 files changed, 379 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.d= ts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/a= llwinner/Makefile index 773cc02a13d0..780aeba0f3a4 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -57,3 +57,4 @@ dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h700-anbernic-rg35xx= -sp.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun55i-a527-cubie-a5e.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun55i-h728-x96qpro+.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun55i-t527-avaota-a1.dtb +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun55i-t527-orangepi-4a.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/ar= ch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts new file mode 100644 index 000000000000..8a62607e584c --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts @@ -0,0 +1,378 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Copyright (C) 2025 Chen-Yu Tsai + */ + +/dts-v1/; + +#include "sun55i-a523.dtsi" + +#include +#include + +/ { + model =3D "OrangePi 4A"; + compatible =3D "xunlong,orangepi-4a", "allwinner,sun55i-t527"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + ext_osc32k: ext-osc32k-clk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <32768>; + clock-output-names =3D "ext_osc32k"; + }; + + leds { + compatible =3D "gpio-leds"; + + /* PWM capable pin, but PWM isn't supported yet. */ + led { + function =3D LED_FUNCTION_STATUS; + color =3D ; + gpios =3D <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */ + }; + }; + + wifi_pwrseq: pwrseq { + compatible =3D "mmc-pwrseq-simple"; + reset-gpios =3D <&r_pio 1 1 GPIO_ACTIVE_LOW>; /* PM1 */ + clocks =3D <&rtc CLK_OSC32K_FANOUT>; + clock-names =3D "ext_clock"; + }; + + reg_otg_vbus: regulator-otg-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "otg-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <®_vcc5v>; + gpio =3D <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ + enable-active-high; + }; + + reg_pcie_vcc3v3: regulator-pcie-vcc3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-pcie-3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <®_vcc5v>; + gpio =3D <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ + enable-active-high; + }; + + reg_usb_vbus: regulator-usb-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "usb-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <®_vcc5v>; + gpio =3D <&r_pio 0 12 GPIO_ACTIVE_HIGH>; /* PL12 */ + enable-active-high; + }; + + reg_vcc5v: regulator-vcc5v { + /* board wide 5V supply from USB type-C port */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-5v"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + }; +}; + +&ehci0 { + status =3D "okay"; +}; + +&ehci1 { + status =3D "okay"; +}; + +&mmc0 { + vmmc-supply =3D <®_cldo3>; + cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ + bus-width =3D <4>; + status =3D "okay"; +}; + +&mmc1 { + bus-width =3D <4>; + mmc-pwrseq =3D <&wifi_pwrseq>; + non-removable; + vmmc-supply =3D <®_dldo1_323>; + vqmmc-supply =3D <®_bldo1>; + status =3D "okay"; + + brcmf: wifi@1 { + compatible =3D "brcm,bcm4329-fmac"; + reg =3D <1>; + interrupt-parent =3D <&r_pio>; + interrupts =3D <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */ + interrupt-names =3D "host-wake"; + }; +}; + +&mmc2 { + bus-width =3D <8>; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + vmmc-supply =3D <®_cldo3>; + vqmmc-supply =3D <®_cldo1>; + status =3D "okay"; +}; + +&ohci0 { + status =3D "okay"; +}; + +&ohci1 { + status =3D "okay"; +}; + +&pio { + vcc-pb-supply =3D <®_cldo3>; /* via VCC-IO */ + vcc-pc-supply =3D <®_cldo1>; + vcc-pd-supply =3D <®_cldo3>; + vcc-pe-supply =3D <®_aldo2>; + vcc-pf-supply =3D <®_cldo3>; /* VCC-IO for 3.3v; VCC-MCSI for 1.8v */ + vcc-pg-supply =3D <®_bldo1>; + vcc-ph-supply =3D <®_cldo3>; /* via VCC-IO */ + vcc-pi-supply =3D <®_cldo3>; + vcc-pj-supply =3D <®_cldo1>; + vcc-pk-supply =3D <®_cldo1>; +}; + +&r_i2c0 { + status =3D "okay"; + + axp717: pmic@35 { + compatible =3D "x-powers,axp717"; + reg =3D <0x35>; + interrupt-controller; + #interrupt-cells =3D <1>; + interrupts-extended =3D <&nmi_intc 0 IRQ_TYPE_LEVEL_LOW>; + + vin1-supply =3D <®_vcc5v>; + vin2-supply =3D <®_vcc5v>; + vin3-supply =3D <®_vcc5v>; + vin4-supply =3D <®_vcc5v>; + aldoin-supply =3D <®_vcc5v>; + bldoin-supply =3D <®_vcc5v>; + cldoin-supply =3D <®_vcc5v>; + + regulators { + /* Supplies the "little" cluster (1.4 GHz cores) */ + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1160000>; + regulator-name =3D "vdd-cpul"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt =3D <920000>; + regulator-max-microvolt =3D <920000>; + regulator-name =3D "vdd-gpu-sys"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt =3D <1160000>; + regulator-max-microvolt =3D <1160000>; + regulator-name =3D "vcc-dram"; + }; + + reg_dcdc4: dcdc4 { + /* feeds 3.3V pin on GPIO header */ + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vdd-io"; + }; + + reg_aldo1: aldo1 { + regulator-name =3D "avdd-csi"; + }; + + reg_aldo2: aldo2 { + regulator-name =3D "vcc-pe"; + }; + + reg_aldo3: aldo3 { + /* supplies the I2C pins for this PMIC */ + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-pl-usb"; + }; + + reg_aldo4: aldo4 { + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-pll-dxco-avcc"; + }; + + reg_bldo1: bldo1 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-pg-wifi"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-pm-lpddr"; + }; + + reg_bldo3: bldo3 { + regulator-name =3D "dvdd-csi"; + }; + + reg_bldo4: bldo4 { + /* not connected */ + }; + + reg_cldo1: cldo1 { + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-cvp-pc-lvds-mcsi-pk-efuse-pcie-edp-1v8"; + }; + + reg_cldo2: cldo2 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc3v3-csi"; + }; + + reg_cldo3: cldo3 { + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-io-mmc-nand-pd-pi-usb"; + }; + + reg_cldo4: cldo4 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-3v3-phy1-lcd"; + }; + + reg_cpusldo: cpusldo { + /* supplies the management core */ + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdd-cpus"; + }; + }; + }; + + axp323: pmic@36 { + compatible =3D "x-powers,axp323"; + reg =3D <0x36>; + #interrupt-cells =3D <1>; + interrupt-controller; + status =3D "okay"; + + vin1-supply =3D <®_vcc5v>; + vin2-supply =3D <®_vcc5v>; + vin3-supply =3D <®_vcc5v>; + + regulators { + reg_aldo1_323: aldo1 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-wifi"; + }; + + reg_dldo1_323: dldo1 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-wifi2"; + }; + + /* Supplies the "big" cluster (1.8 GHz cores) */ + reg_dcdc1_323: dcdc1 { + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1150000>; + regulator-name =3D "vdd-cpub"; + }; + + /* DCDC2 is polyphased with DCDC1 */ + + /* Some RISC-V management core related voltage */ + reg_dcdc3_323: dcdc3 { + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdd-dnr"; + }; + }; + }; +}; + +&r_pio { +/* + * Specifying the supply would create a circular dependency. + * + * vcc-pl-supply =3D <®_aldo3>; + */ + vcc-pm-supply =3D <®_bldo2>; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_pb_pins>; + status =3D "okay"; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status =3D "okay"; + + bluetooth { + compatible =3D "brcm,bcm4345c5"; + clocks =3D <&rtc CLK_OSC32K_FANOUT>; + clock-names =3D "lpo"; + vbat-supply =3D <®_aldo1_323>; + vddio-supply =3D <®_bldo1>; + device-wakeup-gpios =3D <&r_pio 1 3 GPIO_ACTIVE_HIGH>; /* PM3 */ + host-wakeup-gpios =3D <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */ + shutdown-gpios =3D <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ + }; +}; + +&usb_otg { + /* + * The OTG controller is connected to one of the type-A ports. + * There is a regulator, controlled by a GPIO, to provide VBUS power + * to the port, and a VBUSDET GPIO, to detect externally provided + * power. But without ID or CC pins there is no real way to do a + * runtime role detection. + */ + dr_mode =3D "host"; + status =3D "okay"; +}; + +&usbphy { + usb0_vbus-supply =3D <®_otg_vbus>; + usb0_vbus_det-gpios =3D <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ + usb1_vbus-supply =3D <®_usb_vbus>; + status =3D "okay"; +}; --=20 2.39.5