From nobody Thu Oct 9 08:50:41 2025 Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BBCE2417F2 for ; Thu, 19 Jun 2025 12:56:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.190 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750337771; cv=none; b=DXVrLkN3/6oqiLJ8Sn+WxJcaUDhrxzcZ4WlzuzoUEj968gNqwWZ7Gb2ezh1Mc4LNxnFL2AJoh3O8RLpWQIggOe35SNRDDuiMNRFxTHbgpIztuR6VYcIppHeJL9lSz8oqE/4xf7DVLi9NZDt0RcgUqQe9NwCXtLnmeyp05CoHEss= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750337771; c=relaxed/simple; bh=n9Zjkea1/hAIe2WMs4AZZP5u24xKYRiquJ8wdVUn1h0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jWrnhZ9pIxYJM49hgese7Uxu1E7dQ61qMxmzn79i3qznvg1Yr2uLJTePT1v30AW2kCIA9k+oM36lFXFfjb4QEFdA2la7GJeETK6C42OBnUMjUcPRXmVBOoIcIEXJu7sy+bP6hdlv06WfCbrpFobzeTsm+VsdsCrvMnqAYGoIyRI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.190 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.44]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4bNL965hQQz2CffQ; Thu, 19 Jun 2025 20:52:10 +0800 (CST) Received: from dggemv705-chm.china.huawei.com (unknown [10.3.19.32]) by mail.maildlp.com (Postfix) with ESMTPS id B1107140123; Thu, 19 Jun 2025 20:56:05 +0800 (CST) Received: from kwepemq200018.china.huawei.com (7.202.195.108) by dggemv705-chm.china.huawei.com (10.3.19.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Thu, 19 Jun 2025 20:56:05 +0800 Received: from localhost.localdomain (10.50.165.33) by kwepemq200018.china.huawei.com (7.202.195.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Thu, 19 Jun 2025 20:56:04 +0800 From: Yicong Yang To: , , , CC: , , , , , Subject: [RESEND PATCH v3 3/8] drivers/perf: hisi: Use ACPI driver_data to retrieve SLLC PMU information Date: Thu, 19 Jun 2025 20:55:52 +0800 Message-ID: <20250619125557.57372-4-yangyicong@huawei.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20250619125557.57372-1-yangyicong@huawei.com> References: <20250619125557.57372-1-yangyicong@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To kwepemq200018.china.huawei.com (7.202.195.108) Content-Type: text/plain; charset="utf-8" From: Junhao He Make use of struct acpi_device_id::driver_data for version specific information rather than judge the version register. This will help to simplify the probe process and also a bit easier for extension. Factor out SLLC register definition to struct hisi_sllc_pmu_regs. No functional changes intended. Reviewed-by: Jonathan Cameron Signed-off-by: Junhao He Signed-off-by: Yicong Yang --- drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c | 178 ++++++++++++------ 1 file changed, 118 insertions(+), 60 deletions(-) diff --git a/drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c b/drivers/perf/h= isilicon/hisi_uncore_sllc_pmu.c index dbd079016fc4..79327639ec17 100644 --- a/drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c @@ -41,6 +41,7 @@ #define SLLC_SRCID_CMD_SHIFT 1 #define SLLC_SRCID_MSK_SHIFT 12 #define SLLC_NR_EVENTS 0x80 +#define SLLC_EVENT_CNTn(cnt0, n) ((cnt0) + (n) * 8) =20 HISI_PMU_EVENT_ATTR_EXTRACTOR(tgtid_min, config1, 10, 0); HISI_PMU_EVENT_ATTR_EXTRACTOR(tgtid_max, config1, 21, 11); @@ -48,6 +49,23 @@ HISI_PMU_EVENT_ATTR_EXTRACTOR(srcid_cmd, config1, 32, 22= ); HISI_PMU_EVENT_ATTR_EXTRACTOR(srcid_msk, config1, 43, 33); HISI_PMU_EVENT_ATTR_EXTRACTOR(tracetag_en, config1, 44, 44); =20 +struct hisi_sllc_pmu_regs { + u32 int_mask; + u32 int_clear; + u32 int_status; + u32 perf_ctrl; + u32 srcid_ctrl; + u32 srcid_cmd_shift; + u32 srcid_mask_shift; + u32 tgtid_ctrl; + u32 tgtid_min_shift; + u32 tgtid_max_shift; + u32 event_ctrl; + u32 event_type0; + u32 version; + u32 event_cnt0; +}; + static bool tgtid_is_valid(u32 max, u32 min) { return max > 0 && max >=3D min; @@ -56,96 +74,104 @@ static bool tgtid_is_valid(u32 max, u32 min) static void hisi_sllc_pmu_enable_tracetag(struct perf_event *event) { struct hisi_pmu *sllc_pmu =3D to_hisi_pmu(event->pmu); + struct hisi_sllc_pmu_regs *regs =3D sllc_pmu->dev_info->private; u32 tt_en =3D hisi_get_tracetag_en(event); =20 if (tt_en) { u32 val; =20 - val =3D readl(sllc_pmu->base + SLLC_PERF_CTRL); + val =3D readl(sllc_pmu->base + regs->perf_ctrl); val |=3D SLLC_TRACETAG_EN | SLLC_FILT_EN; - writel(val, sllc_pmu->base + SLLC_PERF_CTRL); + writel(val, sllc_pmu->base + regs->perf_ctrl); } } =20 static void hisi_sllc_pmu_disable_tracetag(struct perf_event *event) { struct hisi_pmu *sllc_pmu =3D to_hisi_pmu(event->pmu); + struct hisi_sllc_pmu_regs *regs =3D sllc_pmu->dev_info->private; u32 tt_en =3D hisi_get_tracetag_en(event); =20 if (tt_en) { u32 val; =20 - val =3D readl(sllc_pmu->base + SLLC_PERF_CTRL); + val =3D readl(sllc_pmu->base + regs->perf_ctrl); val &=3D ~(SLLC_TRACETAG_EN | SLLC_FILT_EN); - writel(val, sllc_pmu->base + SLLC_PERF_CTRL); + writel(val, sllc_pmu->base + regs->perf_ctrl); } } =20 static void hisi_sllc_pmu_config_tgtid(struct perf_event *event) { struct hisi_pmu *sllc_pmu =3D to_hisi_pmu(event->pmu); + struct hisi_sllc_pmu_regs *regs =3D sllc_pmu->dev_info->private; u32 min =3D hisi_get_tgtid_min(event); u32 max =3D hisi_get_tgtid_max(event); =20 if (tgtid_is_valid(max, min)) { - u32 val =3D (max << SLLC_TGTID_MAX_SHIFT) | (min << SLLC_TGTID_MIN_SHIFT= ); + u32 val =3D (max << regs->tgtid_max_shift) | + (min << regs->tgtid_min_shift); =20 - writel(val, sllc_pmu->base + SLLC_TGTID_CTRL); + writel(val, sllc_pmu->base + regs->tgtid_ctrl); /* Enable the tgtid */ - val =3D readl(sllc_pmu->base + SLLC_PERF_CTRL); + val =3D readl(sllc_pmu->base + regs->perf_ctrl); val |=3D SLLC_TGTID_EN | SLLC_FILT_EN; - writel(val, sllc_pmu->base + SLLC_PERF_CTRL); + writel(val, sllc_pmu->base + regs->perf_ctrl); } } =20 static void hisi_sllc_pmu_clear_tgtid(struct perf_event *event) { struct hisi_pmu *sllc_pmu =3D to_hisi_pmu(event->pmu); + struct hisi_sllc_pmu_regs *regs =3D sllc_pmu->dev_info->private; u32 min =3D hisi_get_tgtid_min(event); u32 max =3D hisi_get_tgtid_max(event); =20 if (tgtid_is_valid(max, min)) { u32 val; =20 - writel(SLLC_TGTID_NONE, sllc_pmu->base + SLLC_TGTID_CTRL); + writel(SLLC_TGTID_NONE, sllc_pmu->base + regs->tgtid_ctrl); /* Disable the tgtid */ - val =3D readl(sllc_pmu->base + SLLC_PERF_CTRL); + val =3D readl(sllc_pmu->base + regs->perf_ctrl); val &=3D ~(SLLC_TGTID_EN | SLLC_FILT_EN); - writel(val, sllc_pmu->base + SLLC_PERF_CTRL); + writel(val, sllc_pmu->base + regs->perf_ctrl); } } =20 static void hisi_sllc_pmu_config_srcid(struct perf_event *event) { struct hisi_pmu *sllc_pmu =3D to_hisi_pmu(event->pmu); + struct hisi_sllc_pmu_regs *regs =3D sllc_pmu->dev_info->private; u32 cmd =3D hisi_get_srcid_cmd(event); =20 if (cmd) { u32 val, msk; =20 msk =3D hisi_get_srcid_msk(event); - val =3D (cmd << SLLC_SRCID_CMD_SHIFT) | (msk << SLLC_SRCID_MSK_SHIFT); - writel(val, sllc_pmu->base + SLLC_SRCID_CTRL); + val =3D (cmd << regs->srcid_cmd_shift) | + (msk << regs->srcid_mask_shift); + writel(val, sllc_pmu->base + regs->srcid_ctrl); /* Enable the srcid */ - val =3D readl(sllc_pmu->base + SLLC_PERF_CTRL); + val =3D readl(sllc_pmu->base + regs->perf_ctrl); val |=3D SLLC_SRCID_EN | SLLC_FILT_EN; - writel(val, sllc_pmu->base + SLLC_PERF_CTRL); + writel(val, sllc_pmu->base + regs->perf_ctrl); } } =20 static void hisi_sllc_pmu_clear_srcid(struct perf_event *event) { struct hisi_pmu *sllc_pmu =3D to_hisi_pmu(event->pmu); + struct hisi_sllc_pmu_regs *regs =3D sllc_pmu->dev_info->private; u32 cmd =3D hisi_get_srcid_cmd(event); =20 if (cmd) { u32 val; =20 - writel(SLLC_SRCID_NONE, sllc_pmu->base + SLLC_SRCID_CTRL); + writel(SLLC_SRCID_NONE, sllc_pmu->base + regs->srcid_ctrl); /* Disable the srcid */ - val =3D readl(sllc_pmu->base + SLLC_PERF_CTRL); + val =3D readl(sllc_pmu->base + regs->perf_ctrl); val &=3D ~(SLLC_SRCID_EN | SLLC_FILT_EN); - writel(val, sllc_pmu->base + SLLC_PERF_CTRL); + writel(val, sllc_pmu->base + regs->perf_ctrl); } } =20 @@ -167,29 +193,27 @@ static void hisi_sllc_pmu_clear_filter(struct perf_ev= ent *event) } } =20 -static u32 hisi_sllc_pmu_get_counter_offset(int idx) -{ - return (SLLC_EVENT_CNT0_L + idx * 8); -} - static u64 hisi_sllc_pmu_read_counter(struct hisi_pmu *sllc_pmu, struct hw_perf_event *hwc) { - return readq(sllc_pmu->base + - hisi_sllc_pmu_get_counter_offset(hwc->idx)); + struct hisi_sllc_pmu_regs *regs =3D sllc_pmu->dev_info->private; + + return readq(sllc_pmu->base + SLLC_EVENT_CNTn(regs->event_cnt0, hwc->idx)= ); } =20 static void hisi_sllc_pmu_write_counter(struct hisi_pmu *sllc_pmu, struct hw_perf_event *hwc, u64 val) { - writeq(val, sllc_pmu->base + - hisi_sllc_pmu_get_counter_offset(hwc->idx)); + struct hisi_sllc_pmu_regs *regs =3D sllc_pmu->dev_info->private; + + writeq(val, sllc_pmu->base + SLLC_EVENT_CNTn(regs->event_cnt0, hwc->idx)); } =20 static void hisi_sllc_pmu_write_evtype(struct hisi_pmu *sllc_pmu, int idx, u32 type) { - u32 reg, reg_idx, shift, val; + struct hisi_sllc_pmu_regs *regs =3D sllc_pmu->dev_info->private; + u32 reg, val; =20 /* * Select the appropriate event select register(SLLC_EVENT_TYPE0/1). @@ -198,96 +222,98 @@ static void hisi_sllc_pmu_write_evtype(struct hisi_pm= u *sllc_pmu, int idx, * SLLC_EVENT_TYPE0 is chosen. For the latter 4 hardware counters, * SLLC_EVENT_TYPE1 is chosen. */ - reg =3D SLLC_EVENT_TYPE0 + (idx / 4) * 4; - reg_idx =3D idx % 4; - shift =3D 8 * reg_idx; + reg =3D regs->event_type0 + (idx / 4) * 4; =20 /* Write event code to SLLC_EVENT_TYPEx Register */ val =3D readl(sllc_pmu->base + reg); - val &=3D ~(SLLC_EVTYPE_MASK << shift); - val |=3D (type << shift); + val &=3D ~(SLLC_EVTYPE_MASK << HISI_PMU_EVTYPE_SHIFT(idx)); + val |=3D (type << HISI_PMU_EVTYPE_SHIFT(idx)); writel(val, sllc_pmu->base + reg); } =20 static void hisi_sllc_pmu_start_counters(struct hisi_pmu *sllc_pmu) { + struct hisi_sllc_pmu_regs *regs =3D sllc_pmu->dev_info->private; u32 val; =20 - val =3D readl(sllc_pmu->base + SLLC_PERF_CTRL); + val =3D readl(sllc_pmu->base + regs->perf_ctrl); val |=3D SLLC_PERF_CTRL_EN; - writel(val, sllc_pmu->base + SLLC_PERF_CTRL); + writel(val, sllc_pmu->base + regs->perf_ctrl); } =20 static void hisi_sllc_pmu_stop_counters(struct hisi_pmu *sllc_pmu) { + struct hisi_sllc_pmu_regs *regs =3D sllc_pmu->dev_info->private; u32 val; =20 - val =3D readl(sllc_pmu->base + SLLC_PERF_CTRL); + val =3D readl(sllc_pmu->base + regs->perf_ctrl); val &=3D ~(SLLC_PERF_CTRL_EN); - writel(val, sllc_pmu->base + SLLC_PERF_CTRL); + writel(val, sllc_pmu->base + regs->perf_ctrl); } =20 static void hisi_sllc_pmu_enable_counter(struct hisi_pmu *sllc_pmu, struct hw_perf_event *hwc) { + struct hisi_sllc_pmu_regs *regs =3D sllc_pmu->dev_info->private; u32 val; =20 - val =3D readl(sllc_pmu->base + SLLC_EVENT_CTRL); - val |=3D 1 << hwc->idx; - writel(val, sllc_pmu->base + SLLC_EVENT_CTRL); + val =3D readl(sllc_pmu->base + regs->event_ctrl); + val |=3D BIT_ULL(hwc->idx); + writel(val, sllc_pmu->base + regs->event_ctrl); } =20 static void hisi_sllc_pmu_disable_counter(struct hisi_pmu *sllc_pmu, struct hw_perf_event *hwc) { + struct hisi_sllc_pmu_regs *regs =3D sllc_pmu->dev_info->private; u32 val; =20 - val =3D readl(sllc_pmu->base + SLLC_EVENT_CTRL); - val &=3D ~(1 << hwc->idx); - writel(val, sllc_pmu->base + SLLC_EVENT_CTRL); + val =3D readl(sllc_pmu->base + regs->event_ctrl); + val &=3D ~BIT_ULL(hwc->idx); + writel(val, sllc_pmu->base + regs->event_ctrl); } =20 static void hisi_sllc_pmu_enable_counter_int(struct hisi_pmu *sllc_pmu, struct hw_perf_event *hwc) { + struct hisi_sllc_pmu_regs *regs =3D sllc_pmu->dev_info->private; u32 val; =20 - val =3D readl(sllc_pmu->base + SLLC_INT_MASK); - /* Write 0 to enable interrupt */ - val &=3D ~(1 << hwc->idx); - writel(val, sllc_pmu->base + SLLC_INT_MASK); + val =3D readl(sllc_pmu->base + regs->int_mask); + val &=3D ~BIT_ULL(hwc->idx); + writel(val, sllc_pmu->base + regs->int_mask); } =20 static void hisi_sllc_pmu_disable_counter_int(struct hisi_pmu *sllc_pmu, struct hw_perf_event *hwc) { + struct hisi_sllc_pmu_regs *regs =3D sllc_pmu->dev_info->private; u32 val; =20 - val =3D readl(sllc_pmu->base + SLLC_INT_MASK); - /* Write 1 to mask interrupt */ - val |=3D 1 << hwc->idx; - writel(val, sllc_pmu->base + SLLC_INT_MASK); + val =3D readl(sllc_pmu->base + regs->int_mask); + val |=3D BIT_ULL(hwc->idx); + writel(val, sllc_pmu->base + regs->int_mask); } =20 static u32 hisi_sllc_pmu_get_int_status(struct hisi_pmu *sllc_pmu) { - return readl(sllc_pmu->base + SLLC_INT_STATUS); + struct hisi_sllc_pmu_regs *regs =3D sllc_pmu->dev_info->private; + + return readl(sllc_pmu->base + regs->int_status); } =20 static void hisi_sllc_pmu_clear_int_status(struct hisi_pmu *sllc_pmu, int = idx) { - writel(1 << idx, sllc_pmu->base + SLLC_INT_CLEAR); -} + struct hisi_sllc_pmu_regs *regs =3D sllc_pmu->dev_info->private; =20 -static const struct acpi_device_id hisi_sllc_pmu_acpi_match[] =3D { - { "HISI0263", }, - {} -}; -MODULE_DEVICE_TABLE(acpi, hisi_sllc_pmu_acpi_match); + writel(BIT_ULL(idx), sllc_pmu->base + regs->int_clear); +} =20 static int hisi_sllc_pmu_init_data(struct platform_device *pdev, struct hisi_pmu *sllc_pmu) { + struct hisi_sllc_pmu_regs *regs; + hisi_uncore_pmu_init_topology(sllc_pmu, &pdev->dev); =20 /* @@ -304,13 +330,18 @@ static int hisi_sllc_pmu_init_data(struct platform_de= vice *pdev, return -EINVAL; } =20 + sllc_pmu->dev_info =3D device_get_match_data(&pdev->dev); + if (!sllc_pmu->dev_info) + return -ENODEV; + sllc_pmu->base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(sllc_pmu->base)) { dev_err(&pdev->dev, "ioremap failed for sllc_pmu resource.\n"); return PTR_ERR(sllc_pmu->base); } =20 - sllc_pmu->identifier =3D readl(sllc_pmu->base + SLLC_VERSION); + regs =3D sllc_pmu->dev_info->private; + sllc_pmu->identifier =3D readl(sllc_pmu->base + regs->version); =20 return 0; } @@ -352,6 +383,27 @@ static const struct attribute_group *hisi_sllc_pmu_v2_= attr_groups[] =3D { NULL }; =20 +static struct hisi_sllc_pmu_regs hisi_sllc_v2_pmu_regs =3D { + .int_mask =3D SLLC_INT_MASK, + .int_clear =3D SLLC_INT_CLEAR, + .int_status =3D SLLC_INT_STATUS, + .perf_ctrl =3D SLLC_PERF_CTRL, + .srcid_ctrl =3D SLLC_SRCID_CTRL, + .srcid_cmd_shift =3D SLLC_SRCID_CMD_SHIFT, + .srcid_mask_shift =3D SLLC_SRCID_MSK_SHIFT, + .tgtid_ctrl =3D SLLC_TGTID_CTRL, + .tgtid_min_shift =3D SLLC_TGTID_MIN_SHIFT, + .tgtid_max_shift =3D SLLC_TGTID_MAX_SHIFT, + .event_ctrl =3D SLLC_EVENT_CTRL, + .event_type0 =3D SLLC_EVENT_TYPE0, + .version =3D SLLC_VERSION, + .event_cnt0 =3D SLLC_EVENT_CNT0_L, +}; + +static const struct hisi_pmu_dev_info hisi_sllc_v2 =3D { + .private =3D &hisi_sllc_v2_pmu_regs, +}; + static const struct hisi_uncore_ops hisi_uncore_sllc_ops =3D { .write_evtype =3D hisi_sllc_pmu_write_evtype, .get_event_idx =3D hisi_uncore_pmu_get_event_idx, @@ -443,6 +495,12 @@ static void hisi_sllc_pmu_remove(struct platform_devic= e *pdev) &sllc_pmu->node); } =20 +static const struct acpi_device_id hisi_sllc_pmu_acpi_match[] =3D { + { "HISI0263", (kernel_ulong_t)&hisi_sllc_v2 }, + {} +}; +MODULE_DEVICE_TABLE(acpi, hisi_sllc_pmu_acpi_match); + static struct platform_driver hisi_sllc_pmu_driver =3D { .driver =3D { .name =3D "hisi_sllc_pmu", --=20 2.24.0