From nobody Thu Oct 9 08:50:41 2025 Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ECB8624E4DD for ; Thu, 19 Jun 2025 12:56:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.188 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750337776; cv=none; b=sASV7qL/6ykBcM47+kSqYKVSIBm2cOqvSDT3mnzCqXVrrA8WtW247l2TbAU0oyI8R1DwZiIoTrbB36fs8i2Uw8ZwDfcvysvzYkbJ2alRWg+/e4hxCBW5TthVk0PztwIoIHNn+H6O8zY3MewbuJd/2tKvONxMuIgbONN3uucrZ0U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750337776; c=relaxed/simple; bh=Vo9Su6WecOC161havJMXdjSYOQkpzresUTlZBj6b5MA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XNi8fTVc9pqmqw2wZrEB79GOsG3tuB25XlTLDM98mspRE/OFn+YCQjuPzEmN946jzVLovq/Djl8AvXsU1eKzIBGYTvrX4K+FDGwNHBm2gZZ4QSq+chS61eLhYe2fj/bGJdFQw59Ff1bsAIs8xoR+blBIuWK/DHlGCZ2ov4pHyX4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.188 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.194]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4bNLDG4wzZzVmcR; Thu, 19 Jun 2025 20:54:54 +0800 (CST) Received: from dggemv712-chm.china.huawei.com (unknown [10.1.198.32]) by mail.maildlp.com (Postfix) with ESMTPS id DA8251400D9; Thu, 19 Jun 2025 20:56:04 +0800 (CST) Received: from kwepemq200018.china.huawei.com (7.202.195.108) by dggemv712-chm.china.huawei.com (10.1.198.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Thu, 19 Jun 2025 20:56:04 +0800 Received: from localhost.localdomain (10.50.165.33) by kwepemq200018.china.huawei.com (7.202.195.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Thu, 19 Jun 2025 20:56:03 +0800 From: Yicong Yang To: , , , CC: , , , , , Subject: [RESEND PATCH v3 1/8] drivers/perf: hisi: Simplify the probe process for each DDRC version Date: Thu, 19 Jun 2025 20:55:50 +0800 Message-ID: <20250619125557.57372-2-yangyicong@huawei.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20250619125557.57372-1-yangyicong@huawei.com> References: <20250619125557.57372-1-yangyicong@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To kwepemq200018.china.huawei.com (7.202.195.108) Content-Type: text/plain; charset="utf-8" From: Junhao He Version 1 and 2 of DDRC PMU also use different HID. Make use of struct acpi_device_id::driver_data for version specific information rather than judge the version register. This will help to simplify the probe process and also a bit easier for extension. In order to support this extend struct hisi_pmu_dev_info for version specific counter bits and event range. Signed-off-by: Junhao He Reviewed-by: Jonathan Cameron Signed-off-by: Yicong Yang --- drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c | 328 ++++++++---------- drivers/perf/hisilicon/hisi_uncore_pmu.h | 2 + 2 files changed, 142 insertions(+), 188 deletions(-) diff --git a/drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c b/drivers/perf/h= isilicon/hisi_uncore_ddrc_pmu.c index 7e490f8868f2..7e3c2436e96b 100644 --- a/drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c @@ -50,6 +50,10 @@ #define DDRC_V1_NR_EVENTS 0x7 #define DDRC_V2_NR_EVENTS 0x90 =20 +#define DDRC_EVENT_CNTn(base, n) ((base) + (n) * 8) +#define DDRC_EVENT_TYPEn(base, n) ((base) + (n) * 4) +#define DDRC_UNIMPLEMENTED_REG GENMASK(31, 0) + /* * For PMU v1, there are eight-events and every event has been mapped * to fixed-purpose counters which register offset is not consistent. @@ -63,47 +67,37 @@ static const u32 ddrc_reg_off[] =3D { DDRC_PRE_CMD, DDRC_ACT_CMD, DDRC_RNK_CHG, DDRC_RW_CHG }; =20 -/* - * Select the counter register offset using the counter index. - * In PMU v1, there are no programmable counter, the count - * is read form the statistics counter register itself. - */ -static u32 hisi_ddrc_pmu_v1_get_counter_offset(int cntr_idx) -{ - return ddrc_reg_off[cntr_idx]; -} - -static u32 hisi_ddrc_pmu_v2_get_counter_offset(int cntr_idx) -{ - return DDRC_V2_EVENT_CNT + cntr_idx * 8; -} +struct hisi_ddrc_pmu_regs { + u32 event_cnt; + u32 event_ctrl; + u32 event_type; + u32 perf_ctrl; + u32 perf_ctrl_en; + u32 int_mask; + u32 int_clear; + u32 int_status; +}; =20 -static u64 hisi_ddrc_pmu_v1_read_counter(struct hisi_pmu *ddrc_pmu, +static u64 hisi_ddrc_pmu_read_counter(struct hisi_pmu *ddrc_pmu, struct hw_perf_event *hwc) { - return readl(ddrc_pmu->base + - hisi_ddrc_pmu_v1_get_counter_offset(hwc->idx)); -} + struct hisi_ddrc_pmu_regs *regs =3D ddrc_pmu->dev_info->private; =20 -static void hisi_ddrc_pmu_v1_write_counter(struct hisi_pmu *ddrc_pmu, - struct hw_perf_event *hwc, u64 val) -{ - writel((u32)val, - ddrc_pmu->base + hisi_ddrc_pmu_v1_get_counter_offset(hwc->idx)); -} + if (regs->event_cnt =3D=3D DDRC_UNIMPLEMENTED_REG) + return readl(ddrc_pmu->base + ddrc_reg_off[hwc->idx]); =20 -static u64 hisi_ddrc_pmu_v2_read_counter(struct hisi_pmu *ddrc_pmu, - struct hw_perf_event *hwc) -{ - return readq(ddrc_pmu->base + - hisi_ddrc_pmu_v2_get_counter_offset(hwc->idx)); + return readq(ddrc_pmu->base + DDRC_EVENT_CNTn(regs->event_cnt, hwc->idx)); } =20 -static void hisi_ddrc_pmu_v2_write_counter(struct hisi_pmu *ddrc_pmu, - struct hw_perf_event *hwc, u64 val) +static void hisi_ddrc_pmu_write_counter(struct hisi_pmu *ddrc_pmu, + struct hw_perf_event *hwc, u64 val) { - writeq(val, - ddrc_pmu->base + hisi_ddrc_pmu_v2_get_counter_offset(hwc->idx)); + struct hisi_ddrc_pmu_regs *regs =3D ddrc_pmu->dev_info->private; + + if (regs->event_cnt =3D=3D DDRC_UNIMPLEMENTED_REG) + writel((u32)val, ddrc_pmu->base + ddrc_reg_off[hwc->idx]); + else + writeq(val, ddrc_pmu->base + DDRC_EVENT_CNTn(regs->event_cnt, hwc->idx)); } =20 /* @@ -114,54 +108,12 @@ static void hisi_ddrc_pmu_v2_write_counter(struct his= i_pmu *ddrc_pmu, static void hisi_ddrc_pmu_write_evtype(struct hisi_pmu *ddrc_pmu, int idx, u32 type) { - u32 offset; - - if (ddrc_pmu->identifier >=3D HISI_PMU_V2) { - offset =3D DDRC_V2_EVENT_TYPE + 4 * idx; - writel(type, ddrc_pmu->base + offset); - } -} - -static void hisi_ddrc_pmu_v1_start_counters(struct hisi_pmu *ddrc_pmu) -{ - u32 val; + struct hisi_ddrc_pmu_regs *regs =3D ddrc_pmu->dev_info->private; =20 - /* Set perf_enable in DDRC_PERF_CTRL to start event counting */ - val =3D readl(ddrc_pmu->base + DDRC_PERF_CTRL); - val |=3D DDRC_V1_PERF_CTRL_EN; - writel(val, ddrc_pmu->base + DDRC_PERF_CTRL); -} + if (regs->event_type =3D=3D DDRC_UNIMPLEMENTED_REG) + return; =20 -static void hisi_ddrc_pmu_v1_stop_counters(struct hisi_pmu *ddrc_pmu) -{ - u32 val; - - /* Clear perf_enable in DDRC_PERF_CTRL to stop event counting */ - val =3D readl(ddrc_pmu->base + DDRC_PERF_CTRL); - val &=3D ~DDRC_V1_PERF_CTRL_EN; - writel(val, ddrc_pmu->base + DDRC_PERF_CTRL); -} - -static void hisi_ddrc_pmu_v1_enable_counter(struct hisi_pmu *ddrc_pmu, - struct hw_perf_event *hwc) -{ - u32 val; - - /* Set counter index(event code) in DDRC_EVENT_CTRL register */ - val =3D readl(ddrc_pmu->base + DDRC_EVENT_CTRL); - val |=3D (1 << GET_DDRC_EVENTID(hwc)); - writel(val, ddrc_pmu->base + DDRC_EVENT_CTRL); -} - -static void hisi_ddrc_pmu_v1_disable_counter(struct hisi_pmu *ddrc_pmu, - struct hw_perf_event *hwc) -{ - u32 val; - - /* Clear counter index(event code) in DDRC_EVENT_CTRL register */ - val =3D readl(ddrc_pmu->base + DDRC_EVENT_CTRL); - val &=3D ~(1 << GET_DDRC_EVENTID(hwc)); - writel(val, ddrc_pmu->base + DDRC_EVENT_CTRL); + writel(type, ddrc_pmu->base + DDRC_EVENT_TYPEn(regs->event_type, idx)); } =20 static int hisi_ddrc_pmu_v1_get_event_idx(struct perf_event *event) @@ -180,120 +132,96 @@ static int hisi_ddrc_pmu_v1_get_event_idx(struct per= f_event *event) return idx; } =20 -static int hisi_ddrc_pmu_v2_get_event_idx(struct perf_event *event) +static int hisi_ddrc_pmu_get_event_idx(struct perf_event *event) { + struct hisi_pmu *ddrc_pmu =3D to_hisi_pmu(event->pmu); + struct hisi_ddrc_pmu_regs *regs =3D ddrc_pmu->dev_info->private; + + if (regs->event_type =3D=3D DDRC_UNIMPLEMENTED_REG) + return hisi_ddrc_pmu_v1_get_event_idx(event); + return hisi_uncore_pmu_get_event_idx(event); } =20 -static void hisi_ddrc_pmu_v2_start_counters(struct hisi_pmu *ddrc_pmu) +static void hisi_ddrc_pmu_start_counters(struct hisi_pmu *ddrc_pmu) { + struct hisi_ddrc_pmu_regs *regs =3D ddrc_pmu->dev_info->private; u32 val; =20 - val =3D readl(ddrc_pmu->base + DDRC_V2_PERF_CTRL); - val |=3D DDRC_V2_PERF_CTRL_EN; - writel(val, ddrc_pmu->base + DDRC_V2_PERF_CTRL); + val =3D readl(ddrc_pmu->base + regs->perf_ctrl); + val |=3D regs->perf_ctrl_en; + writel(val, ddrc_pmu->base + regs->perf_ctrl); } =20 -static void hisi_ddrc_pmu_v2_stop_counters(struct hisi_pmu *ddrc_pmu) +static void hisi_ddrc_pmu_stop_counters(struct hisi_pmu *ddrc_pmu) { + struct hisi_ddrc_pmu_regs *regs =3D ddrc_pmu->dev_info->private; u32 val; =20 - val =3D readl(ddrc_pmu->base + DDRC_V2_PERF_CTRL); - val &=3D ~DDRC_V2_PERF_CTRL_EN; - writel(val, ddrc_pmu->base + DDRC_V2_PERF_CTRL); + val =3D readl(ddrc_pmu->base + regs->perf_ctrl); + val &=3D ~regs->perf_ctrl_en; + writel(val, ddrc_pmu->base + regs->perf_ctrl); } =20 -static void hisi_ddrc_pmu_v2_enable_counter(struct hisi_pmu *ddrc_pmu, +static void hisi_ddrc_pmu_enable_counter(struct hisi_pmu *ddrc_pmu, struct hw_perf_event *hwc) { + struct hisi_ddrc_pmu_regs *regs =3D ddrc_pmu->dev_info->private; u32 val; =20 - val =3D readl(ddrc_pmu->base + DDRC_V2_EVENT_CTRL); - val |=3D 1 << hwc->idx; - writel(val, ddrc_pmu->base + DDRC_V2_EVENT_CTRL); + val =3D readl(ddrc_pmu->base + regs->event_ctrl); + val |=3D BIT_ULL(hwc->idx); + writel(val, ddrc_pmu->base + regs->event_ctrl); } =20 -static void hisi_ddrc_pmu_v2_disable_counter(struct hisi_pmu *ddrc_pmu, +static void hisi_ddrc_pmu_disable_counter(struct hisi_pmu *ddrc_pmu, struct hw_perf_event *hwc) { + struct hisi_ddrc_pmu_regs *regs =3D ddrc_pmu->dev_info->private; u32 val; =20 - val =3D readl(ddrc_pmu->base + DDRC_V2_EVENT_CTRL); - val &=3D ~(1 << hwc->idx); - writel(val, ddrc_pmu->base + DDRC_V2_EVENT_CTRL); -} - -static void hisi_ddrc_pmu_v1_enable_counter_int(struct hisi_pmu *ddrc_pmu, - struct hw_perf_event *hwc) -{ - u32 val; - - /* Write 0 to enable interrupt */ - val =3D readl(ddrc_pmu->base + DDRC_INT_MASK); - val &=3D ~(1 << hwc->idx); - writel(val, ddrc_pmu->base + DDRC_INT_MASK); -} - -static void hisi_ddrc_pmu_v1_disable_counter_int(struct hisi_pmu *ddrc_pmu, - struct hw_perf_event *hwc) -{ - u32 val; - - /* Write 1 to mask interrupt */ - val =3D readl(ddrc_pmu->base + DDRC_INT_MASK); - val |=3D 1 << hwc->idx; - writel(val, ddrc_pmu->base + DDRC_INT_MASK); + val =3D readl(ddrc_pmu->base + regs->event_ctrl); + val &=3D ~BIT_ULL(hwc->idx); + writel(val, ddrc_pmu->base + regs->event_ctrl); } =20 -static void hisi_ddrc_pmu_v2_enable_counter_int(struct hisi_pmu *ddrc_pmu, - struct hw_perf_event *hwc) +static void hisi_ddrc_pmu_enable_counter_int(struct hisi_pmu *ddrc_pmu, + struct hw_perf_event *hwc) { + struct hisi_ddrc_pmu_regs *regs =3D ddrc_pmu->dev_info->private; u32 val; =20 - val =3D readl(ddrc_pmu->base + DDRC_V2_INT_MASK); - val &=3D ~(1 << hwc->idx); - writel(val, ddrc_pmu->base + DDRC_V2_INT_MASK); + val =3D readl(ddrc_pmu->base + regs->int_mask); + val &=3D ~BIT_ULL(hwc->idx); + writel(val, ddrc_pmu->base + regs->int_mask); } =20 -static void hisi_ddrc_pmu_v2_disable_counter_int(struct hisi_pmu *ddrc_pmu, - struct hw_perf_event *hwc) +static void hisi_ddrc_pmu_disable_counter_int(struct hisi_pmu *ddrc_pmu, + struct hw_perf_event *hwc) { + struct hisi_ddrc_pmu_regs *regs =3D ddrc_pmu->dev_info->private; u32 val; =20 - val =3D readl(ddrc_pmu->base + DDRC_V2_INT_MASK); - val |=3D 1 << hwc->idx; - writel(val, ddrc_pmu->base + DDRC_V2_INT_MASK); + val =3D readl(ddrc_pmu->base + regs->int_mask); + val |=3D BIT_ULL(hwc->idx); + writel(val, ddrc_pmu->base + regs->int_mask); } =20 -static u32 hisi_ddrc_pmu_v1_get_int_status(struct hisi_pmu *ddrc_pmu) +static u32 hisi_ddrc_pmu_get_int_status(struct hisi_pmu *ddrc_pmu) { - return readl(ddrc_pmu->base + DDRC_INT_STATUS); -} + struct hisi_ddrc_pmu_regs *regs =3D ddrc_pmu->dev_info->private; =20 -static void hisi_ddrc_pmu_v1_clear_int_status(struct hisi_pmu *ddrc_pmu, - int idx) -{ - writel(1 << idx, ddrc_pmu->base + DDRC_INT_CLEAR); + return readl(ddrc_pmu->base + regs->int_status); } =20 -static u32 hisi_ddrc_pmu_v2_get_int_status(struct hisi_pmu *ddrc_pmu) +static void hisi_ddrc_pmu_clear_int_status(struct hisi_pmu *ddrc_pmu, + int idx) { - return readl(ddrc_pmu->base + DDRC_V2_INT_STATUS); -} + struct hisi_ddrc_pmu_regs *regs =3D ddrc_pmu->dev_info->private; =20 -static void hisi_ddrc_pmu_v2_clear_int_status(struct hisi_pmu *ddrc_pmu, - int idx) -{ - writel(1 << idx, ddrc_pmu->base + DDRC_V2_INT_CLEAR); + writel(1 << idx, ddrc_pmu->base + regs->int_clear); } =20 -static const struct acpi_device_id hisi_ddrc_pmu_acpi_match[] =3D { - { "HISI0233", }, - { "HISI0234", }, - {} -}; -MODULE_DEVICE_TABLE(acpi, hisi_ddrc_pmu_acpi_match); - static int hisi_ddrc_pmu_init_data(struct platform_device *pdev, struct hisi_pmu *ddrc_pmu) { @@ -314,6 +242,10 @@ static int hisi_ddrc_pmu_init_data(struct platform_dev= ice *pdev, return -EINVAL; } =20 + ddrc_pmu->dev_info =3D device_get_match_data(&pdev->dev); + if (!ddrc_pmu->dev_info) + return -ENODEV; + ddrc_pmu->base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(ddrc_pmu->base)) { dev_err(&pdev->dev, "ioremap failed for ddrc_pmu resource\n"); @@ -396,34 +328,19 @@ static const struct attribute_group *hisi_ddrc_pmu_v2= _attr_groups[] =3D { NULL }; =20 -static const struct hisi_uncore_ops hisi_uncore_ddrc_v1_ops =3D { +static const struct hisi_uncore_ops hisi_uncore_ddrc_ops =3D { .write_evtype =3D hisi_ddrc_pmu_write_evtype, - .get_event_idx =3D hisi_ddrc_pmu_v1_get_event_idx, - .start_counters =3D hisi_ddrc_pmu_v1_start_counters, - .stop_counters =3D hisi_ddrc_pmu_v1_stop_counters, - .enable_counter =3D hisi_ddrc_pmu_v1_enable_counter, - .disable_counter =3D hisi_ddrc_pmu_v1_disable_counter, - .enable_counter_int =3D hisi_ddrc_pmu_v1_enable_counter_int, - .disable_counter_int =3D hisi_ddrc_pmu_v1_disable_counter_int, - .write_counter =3D hisi_ddrc_pmu_v1_write_counter, - .read_counter =3D hisi_ddrc_pmu_v1_read_counter, - .get_int_status =3D hisi_ddrc_pmu_v1_get_int_status, - .clear_int_status =3D hisi_ddrc_pmu_v1_clear_int_status, -}; - -static const struct hisi_uncore_ops hisi_uncore_ddrc_v2_ops =3D { - .write_evtype =3D hisi_ddrc_pmu_write_evtype, - .get_event_idx =3D hisi_ddrc_pmu_v2_get_event_idx, - .start_counters =3D hisi_ddrc_pmu_v2_start_counters, - .stop_counters =3D hisi_ddrc_pmu_v2_stop_counters, - .enable_counter =3D hisi_ddrc_pmu_v2_enable_counter, - .disable_counter =3D hisi_ddrc_pmu_v2_disable_counter, - .enable_counter_int =3D hisi_ddrc_pmu_v2_enable_counter_int, - .disable_counter_int =3D hisi_ddrc_pmu_v2_disable_counter_int, - .write_counter =3D hisi_ddrc_pmu_v2_write_counter, - .read_counter =3D hisi_ddrc_pmu_v2_read_counter, - .get_int_status =3D hisi_ddrc_pmu_v2_get_int_status, - .clear_int_status =3D hisi_ddrc_pmu_v2_clear_int_status, + .get_event_idx =3D hisi_ddrc_pmu_get_event_idx, + .start_counters =3D hisi_ddrc_pmu_start_counters, + .stop_counters =3D hisi_ddrc_pmu_stop_counters, + .enable_counter =3D hisi_ddrc_pmu_enable_counter, + .disable_counter =3D hisi_ddrc_pmu_disable_counter, + .enable_counter_int =3D hisi_ddrc_pmu_enable_counter_int, + .disable_counter_int =3D hisi_ddrc_pmu_disable_counter_int, + .write_counter =3D hisi_ddrc_pmu_write_counter, + .read_counter =3D hisi_ddrc_pmu_read_counter, + .get_int_status =3D hisi_ddrc_pmu_get_int_status, + .clear_int_status =3D hisi_ddrc_pmu_clear_int_status, }; =20 static int hisi_ddrc_pmu_dev_probe(struct platform_device *pdev, @@ -439,18 +356,10 @@ static int hisi_ddrc_pmu_dev_probe(struct platform_de= vice *pdev, if (ret) return ret; =20 - if (ddrc_pmu->identifier >=3D HISI_PMU_V2) { - ddrc_pmu->counter_bits =3D 48; - ddrc_pmu->check_event =3D DDRC_V2_NR_EVENTS; - ddrc_pmu->pmu_events.attr_groups =3D hisi_ddrc_pmu_v2_attr_groups; - ddrc_pmu->ops =3D &hisi_uncore_ddrc_v2_ops; - } else { - ddrc_pmu->counter_bits =3D 32; - ddrc_pmu->check_event =3D DDRC_V1_NR_EVENTS; - ddrc_pmu->pmu_events.attr_groups =3D hisi_ddrc_pmu_v1_attr_groups; - ddrc_pmu->ops =3D &hisi_uncore_ddrc_v1_ops; - } - + ddrc_pmu->pmu_events.attr_groups =3D ddrc_pmu->dev_info->attr_groups; + ddrc_pmu->counter_bits =3D ddrc_pmu->dev_info->counter_bits; + ddrc_pmu->check_event =3D ddrc_pmu->dev_info->check_event; + ddrc_pmu->ops =3D &hisi_uncore_ddrc_ops; ddrc_pmu->num_counters =3D DDRC_NR_COUNTERS; ddrc_pmu->dev =3D &pdev->dev; ddrc_pmu->on_cpu =3D -1; @@ -515,6 +424,49 @@ static void hisi_ddrc_pmu_remove(struct platform_devic= e *pdev) &ddrc_pmu->node); } =20 +static struct hisi_ddrc_pmu_regs hisi_ddrc_v1_pmu_regs =3D { + .event_cnt =3D DDRC_UNIMPLEMENTED_REG, + .event_ctrl =3D DDRC_EVENT_CTRL, + .event_type =3D DDRC_UNIMPLEMENTED_REG, + .perf_ctrl =3D DDRC_PERF_CTRL, + .perf_ctrl_en =3D DDRC_V1_PERF_CTRL_EN, + .int_mask =3D DDRC_INT_MASK, + .int_clear =3D DDRC_INT_CLEAR, + .int_status =3D DDRC_INT_STATUS, +}; + +static const struct hisi_pmu_dev_info hisi_ddrc_v1 =3D { + .counter_bits =3D 32, + .check_event =3D DDRC_V1_NR_EVENTS, + .attr_groups =3D hisi_ddrc_pmu_v1_attr_groups, + .private =3D &hisi_ddrc_v1_pmu_regs, +}; + +static struct hisi_ddrc_pmu_regs hisi_ddrc_v2_pmu_regs =3D { + .event_cnt =3D DDRC_V2_EVENT_CNT, + .event_ctrl =3D DDRC_V2_EVENT_CTRL, + .event_type =3D DDRC_V2_EVENT_TYPE, + .perf_ctrl =3D DDRC_V2_PERF_CTRL, + .perf_ctrl_en =3D DDRC_V2_PERF_CTRL_EN, + .int_mask =3D DDRC_V2_INT_MASK, + .int_clear =3D DDRC_V2_INT_CLEAR, + .int_status =3D DDRC_V2_INT_STATUS, +}; + +static const struct hisi_pmu_dev_info hisi_ddrc_v2 =3D { + .counter_bits =3D 48, + .check_event =3D DDRC_V2_NR_EVENTS, + .attr_groups =3D hisi_ddrc_pmu_v2_attr_groups, + .private =3D &hisi_ddrc_v2_pmu_regs, +}; + +static const struct acpi_device_id hisi_ddrc_pmu_acpi_match[] =3D { + { "HISI0233", (kernel_ulong_t)&hisi_ddrc_v1 }, + { "HISI0234", (kernel_ulong_t)&hisi_ddrc_v2 }, + {} +}; +MODULE_DEVICE_TABLE(acpi, hisi_ddrc_pmu_acpi_match); + static struct platform_driver hisi_ddrc_pmu_driver =3D { .driver =3D { .name =3D "hisi_ddrc_pmu", diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.h b/drivers/perf/hisili= con/hisi_uncore_pmu.h index f4fed2544877..777675838b80 100644 --- a/drivers/perf/hisilicon/hisi_uncore_pmu.h +++ b/drivers/perf/hisilicon/hisi_uncore_pmu.h @@ -72,6 +72,8 @@ struct hisi_uncore_ops { struct hisi_pmu_dev_info { const char *name; const struct attribute_group **attr_groups; + u32 counter_bits; + u32 check_event; void *private; }; =20 --=20 2.24.0