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Thu, 19 Jun 2025 04:55:41 -0700 From: Mark Bloch To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Leon Romanovsky , Jonathan Corbet , , , , , Vlad Dogaru , Yevgeny Kliteynik , Mark Bloch Subject: [PATCH net-next 4/8] net/mlx5: HWS, Create STEs directly from matcher Date: Thu, 19 Jun 2025 14:55:18 +0300 Message-ID: <20250619115522.68469-5-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250619115522.68469-1-mbloch@nvidia.com> References: <20250619115522.68469-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F4:EE_|CYYPR12MB8656:EE_ X-MS-Office365-Filtering-Correlation-Id: d8c76bc3-4694-409c-32b9-08ddaf283c15 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?YRz0E4Oj+5nI5cF08ppAGkFRb4DHwby9/3JmIxHleG3n07JU4l7IuQ35Kx1d?= =?us-ascii?Q?f8IKiqQHs4FPzxtdbhitUYCYaf74YeJRZS87Dfr1tywBaK8gudkUzeTvJ6gS?= =?us-ascii?Q?/3BJhv6J0XoqtR0Se5SvSvEYGjrC/2CsmRuWBYeXaQbzs0JZNrnM467vR39P?= =?us-ascii?Q?BQif4jntiiJtKKrh5KjbMXsNbIDA4RCVlG7SqxQ1iqRY+rSt+L+TqMRQldUr?= =?us-ascii?Q?eMmxa9f3VYHJukYSd+wB96kKVrxx51gnhteLzzn+el7HcSlMfHhJgT+NH7Za?= =?us-ascii?Q?hPMu3VCC9H9I2VlyOqQFdUTmFovBKL5BhqHSH+FUSFyxmsKa8946Kt17Zk0Z?= =?us-ascii?Q?kGegl+6787hs873U2tsBdOjE6/3Oa6dOW17JFEb1FmXSwoSL/G2w9Qv9MWpN?= =?us-ascii?Q?1I2CeSmkHSxC6ldiZnf2mfZ9CJZXGcwqp/lCKZWah08BrFA+gcgapTzLRCnO?= =?us-ascii?Q?ttPbWZHPHyR8V6s11WFzqRbc+gnKj1a531UWNosx5F5pzdIB+oUD4yHXG9JQ?= =?us-ascii?Q?3V2PPPCHdidBOLQduSv656/dx7PMKG6NGm0NOW6v697IyoUybDNwmXx3CLLu?= =?us-ascii?Q?WKzh2GCuSKRPupxSa1Q4eI22IQdkBqmUsGP/M5AZarM38lkC7NDFloiARhEy?= =?us-ascii?Q?kyOoVS6ecfVkTVS0vwgIuV+BHmCv8iKeEdsIEHn2e0jjM9jNdN4cQj0iLfiY?= =?us-ascii?Q?u3iCivyIrNoi//l7CleJ/rrZj4rSECliReivfb/ylYCerHx4/g2QLK0uyaT+?= =?us-ascii?Q?aW3YhiO/r76i6znWKAbGAqU121v9zc71oAE3+BH/2XiKGEAMUjVYC1NmYbJk?= =?us-ascii?Q?vZmCIPoLnd0MLljoSTHGn563LuGom/CLUkKbUf2589Yl1ST+oZ4Xs03RlJ2B?= =?us-ascii?Q?D2UGvM40lRA6ZfoKqcfJgq5n2UWjy3X4dsux9uFbAPoCs74o4g9R5g7s06y5?= =?us-ascii?Q?7o7WEc6I1BjqZ+9xOSYOFq8j3aoHL9xOP94D3lWKuKs3JkHXer+vfko3ROHY?= =?us-ascii?Q?1kk6vvpjCaWk4lVgvcL3jVOwmOk+9kSgq/YEhKYgv8B8jMskR/C1HB1pjw1S?= =?us-ascii?Q?GcDhNIZ3ey2bjJc0rHdEDZ/8XTaN2MEwdCcvDsmuKMtLtnMteZi9fLlLm0hP?= =?us-ascii?Q?tt3/lNnUWpLvcREndToJAwvCS+0FTwa+8ggq/SIwpMeW7DBNAZlzbJGlm6yC?= =?us-ascii?Q?mufDs/Ux9J5DoeVhFD14zP8eDEtZe6Iyrde20ilxBUuU7RSbBQbuJlByWblG?= =?us-ascii?Q?K1qb+XhpdlX88dGuPjRgSIeelJ5vW71S3zVaHyc3L74NFpnG2eBeXRYqqn8M?= =?us-ascii?Q?aBI5xk6h9N+VWCOYp4yKk5Oqvs2Vfrs7XsuToyevaFhPdeMejOMJ948bLwex?= =?us-ascii?Q?AS5BMt5aThRm5r1mIYYvK9le+2ag5fEuNftu4h2PiP7u+o9Hfitvy1mAa7tW?= =?us-ascii?Q?LG1y/VyBtpJc/eiXRllyaA4NVPyR1FVJky1nbgWn/1pCEJdZGpROqESN92tf?= =?us-ascii?Q?NRBwAtXJirKZD2h5FVboWqDtd2LbAIZ5xSBh?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(36860700013)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2025 11:55:49.7729 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d8c76bc3-4694-409c-32b9-08ddaf283c15 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8656 Content-Type: text/plain; charset="utf-8" From: Vlad Dogaru Matchers were using the pool abstraction solely as a convenience to allocate two STE ranges. The pool's core functionality, that of allocating individual items from the range, was unused. Matchers rely either on the hardware to hash rules into a table, or on a user-provided index. Remove the STE pool from the matcher and allocate the STE ranges manually instead. Signed-off-by: Vlad Dogaru Reviewed-by: Yevgeny Kliteynik Signed-off-by: Mark Bloch --- .../mellanox/mlx5/core/steering/hws/debug.c | 10 +-- .../mellanox/mlx5/core/steering/hws/matcher.c | 71 ++++++++++--------- .../mellanox/mlx5/core/steering/hws/matcher.h | 3 +- 3 files changed, 41 insertions(+), 43 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/debug.c b= /drivers/net/ethernet/mellanox/mlx5/core/steering/hws/debug.c index 91568d6c1dac..f9b75aefcaa7 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/debug.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/debug.c @@ -118,7 +118,6 @@ static int hws_debug_dump_matcher(struct seq_file *f, s= truct mlx5hws_matcher *ma { enum mlx5hws_table_type tbl_type =3D matcher->tbl->type; struct mlx5hws_cmd_ft_query_attr ft_attr =3D {0}; - struct mlx5hws_pool *ste_pool; u64 icm_addr_0 =3D 0; u64 icm_addr_1 =3D 0; u32 ste_0_id =3D -1; @@ -133,12 +132,9 @@ static int hws_debug_dump_matcher(struct seq_file *f, = struct mlx5hws_matcher *ma matcher->end_ft_id, matcher->col_matcher ? HWS_PTR_TO_ID(matcher->col_matcher) : 0); =20 - ste_pool =3D matcher->match_ste.pool; - if (ste_pool) { - ste_0_id =3D mlx5hws_pool_get_base_id(ste_pool); - if (tbl_type =3D=3D MLX5HWS_TABLE_TYPE_FDB) - ste_1_id =3D mlx5hws_pool_get_base_mirror_id(ste_pool); - } + ste_0_id =3D matcher->match_ste.ste_0_base; + if (tbl_type =3D=3D MLX5HWS_TABLE_TYPE_FDB) + ste_1_id =3D matcher->match_ste.ste_1_base; =20 seq_printf(f, ",%d,%d,%d,%d", matcher->match_ste.rtc_0_id, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c= b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c index ce28ee1c0e41..b0fcaf508e06 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c @@ -507,10 +507,8 @@ static int hws_matcher_create_rtc(struct mlx5hws_match= er *matcher) } } =20 - obj_id =3D mlx5hws_pool_get_base_id(matcher->match_ste.pool); - rtc_attr.pd =3D ctx->pd_num; - rtc_attr.ste_base =3D obj_id; + rtc_attr.ste_base =3D matcher->match_ste.ste_0_base; rtc_attr.reparse_mode =3D mlx5hws_context_get_reparse_mode(ctx); rtc_attr.table_type =3D mlx5hws_table_get_res_fw_ft_type(tbl->type, false= ); hws_matcher_set_rtc_attr_sz(matcher, &rtc_attr, false); @@ -527,9 +525,7 @@ static int hws_matcher_create_rtc(struct mlx5hws_matche= r *matcher) } =20 if (tbl->type =3D=3D MLX5HWS_TABLE_TYPE_FDB) { - obj_id =3D mlx5hws_pool_get_base_mirror_id( - matcher->match_ste.pool); - rtc_attr.ste_base =3D obj_id; + rtc_attr.ste_base =3D matcher->match_ste.ste_1_base; rtc_attr.table_type =3D mlx5hws_table_get_res_fw_ft_type(tbl->type, true= ); =20 obj_id =3D mlx5hws_pool_get_base_mirror_id(ctx->stc_pool); @@ -588,21 +584,6 @@ hws_matcher_check_attr_sz(struct mlx5hws_cmd_query_cap= s *caps, return 0; } =20 -static void hws_matcher_set_pool_attr(struct mlx5hws_pool_attr *attr, - struct mlx5hws_matcher *matcher) -{ - switch (matcher->attr.optimize_flow_src) { - case MLX5HWS_MATCHER_FLOW_SRC_VPORT: - attr->opt_type =3D MLX5HWS_POOL_OPTIMIZE_ORIG; - break; - case MLX5HWS_MATCHER_FLOW_SRC_WIRE: - attr->opt_type =3D MLX5HWS_POOL_OPTIMIZE_MIRROR; - break; - default: - break; - } -} - static int hws_matcher_check_and_process_at(struct mlx5hws_matcher *matche= r, struct mlx5hws_action_template *at) { @@ -683,8 +664,8 @@ static void hws_matcher_set_ip_version_match(struct mlx= 5hws_matcher *matcher) =20 static int hws_matcher_bind_mt(struct mlx5hws_matcher *matcher) { + struct mlx5hws_cmd_ste_create_attr ste_attr =3D {}; struct mlx5hws_context *ctx =3D matcher->tbl->ctx; - struct mlx5hws_pool_attr pool_attr =3D {0}; int ret; =20 /* Calculate match, range and hash definers */ @@ -699,22 +680,39 @@ static int hws_matcher_bind_mt(struct mlx5hws_matcher= *matcher) =20 hws_matcher_set_ip_version_match(matcher); =20 - /* Create an STE pool per matcher*/ - pool_attr.table_type =3D matcher->tbl->type; - pool_attr.pool_type =3D MLX5HWS_POOL_TYPE_STE; - pool_attr.alloc_log_sz =3D matcher->attr.table.sz_col_log + - matcher->attr.table.sz_row_log; - hws_matcher_set_pool_attr(&pool_attr, matcher); - - matcher->match_ste.pool =3D mlx5hws_pool_create(ctx, &pool_attr); - if (!matcher->match_ste.pool) { - mlx5hws_err(ctx, "Failed to allocate matcher STE pool\n"); - ret =3D -EOPNOTSUPP; + /* Create an STE range each for RX and TX. */ + ste_attr.table_type =3D FS_FT_FDB_RX; + ste_attr.log_obj_range =3D + matcher->attr.optimize_flow_src =3D=3D + MLX5HWS_MATCHER_FLOW_SRC_VPORT ? + 0 : matcher->attr.table.sz_col_log + + matcher->attr.table.sz_row_log; + + ret =3D mlx5hws_cmd_ste_create(ctx->mdev, &ste_attr, + &matcher->match_ste.ste_0_base); + if (ret) { + mlx5hws_err(ctx, "Failed to allocate RX STE range (%d)\n", ret); goto uninit_match_definer; } =20 + ste_attr.table_type =3D FS_FT_FDB_TX; + ste_attr.log_obj_range =3D + matcher->attr.optimize_flow_src =3D=3D + MLX5HWS_MATCHER_FLOW_SRC_WIRE ? + 0 : matcher->attr.table.sz_col_log + + matcher->attr.table.sz_row_log; + + ret =3D mlx5hws_cmd_ste_create(ctx->mdev, &ste_attr, + &matcher->match_ste.ste_1_base); + if (ret) { + mlx5hws_err(ctx, "Failed to allocate TX STE range (%d)\n", ret); + goto destroy_rx_ste_range; + } + return 0; =20 +destroy_rx_ste_range: + mlx5hws_cmd_ste_destroy(ctx->mdev, matcher->match_ste.ste_0_base); uninit_match_definer: if (!(matcher->flags & MLX5HWS_MATCHER_FLAGS_COLLISION)) mlx5hws_definer_mt_uninit(ctx, matcher->mt); @@ -723,9 +721,12 @@ static int hws_matcher_bind_mt(struct mlx5hws_matcher = *matcher) =20 static void hws_matcher_unbind_mt(struct mlx5hws_matcher *matcher) { - mlx5hws_pool_destroy(matcher->match_ste.pool); + struct mlx5hws_context *ctx =3D matcher->tbl->ctx; + + mlx5hws_cmd_ste_destroy(ctx->mdev, matcher->match_ste.ste_1_base); + mlx5hws_cmd_ste_destroy(ctx->mdev, matcher->match_ste.ste_0_base); if (!(matcher->flags & MLX5HWS_MATCHER_FLAGS_COLLISION)) - mlx5hws_definer_mt_uninit(matcher->tbl->ctx, matcher->mt); + mlx5hws_definer_mt_uninit(ctx, matcher->mt); } =20 static int diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.h= b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.h index 32e83cddcd60..ae20bcebfdde 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.h @@ -48,7 +48,8 @@ struct mlx5hws_match_template { struct mlx5hws_matcher_match_ste { u32 rtc_0_id; u32 rtc_1_id; - struct mlx5hws_pool *pool; + u32 ste_0_base; + u32 ste_1_base; }; =20 enum { --=20 2.34.1