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Thu, 19 Jun 2025 04:55:37 -0700 From: Mark Bloch To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Leon Romanovsky , Jonathan Corbet , , , , , Vlad Dogaru , Yevgeny Kliteynik , Mark Bloch Subject: [PATCH net-next 3/8] net/mlx5: HWS, Refactor and export rule skip logic Date: Thu, 19 Jun 2025 14:55:17 +0300 Message-ID: <20250619115522.68469-4-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250619115522.68469-1-mbloch@nvidia.com> References: <20250619115522.68469-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F4:EE_|PH8PR12MB8429:EE_ X-MS-Office365-Filtering-Correlation-Id: 212af4bf-bdca-4e77-ec97-08ddaf283907 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|7416014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?thupbgD+eddhT/GEvAMBNDxv8uR9C/0V/+jXfHdFJt3zbZ9MvEsfdz05P7+s?= =?us-ascii?Q?UH2O2FbOwiGF0RVs02XkgqZF+Yt8C1jKCzYZKaAIH3IaeilwkI0mDjtfPLd9?= =?us-ascii?Q?mSQG0v/2CBZPAtIK3EIPZZZWPFhli27wI5bpyyYtscDggd47RlVAUDLBLivg?= =?us-ascii?Q?JuPpkOOeW7S+PHPF0g9dI8Ux8+q/eFMlpSIlIGZjlPDuI9E5u7MQWCy4GyRS?= =?us-ascii?Q?KHF0jgF+eUsI/xQrUTkFxU6k3QD91nH+CSZq47Rvg7HDeTQQFmWx4r2i5098?= =?us-ascii?Q?vHkCbhsp/5HCRGItLScdOkqnmlwOyB1QpCySe8cRc4++OMtg1n1zGa207PxX?= =?us-ascii?Q?pZMPkWFvy1FeljCMr+w9C7jpveQBQ37ssf3JFDlkfjxCjOoqndKrUUVo8l0h?= =?us-ascii?Q?ytCITcz046+/avBsiEenhkaeIGr1psiP75ioO8QemnLA+MofuUvmUDsOg80J?= =?us-ascii?Q?EgmerAs32Y6z/9zWaQ6f70ab5tPTEmJiLtbc3UR+B22E+gZyEboOuy/ynLji?= =?us-ascii?Q?ZH/8y19qqVb02ysxYlTKvSB/bDUB5d4eJpTUQdz1O0HAEHdSQlnHVybHNRDA?= =?us-ascii?Q?6LmE5qjsGwVxYh7DBHfjwQpm8Pi+vvok93LrT8aZskPsUyrJ287vd2T+/eCG?= =?us-ascii?Q?VVVZm5xa++ka3Wok54ecYLNeLKil/kuKWhSh+aCQ3VqvIOZPUyXtzukXDZZ8?= =?us-ascii?Q?ETenMLOCinB8iF2CD48NCzRZ0nHxV11wFhko+fXbxSjHODCoEHh5Zy2B/60Q?= =?us-ascii?Q?KY8sCQhu21YUaTyz+RZVgnsUCRuLE6mq7hDLh8ibinx7du7KebqdTR19d41Y?= =?us-ascii?Q?A4zib8fPJ+PJE25JKW9VY0ENH9tcnPS00eRKHqVeMF5FIqvgmnxMRiLSbi2I?= =?us-ascii?Q?yS33aFcvU1vI/t005xa1sEcCaeQFsjrla4JRgYOpz5TCwFrmPtSRqsyMTGJi?= =?us-ascii?Q?l/+5k6bDmFnJLmU158GyOyGjZ2nb6xK8jnQdanZKpstgKkqDb8muW7u2Vx5x?= =?us-ascii?Q?ZmDM0NPmwr2pSiRPOhUKJZX6x+ezHexqgjeXUYqYTkhCjKtswgCM5NNoHJn7?= =?us-ascii?Q?99NVrW86jRKmzbi7ZA1DvhrcynZgi3rzQf/VcWp1NqXHuP67gbptWh/jReoZ?= =?us-ascii?Q?m5VHSUh7J/c0nzF9sqZHpGFZHdosFqIFMEICzkLsMg3eamxaRULGE42u8xIK?= =?us-ascii?Q?2evDcUMBShHD16v64bYkbzLE36XpDKJR7ptw2bCUpjrEsYsXHG/wQS4ewLxU?= =?us-ascii?Q?J9sd5Die/wOVwEd+hYF0h2xDwpkUvZpRUSu+0Rom4ZA+2BwWtjFjd4BlQ/Ve?= =?us-ascii?Q?41D7wUmWfo3oOSDDYXV8zVafF5ToMtzU7pFhTIbmWwCgQQDqdmvOf5yo3Faw?= =?us-ascii?Q?qSnTQYtj5v3zqJOVUrvVqoXoct9w0V6e/94pwTPWsg79XoJ2GN2SQKAhTMNJ?= =?us-ascii?Q?ZQ2O5ax/mZmvoSwvHKKvPvGX+/jGGFHEpD17zMF+OCyjenTEm8Nfhjm0Pahf?= =?us-ascii?Q?WN0ebk8bv7Ixk/1eGIjRRAsLd5ojnfL0WhDp?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(1800799024)(7416014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2025 11:55:44.6479 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 212af4bf-bdca-4e77-ec97-08ddaf283907 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB8429 Content-Type: text/plain; charset="utf-8" From: Vlad Dogaru The bwc layer will use `mlx5hws_rule_skip` to keep track of numbers of RX and TX rules individually, so export this function for future usage. While we're in there, reduce nesting by adding a couple of early return statements. Signed-off-by: Vlad Dogaru Reviewed-by: Yevgeny Kliteynik Signed-off-by: Mark Bloch --- .../mellanox/mlx5/core/steering/hws/rule.c | 35 ++++++++++--------- .../mellanox/mlx5/core/steering/hws/rule.h | 3 ++ 2 files changed, 21 insertions(+), 17 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/rule.c b/= drivers/net/ethernet/mellanox/mlx5/core/steering/hws/rule.c index 5342a4cc7194..0370b9b87d4e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/rule.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/rule.c @@ -3,10 +3,8 @@ =20 #include "internal.h" =20 -static void hws_rule_skip(struct mlx5hws_matcher *matcher, - struct mlx5hws_match_template *mt, - u32 flow_source, - bool *skip_rx, bool *skip_tx) +void mlx5hws_rule_skip(struct mlx5hws_matcher *matcher, u32 flow_source, + bool *skip_rx, bool *skip_tx) { /* By default FDB rules are added to both RX and TX */ *skip_rx =3D false; @@ -14,20 +12,22 @@ static void hws_rule_skip(struct mlx5hws_matcher *match= er, =20 if (flow_source =3D=3D MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT) { *skip_rx =3D true; - } else if (flow_source =3D=3D MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK) { + return; + } + + if (flow_source =3D=3D MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK) { *skip_tx =3D true; - } else { - /* If no flow source was set for current rule, - * check for flow source in matcher attributes. - */ - if (matcher->attr.optimize_flow_src) { - *skip_tx =3D - matcher->attr.optimize_flow_src =3D=3D MLX5HWS_MATCHER_FLOW_SRC_WIRE; - *skip_rx =3D - matcher->attr.optimize_flow_src =3D=3D MLX5HWS_MATCHER_FLOW_SRC_VPORT; - return; - } + return; } + + /* If no flow source was set for the rule, check for flow source in + * matcher attributes. + */ + if (matcher->attr.optimize_flow_src =3D=3D MLX5HWS_MATCHER_FLOW_SRC_WIRE) + *skip_tx =3D true; + else if (matcher->attr.optimize_flow_src =3D=3D + MLX5HWS_MATCHER_FLOW_SRC_VPORT) + *skip_rx =3D true; } =20 static void @@ -66,7 +66,8 @@ static void hws_rule_init_dep_wqe(struct mlx5hws_send_rin= g_dep_wqe *dep_wqe, attr->rule_idx : 0; =20 if (tbl->type =3D=3D MLX5HWS_TABLE_TYPE_FDB) { - hws_rule_skip(matcher, mt, attr->flow_source, &skip_rx, &skip_tx); + mlx5hws_rule_skip(matcher, attr->flow_source, &skip_rx, + &skip_tx); =20 if (!skip_rx) { dep_wqe->rtc_0 =3D matcher->match_ste.rtc_0_id; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/rule.h b/= drivers/net/ethernet/mellanox/mlx5/core/steering/hws/rule.h index 1c47a9c11572..d0f082b8dbf5 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/rule.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/rule.h @@ -69,6 +69,9 @@ struct mlx5hws_rule { */ }; =20 +void mlx5hws_rule_skip(struct mlx5hws_matcher *matcher, u32 flow_source, + bool *skip_rx, bool *skip_tx); + void mlx5hws_rule_free_action_ste(struct mlx5hws_action_ste_chunk *action_= ste); =20 int mlx5hws_rule_move_hws_remove(struct mlx5hws_rule *rule, --=20 2.34.1