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Thu, 19 Jun 2025 04:55:28 -0700 From: Mark Bloch To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Leon Romanovsky , Jonathan Corbet , , , , , Vlad Dogaru , Yevgeny Kliteynik , Mark Bloch Subject: [PATCH net-next 1/8] net/mlx5: HWS, remove unused create_dest_array parameter Date: Thu, 19 Jun 2025 14:55:15 +0300 Message-ID: <20250619115522.68469-2-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250619115522.68469-1-mbloch@nvidia.com> References: <20250619115522.68469-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F3:EE_|MW3PR12MB4393:EE_ X-MS-Office365-Filtering-Correlation-Id: fe9d1490-cba2-4844-3a8c-08ddaf283512 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|7416014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?2vN81jmYQPC6ivxHBFy84P71f7o3ggi5g4UkLZJ4kF/sGUQu6ssZZm/5U9t4?= =?us-ascii?Q?ZQ+qJcwUK5ZTxvPzjSo5EzrSre5IfjjPur4HtCCvlzJIKrmIOZIPlIzO3P2t?= =?us-ascii?Q?Qv6h7kIDxYtGfuLIIWoSXCdLW92Op3bgHr99jCq56CUDeFKwyua/IgnvCH73?= =?us-ascii?Q?LobBpE++egTOvwJfauFK/ViZ8Dx2Ip4ffUrM3PK8fs+WF5fkeR6bqjL3Eqb6?= =?us-ascii?Q?mIIuYqrV5OQTmXvWmpa2qNu59f7SQ/zAcd+qvzpb+ZxrJBYwvhKwXLsANKYO?= =?us-ascii?Q?m6sxvA4+Nb4OBvxTwEi0Us57OuY38JI8UFQc1bfXY4zZJLG/aOiH1d1++eij?= =?us-ascii?Q?avDLwqLbNri/iN90OTH/0dl38rX6d+SGGgX90+uabAXMexC3nkSwVqr2fSMb?= =?us-ascii?Q?DQrG4aPNd/Kh07dstelxPE5v9OWLfkB5ETqjaqHU7A5DqCKaxEi24TpOsLVd?= =?us-ascii?Q?XP8kGZ+LU71r01kyYuEJFkHMNbAZLMUyx0QJJD6Y97JX1ruACA3K4wRpVNFb?= =?us-ascii?Q?1rzRclZcw3KzKxZ2/tAfrDFcd9UzjAhzm1iWO3vggtAR6n2DeRTyK3Mu+HAd?= =?us-ascii?Q?baKkjvHY5s8Gve3svLDxg7jL+SBNUT/Mf6Xoz+sAKy/0ATdKYrLkFpDauZRY?= =?us-ascii?Q?PumYMdvT5TSN6+Y6wsRAiuRDMOXTvlyhD9rIsRhvNU0UhTEei6GhX38ltZCS?= =?us-ascii?Q?YozosjsSA/+oZ4R9vlkIxDXKhfuj13fqNiZDYFpMolmKH/xycb+G7v8PC3xt?= =?us-ascii?Q?r+Eb1CdV1v83qZbM/nk8KXpO7eto6eF+hxqiBGLnPsmjYDsF3b9rPnxnCGUd?= =?us-ascii?Q?DWyeKaBu18UCg+gGHhigzhxPpUIxmkkAoUN5/WlsxcPBy9BwUn+NbKr2cTPc?= =?us-ascii?Q?t8pm4fMBblQbl2r/tBOMUkhaGoQ/bxWdlPh/4VAakRvtAN0ylrXiMuipZHKC?= =?us-ascii?Q?Tcv/nlLnOrXMkyMdGicpX3QabutfHjXuZdD+cDA5bYG4cHnRvdyjY+6wjqtu?= =?us-ascii?Q?evmKRNmNKUPefJj6V1SWFRnuQTIiM/xujgtMC0OTeIVRDlDINRqOMY+SduxZ?= =?us-ascii?Q?bZXR0mL2pnonv2PhSnPcfuGbj48U1DTcnG5eb72y+3g91zCpXQd/O15FdOsL?= =?us-ascii?Q?SqJR4/9r1i+MAtrluwkopT4fkYwTk2Tx1f6cxYmBgOCNPsDc33HoMdjuLmZQ?= =?us-ascii?Q?c9Sp7EkpDZwplS2ujz9rIs7O9lWHnwGIrt/s7RlRyMkOF8vd5s2tgyhDgBjV?= =?us-ascii?Q?s6cQGUdVAYcdCYM3HIRe6cKo19/3v9yawMKnliMg894/m3rfN0QMwP2oAuK6?= =?us-ascii?Q?Ed4J/xP+qhwxzsDUuOhgNhY7j4RDai9W+GZrwXCE2eTRCDMzx5amyQWFUMv7?= =?us-ascii?Q?1zZXsxxTW8UXjxfbn+LXmpb6obLgDl+AJlSDUPHKk58rMrZdl4E3PIW45be4?= =?us-ascii?Q?o5debmmIwkhNDR8ZFSl0iULw7Oo3Gq3d9kwCXTH5Oa061GvPEnljVfGUs37T?= =?us-ascii?Q?XrfNiTbYqO8AWGcfK8HyQ66/kfSkc5pLvRUD?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(7416014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2025 11:55:38.0070 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fe9d1490-cba2-4844-3a8c-08ddaf283512 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4393 Content-Type: text/plain; charset="utf-8" From: Vlad Dogaru `flow_source` is not used anywhere in mlx5hws_action_create_dest_array. Signed-off-by: Vlad Dogaru Reviewed-by: Yevgeny Kliteynik Signed-off-by: Mark Bloch --- .../mellanox/mlx5/core/steering/hws/action.c | 7 ++----- .../mellanox/mlx5/core/steering/hws/fs_hws.c | 15 ++++++--------- .../mellanox/mlx5/core/steering/hws/mlx5hws.h | 8 ++------ 3 files changed, 10 insertions(+), 20 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c = b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c index 447ea3f8722c..396804369b00 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c @@ -1358,12 +1358,9 @@ mlx5hws_action_create_modify_header(struct mlx5hws_c= ontext *ctx, } =20 struct mlx5hws_action * -mlx5hws_action_create_dest_array(struct mlx5hws_context *ctx, - size_t num_dest, +mlx5hws_action_create_dest_array(struct mlx5hws_context *ctx, size_t num_d= est, struct mlx5hws_action_dest_attr *dests, - bool ignore_flow_level, - u32 flow_source, - u32 flags) + bool ignore_flow_level, u32 flags) { struct mlx5hws_cmd_set_fte_dest *dest_list =3D NULL; struct mlx5hws_cmd_ft_create_attr ft_attr =3D {0}; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/fs_hws.c = b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/fs_hws.c index bf4643d0ce17..57592b92e24b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/fs_hws.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/fs_hws.c @@ -571,14 +571,12 @@ static void mlx5_fs_put_dest_action_sampler(struct ml= x5_fs_hws_context *fs_ctx, static struct mlx5hws_action * mlx5_fs_create_action_dest_array(struct mlx5hws_context *ctx, struct mlx5hws_action_dest_attr *dests, - u32 num_of_dests, bool ignore_flow_level, - u32 flow_source) + u32 num_of_dests, bool ignore_flow_level) { u32 flags =3D MLX5HWS_ACTION_FLAG_HWS_FDB | MLX5HWS_ACTION_FLAG_SHARED; =20 return mlx5hws_action_create_dest_array(ctx, num_of_dests, dests, - ignore_flow_level, - flow_source, flags); + ignore_flow_level, flags); } =20 static struct mlx5hws_action * @@ -1015,7 +1013,6 @@ static int mlx5_fs_fte_get_hws_actions(struct mlx5_fl= ow_root_namespace *ns, } (*ractions)[num_actions++].action =3D dest_actions->dest; } else if (num_dest_actions > 1) { - u32 flow_source =3D fte->act_dests.flow_context.flow_source; bool ignore_flow_level; =20 if (num_actions =3D=3D MLX5_FLOW_CONTEXT_ACTION_MAX || @@ -1025,10 +1022,10 @@ static int mlx5_fs_fte_get_hws_actions(struct mlx5_= flow_root_namespace *ns, } ignore_flow_level =3D !!(fte_action->flags & FLOW_ACT_IGNORE_FLOW_LEVEL); - tmp_action =3D mlx5_fs_create_action_dest_array(ctx, dest_actions, - num_dest_actions, - ignore_flow_level, - flow_source); + tmp_action =3D + mlx5_fs_create_action_dest_array(ctx, dest_actions, + num_dest_actions, + ignore_flow_level); if (!tmp_action) { err =3D -EOPNOTSUPP; goto free_actions; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws.h= b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws.h index d8ac6c196211..a1295a311b70 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws.h @@ -727,18 +727,14 @@ mlx5hws_action_create_push_vlan(struct mlx5hws_contex= t *ctx, u32 flags); * @dests: The destination array. Each contains a destination action and c= an * have additional actions. * @ignore_flow_level: Whether to turn on 'ignore_flow_level' for this des= t. - * @flow_source: Source port of the traffic for this actions. * @flags: Action creation flags (enum mlx5hws_action_flags). * * Return: pointer to mlx5hws_action on success NULL otherwise. */ struct mlx5hws_action * -mlx5hws_action_create_dest_array(struct mlx5hws_context *ctx, - size_t num_dest, +mlx5hws_action_create_dest_array(struct mlx5hws_context *ctx, size_t num_d= est, struct mlx5hws_action_dest_attr *dests, - bool ignore_flow_level, - u32 flow_source, - u32 flags); + bool ignore_flow_level, u32 flags); =20 /** * mlx5hws_action_create_insert_header - Create insert header action. --=20 2.34.1 From nobody Thu Oct 9 07:03:13 2025 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2065.outbound.protection.outlook.com [40.107.237.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F23723B628; 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Signed-off-by: Yevgeny Kliteynik Reviewed-by: Vlad Dogaru Signed-off-by: Mark Bloch --- drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c b/d= rivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c index 9e057f808ea5..665e6e285db5 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c @@ -876,8 +876,6 @@ int mlx5hws_bwc_rule_create_simple(struct mlx5hws_bwc_r= ule *bwc_rule, =20 /* At this point the rule wasn't added. * It could be because there was collision, or some other problem. - * If we don't dive deeper than API, the only thing we know is that - * the status of completion is RTE_FLOW_OP_ERROR. * Try rehash by size and insert rule again - last chance. */ =20 --=20 2.34.1 From nobody Thu Oct 9 07:03:13 2025 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2042.outbound.protection.outlook.com [40.107.243.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68CFF23D283; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Leon Romanovsky , Jonathan Corbet , , , , , Vlad Dogaru , Yevgeny Kliteynik , Mark Bloch Subject: [PATCH net-next 3/8] net/mlx5: HWS, Refactor and export rule skip logic Date: Thu, 19 Jun 2025 14:55:17 +0300 Message-ID: <20250619115522.68469-4-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250619115522.68469-1-mbloch@nvidia.com> References: <20250619115522.68469-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F4:EE_|PH8PR12MB8429:EE_ X-MS-Office365-Filtering-Correlation-Id: 212af4bf-bdca-4e77-ec97-08ddaf283907 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|7416014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?thupbgD+eddhT/GEvAMBNDxv8uR9C/0V/+jXfHdFJt3zbZ9MvEsfdz05P7+s?= =?us-ascii?Q?UH2O2FbOwiGF0RVs02XkgqZF+Yt8C1jKCzYZKaAIH3IaeilwkI0mDjtfPLd9?= =?us-ascii?Q?mSQG0v/2CBZPAtIK3EIPZZZWPFhli27wI5bpyyYtscDggd47RlVAUDLBLivg?= =?us-ascii?Q?JuPpkOOeW7S+PHPF0g9dI8Ux8+q/eFMlpSIlIGZjlPDuI9E5u7MQWCy4GyRS?= =?us-ascii?Q?KHF0jgF+eUsI/xQrUTkFxU6k3QD91nH+CSZq47Rvg7HDeTQQFmWx4r2i5098?= =?us-ascii?Q?vHkCbhsp/5HCRGItLScdOkqnmlwOyB1QpCySe8cRc4++OMtg1n1zGa207PxX?= =?us-ascii?Q?pZMPkWFvy1FeljCMr+w9C7jpveQBQ37ssf3JFDlkfjxCjOoqndKrUUVo8l0h?= =?us-ascii?Q?ytCITcz046+/avBsiEenhkaeIGr1psiP75ioO8QemnLA+MofuUvmUDsOg80J?= =?us-ascii?Q?EgmerAs32Y6z/9zWaQ6f70ab5tPTEmJiLtbc3UR+B22E+gZyEboOuy/ynLji?= =?us-ascii?Q?ZH/8y19qqVb02ysxYlTKvSB/bDUB5d4eJpTUQdz1O0HAEHdSQlnHVybHNRDA?= =?us-ascii?Q?6LmE5qjsGwVxYh7DBHfjwQpm8Pi+vvok93LrT8aZskPsUyrJ287vd2T+/eCG?= =?us-ascii?Q?VVVZm5xa++ka3Wok54ecYLNeLKil/kuKWhSh+aCQ3VqvIOZPUyXtzukXDZZ8?= =?us-ascii?Q?ETenMLOCinB8iF2CD48NCzRZ0nHxV11wFhko+fXbxSjHODCoEHh5Zy2B/60Q?= =?us-ascii?Q?KY8sCQhu21YUaTyz+RZVgnsUCRuLE6mq7hDLh8ibinx7du7KebqdTR19d41Y?= =?us-ascii?Q?A4zib8fPJ+PJE25JKW9VY0ENH9tcnPS00eRKHqVeMF5FIqvgmnxMRiLSbi2I?= =?us-ascii?Q?yS33aFcvU1vI/t005xa1sEcCaeQFsjrla4JRgYOpz5TCwFrmPtSRqsyMTGJi?= =?us-ascii?Q?l/+5k6bDmFnJLmU158GyOyGjZ2nb6xK8jnQdanZKpstgKkqDb8muW7u2Vx5x?= =?us-ascii?Q?ZmDM0NPmwr2pSiRPOhUKJZX6x+ezHexqgjeXUYqYTkhCjKtswgCM5NNoHJn7?= =?us-ascii?Q?99NVrW86jRKmzbi7ZA1DvhrcynZgi3rzQf/VcWp1NqXHuP67gbptWh/jReoZ?= =?us-ascii?Q?m5VHSUh7J/c0nzF9sqZHpGFZHdosFqIFMEICzkLsMg3eamxaRULGE42u8xIK?= =?us-ascii?Q?2evDcUMBShHD16v64bYkbzLE36XpDKJR7ptw2bCUpjrEsYsXHG/wQS4ewLxU?= =?us-ascii?Q?J9sd5Die/wOVwEd+hYF0h2xDwpkUvZpRUSu+0Rom4ZA+2BwWtjFjd4BlQ/Ve?= =?us-ascii?Q?41D7wUmWfo3oOSDDYXV8zVafF5ToMtzU7pFhTIbmWwCgQQDqdmvOf5yo3Faw?= =?us-ascii?Q?qSnTQYtj5v3zqJOVUrvVqoXoct9w0V6e/94pwTPWsg79XoJ2GN2SQKAhTMNJ?= =?us-ascii?Q?ZQ2O5ax/mZmvoSwvHKKvPvGX+/jGGFHEpD17zMF+OCyjenTEm8Nfhjm0Pahf?= =?us-ascii?Q?WN0ebk8bv7Ixk/1eGIjRRAsLd5ojnfL0WhDp?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(1800799024)(7416014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2025 11:55:44.6479 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 212af4bf-bdca-4e77-ec97-08ddaf283907 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB8429 Content-Type: text/plain; charset="utf-8" From: Vlad Dogaru The bwc layer will use `mlx5hws_rule_skip` to keep track of numbers of RX and TX rules individually, so export this function for future usage. While we're in there, reduce nesting by adding a couple of early return statements. Signed-off-by: Vlad Dogaru Reviewed-by: Yevgeny Kliteynik Signed-off-by: Mark Bloch --- .../mellanox/mlx5/core/steering/hws/rule.c | 35 ++++++++++--------- .../mellanox/mlx5/core/steering/hws/rule.h | 3 ++ 2 files changed, 21 insertions(+), 17 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/rule.c b/= drivers/net/ethernet/mellanox/mlx5/core/steering/hws/rule.c index 5342a4cc7194..0370b9b87d4e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/rule.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/rule.c @@ -3,10 +3,8 @@ =20 #include "internal.h" =20 -static void hws_rule_skip(struct mlx5hws_matcher *matcher, - struct mlx5hws_match_template *mt, - u32 flow_source, - bool *skip_rx, bool *skip_tx) +void mlx5hws_rule_skip(struct mlx5hws_matcher *matcher, u32 flow_source, + bool *skip_rx, bool *skip_tx) { /* By default FDB rules are added to both RX and TX */ *skip_rx =3D false; @@ -14,20 +12,22 @@ static void hws_rule_skip(struct mlx5hws_matcher *match= er, =20 if (flow_source =3D=3D MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT) { *skip_rx =3D true; - } else if (flow_source =3D=3D MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK) { + return; + } + + if (flow_source =3D=3D MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK) { *skip_tx =3D true; - } else { - /* If no flow source was set for current rule, - * check for flow source in matcher attributes. - */ - if (matcher->attr.optimize_flow_src) { - *skip_tx =3D - matcher->attr.optimize_flow_src =3D=3D MLX5HWS_MATCHER_FLOW_SRC_WIRE; - *skip_rx =3D - matcher->attr.optimize_flow_src =3D=3D MLX5HWS_MATCHER_FLOW_SRC_VPORT; - return; - } + return; } + + /* If no flow source was set for the rule, check for flow source in + * matcher attributes. + */ + if (matcher->attr.optimize_flow_src =3D=3D MLX5HWS_MATCHER_FLOW_SRC_WIRE) + *skip_tx =3D true; + else if (matcher->attr.optimize_flow_src =3D=3D + MLX5HWS_MATCHER_FLOW_SRC_VPORT) + *skip_rx =3D true; } =20 static void @@ -66,7 +66,8 @@ static void hws_rule_init_dep_wqe(struct mlx5hws_send_rin= g_dep_wqe *dep_wqe, attr->rule_idx : 0; =20 if (tbl->type =3D=3D MLX5HWS_TABLE_TYPE_FDB) { - hws_rule_skip(matcher, mt, attr->flow_source, &skip_rx, &skip_tx); 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Leon Romanovsky , Jonathan Corbet , , , , , Vlad Dogaru , Yevgeny Kliteynik , Mark Bloch Subject: [PATCH net-next 4/8] net/mlx5: HWS, Create STEs directly from matcher Date: Thu, 19 Jun 2025 14:55:18 +0300 Message-ID: <20250619115522.68469-5-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250619115522.68469-1-mbloch@nvidia.com> References: <20250619115522.68469-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F4:EE_|CYYPR12MB8656:EE_ X-MS-Office365-Filtering-Correlation-Id: d8c76bc3-4694-409c-32b9-08ddaf283c15 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?YRz0E4Oj+5nI5cF08ppAGkFRb4DHwby9/3JmIxHleG3n07JU4l7IuQ35Kx1d?= =?us-ascii?Q?f8IKiqQHs4FPzxtdbhitUYCYaf74YeJRZS87Dfr1tywBaK8gudkUzeTvJ6gS?= =?us-ascii?Q?/3BJhv6J0XoqtR0Se5SvSvEYGjrC/2CsmRuWBYeXaQbzs0JZNrnM467vR39P?= =?us-ascii?Q?BQif4jntiiJtKKrh5KjbMXsNbIDA4RCVlG7SqxQ1iqRY+rSt+L+TqMRQldUr?= =?us-ascii?Q?eMmxa9f3VYHJukYSd+wB96kKVrxx51gnhteLzzn+el7HcSlMfHhJgT+NH7Za?= =?us-ascii?Q?hPMu3VCC9H9I2VlyOqQFdUTmFovBKL5BhqHSH+FUSFyxmsKa8946Kt17Zk0Z?= =?us-ascii?Q?kGegl+6787hs873U2tsBdOjE6/3Oa6dOW17JFEb1FmXSwoSL/G2w9Qv9MWpN?= =?us-ascii?Q?1I2CeSmkHSxC6ldiZnf2mfZ9CJZXGcwqp/lCKZWah08BrFA+gcgapTzLRCnO?= =?us-ascii?Q?ttPbWZHPHyR8V6s11WFzqRbc+gnKj1a531UWNosx5F5pzdIB+oUD4yHXG9JQ?= =?us-ascii?Q?3V2PPPCHdidBOLQduSv656/dx7PMKG6NGm0NOW6v697IyoUybDNwmXx3CLLu?= =?us-ascii?Q?WKzh2GCuSKRPupxSa1Q4eI22IQdkBqmUsGP/M5AZarM38lkC7NDFloiARhEy?= =?us-ascii?Q?kyOoVS6ecfVkTVS0vwgIuV+BHmCv8iKeEdsIEHn2e0jjM9jNdN4cQj0iLfiY?= =?us-ascii?Q?u3iCivyIrNoi//l7CleJ/rrZj4rSECliReivfb/ylYCerHx4/g2QLK0uyaT+?= =?us-ascii?Q?aW3YhiO/r76i6znWKAbGAqU121v9zc71oAE3+BH/2XiKGEAMUjVYC1NmYbJk?= =?us-ascii?Q?vZmCIPoLnd0MLljoSTHGn563LuGom/CLUkKbUf2589Yl1ST+oZ4Xs03RlJ2B?= =?us-ascii?Q?D2UGvM40lRA6ZfoKqcfJgq5n2UWjy3X4dsux9uFbAPoCs74o4g9R5g7s06y5?= =?us-ascii?Q?7o7WEc6I1BjqZ+9xOSYOFq8j3aoHL9xOP94D3lWKuKs3JkHXer+vfko3ROHY?= =?us-ascii?Q?1kk6vvpjCaWk4lVgvcL3jVOwmOk+9kSgq/YEhKYgv8B8jMskR/C1HB1pjw1S?= =?us-ascii?Q?GcDhNIZ3ey2bjJc0rHdEDZ/8XTaN2MEwdCcvDsmuKMtLtnMteZi9fLlLm0hP?= =?us-ascii?Q?tt3/lNnUWpLvcREndToJAwvCS+0FTwa+8ggq/SIwpMeW7DBNAZlzbJGlm6yC?= =?us-ascii?Q?mufDs/Ux9J5DoeVhFD14zP8eDEtZe6Iyrde20ilxBUuU7RSbBQbuJlByWblG?= =?us-ascii?Q?K1qb+XhpdlX88dGuPjRgSIeelJ5vW71S3zVaHyc3L74NFpnG2eBeXRYqqn8M?= =?us-ascii?Q?aBI5xk6h9N+VWCOYp4yKk5Oqvs2Vfrs7XsuToyevaFhPdeMejOMJ948bLwex?= =?us-ascii?Q?AS5BMt5aThRm5r1mIYYvK9le+2ag5fEuNftu4h2PiP7u+o9Hfitvy1mAa7tW?= =?us-ascii?Q?LG1y/VyBtpJc/eiXRllyaA4NVPyR1FVJky1nbgWn/1pCEJdZGpROqESN92tf?= =?us-ascii?Q?NRBwAtXJirKZD2h5FVboWqDtd2LbAIZ5xSBh?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(36860700013)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2025 11:55:49.7729 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d8c76bc3-4694-409c-32b9-08ddaf283c15 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8656 Content-Type: text/plain; charset="utf-8" From: Vlad Dogaru Matchers were using the pool abstraction solely as a convenience to allocate two STE ranges. The pool's core functionality, that of allocating individual items from the range, was unused. Matchers rely either on the hardware to hash rules into a table, or on a user-provided index. Remove the STE pool from the matcher and allocate the STE ranges manually instead. Signed-off-by: Vlad Dogaru Reviewed-by: Yevgeny Kliteynik Signed-off-by: Mark Bloch --- .../mellanox/mlx5/core/steering/hws/debug.c | 10 +-- .../mellanox/mlx5/core/steering/hws/matcher.c | 71 ++++++++++--------- .../mellanox/mlx5/core/steering/hws/matcher.h | 3 +- 3 files changed, 41 insertions(+), 43 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/debug.c b= /drivers/net/ethernet/mellanox/mlx5/core/steering/hws/debug.c index 91568d6c1dac..f9b75aefcaa7 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/debug.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/debug.c @@ -118,7 +118,6 @@ static int hws_debug_dump_matcher(struct seq_file *f, s= truct mlx5hws_matcher *ma { enum mlx5hws_table_type tbl_type =3D matcher->tbl->type; struct mlx5hws_cmd_ft_query_attr ft_attr =3D {0}; - struct mlx5hws_pool *ste_pool; u64 icm_addr_0 =3D 0; u64 icm_addr_1 =3D 0; u32 ste_0_id =3D -1; @@ -133,12 +132,9 @@ static int hws_debug_dump_matcher(struct seq_file *f, = struct mlx5hws_matcher *ma matcher->end_ft_id, matcher->col_matcher ? HWS_PTR_TO_ID(matcher->col_matcher) : 0); =20 - ste_pool =3D matcher->match_ste.pool; - if (ste_pool) { - ste_0_id =3D mlx5hws_pool_get_base_id(ste_pool); - if (tbl_type =3D=3D MLX5HWS_TABLE_TYPE_FDB) - ste_1_id =3D mlx5hws_pool_get_base_mirror_id(ste_pool); - } + ste_0_id =3D matcher->match_ste.ste_0_base; + if (tbl_type =3D=3D MLX5HWS_TABLE_TYPE_FDB) + ste_1_id =3D matcher->match_ste.ste_1_base; =20 seq_printf(f, ",%d,%d,%d,%d", matcher->match_ste.rtc_0_id, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c= b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c index ce28ee1c0e41..b0fcaf508e06 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c @@ -507,10 +507,8 @@ static int hws_matcher_create_rtc(struct mlx5hws_match= er *matcher) } } =20 - obj_id =3D mlx5hws_pool_get_base_id(matcher->match_ste.pool); - rtc_attr.pd =3D ctx->pd_num; - rtc_attr.ste_base =3D obj_id; + rtc_attr.ste_base =3D matcher->match_ste.ste_0_base; rtc_attr.reparse_mode =3D mlx5hws_context_get_reparse_mode(ctx); rtc_attr.table_type =3D mlx5hws_table_get_res_fw_ft_type(tbl->type, false= ); hws_matcher_set_rtc_attr_sz(matcher, &rtc_attr, false); @@ -527,9 +525,7 @@ static int hws_matcher_create_rtc(struct mlx5hws_matche= r *matcher) } =20 if (tbl->type =3D=3D MLX5HWS_TABLE_TYPE_FDB) { - obj_id =3D mlx5hws_pool_get_base_mirror_id( - matcher->match_ste.pool); - rtc_attr.ste_base =3D obj_id; + rtc_attr.ste_base =3D matcher->match_ste.ste_1_base; rtc_attr.table_type =3D mlx5hws_table_get_res_fw_ft_type(tbl->type, true= ); =20 obj_id =3D mlx5hws_pool_get_base_mirror_id(ctx->stc_pool); @@ -588,21 +584,6 @@ hws_matcher_check_attr_sz(struct mlx5hws_cmd_query_cap= s *caps, return 0; } =20 -static void hws_matcher_set_pool_attr(struct mlx5hws_pool_attr *attr, - struct mlx5hws_matcher *matcher) -{ - switch (matcher->attr.optimize_flow_src) { - case MLX5HWS_MATCHER_FLOW_SRC_VPORT: - attr->opt_type =3D MLX5HWS_POOL_OPTIMIZE_ORIG; - break; - case MLX5HWS_MATCHER_FLOW_SRC_WIRE: - attr->opt_type =3D MLX5HWS_POOL_OPTIMIZE_MIRROR; - break; - default: - break; - } -} - static int hws_matcher_check_and_process_at(struct mlx5hws_matcher *matche= r, struct mlx5hws_action_template *at) { @@ -683,8 +664,8 @@ static void hws_matcher_set_ip_version_match(struct mlx= 5hws_matcher *matcher) =20 static int hws_matcher_bind_mt(struct mlx5hws_matcher *matcher) { + struct mlx5hws_cmd_ste_create_attr ste_attr =3D {}; struct mlx5hws_context *ctx =3D matcher->tbl->ctx; - struct mlx5hws_pool_attr pool_attr =3D {0}; int ret; =20 /* Calculate match, range and hash definers */ @@ -699,22 +680,39 @@ static int hws_matcher_bind_mt(struct mlx5hws_matcher= *matcher) =20 hws_matcher_set_ip_version_match(matcher); =20 - /* Create an STE pool per matcher*/ - pool_attr.table_type =3D matcher->tbl->type; - pool_attr.pool_type =3D MLX5HWS_POOL_TYPE_STE; - pool_attr.alloc_log_sz =3D matcher->attr.table.sz_col_log + - matcher->attr.table.sz_row_log; - hws_matcher_set_pool_attr(&pool_attr, matcher); - - matcher->match_ste.pool =3D mlx5hws_pool_create(ctx, &pool_attr); - if (!matcher->match_ste.pool) { - mlx5hws_err(ctx, "Failed to allocate matcher STE pool\n"); - ret =3D -EOPNOTSUPP; + /* Create an STE range each for RX and TX. */ + ste_attr.table_type =3D FS_FT_FDB_RX; + ste_attr.log_obj_range =3D + matcher->attr.optimize_flow_src =3D=3D + MLX5HWS_MATCHER_FLOW_SRC_VPORT ? + 0 : matcher->attr.table.sz_col_log + + matcher->attr.table.sz_row_log; + + ret =3D mlx5hws_cmd_ste_create(ctx->mdev, &ste_attr, + &matcher->match_ste.ste_0_base); + if (ret) { + mlx5hws_err(ctx, "Failed to allocate RX STE range (%d)\n", ret); goto uninit_match_definer; } =20 + ste_attr.table_type =3D FS_FT_FDB_TX; + ste_attr.log_obj_range =3D + matcher->attr.optimize_flow_src =3D=3D + MLX5HWS_MATCHER_FLOW_SRC_WIRE ? + 0 : matcher->attr.table.sz_col_log + + matcher->attr.table.sz_row_log; + + ret =3D mlx5hws_cmd_ste_create(ctx->mdev, &ste_attr, + &matcher->match_ste.ste_1_base); + if (ret) { + mlx5hws_err(ctx, "Failed to allocate TX STE range (%d)\n", ret); + goto destroy_rx_ste_range; + } + return 0; =20 +destroy_rx_ste_range: + mlx5hws_cmd_ste_destroy(ctx->mdev, matcher->match_ste.ste_0_base); uninit_match_definer: if (!(matcher->flags & MLX5HWS_MATCHER_FLAGS_COLLISION)) mlx5hws_definer_mt_uninit(ctx, matcher->mt); @@ -723,9 +721,12 @@ static int hws_matcher_bind_mt(struct mlx5hws_matcher = *matcher) =20 static void hws_matcher_unbind_mt(struct mlx5hws_matcher *matcher) { - mlx5hws_pool_destroy(matcher->match_ste.pool); + struct mlx5hws_context *ctx =3D matcher->tbl->ctx; + + mlx5hws_cmd_ste_destroy(ctx->mdev, matcher->match_ste.ste_1_base); + mlx5hws_cmd_ste_destroy(ctx->mdev, matcher->match_ste.ste_0_base); if (!(matcher->flags & MLX5HWS_MATCHER_FLAGS_COLLISION)) - mlx5hws_definer_mt_uninit(matcher->tbl->ctx, matcher->mt); + mlx5hws_definer_mt_uninit(ctx, matcher->mt); } =20 static int diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.h= b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.h index 32e83cddcd60..ae20bcebfdde 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.h @@ -48,7 +48,8 @@ struct mlx5hws_match_template { struct mlx5hws_matcher_match_ste { u32 rtc_0_id; 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Thu, 19 Jun 2025 04:55:46 -0700 From: Mark Bloch To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Leon Romanovsky , Jonathan Corbet , , , , , "Yevgeny Kliteynik" , Vlad Dogaru , Mark Bloch Subject: [PATCH net-next 5/8] net/mlx5: HWS, Decouple matcher RX and TX sizes Date: Thu, 19 Jun 2025 14:55:19 +0300 Message-ID: <20250619115522.68469-6-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250619115522.68469-1-mbloch@nvidia.com> References: <20250619115522.68469-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37D:EE_|IA0PPF8CAB220A1:EE_ X-MS-Office365-Filtering-Correlation-Id: dc6ec36c-f52a-497d-9702-08ddaf283fb9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|82310400026|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?TU9olFV6YgjBds00ZzQnVMAtNNi/089kBAwIsfrwFLurDJJwE/TGmvkq48UT?= =?us-ascii?Q?ngl/zgGEKUlSR4tgrERt/yYYTiARTqqqvJkSthuTbsv+J1LLz5hCsj032WXk?= =?us-ascii?Q?oARwgjDtfO2ZEuc9jHeOKuLeK1bVO95i8wvkZVk8i+6X81RNei/ZYKRFwz3+?= =?us-ascii?Q?FZdgAYHGjIhqY1QIpw5OieMJPco1TzprkwU9s8i6VfbYFwQeFPfEsshhV3kK?= =?us-ascii?Q?2P7QSmDy7BzTlYfRI7PhtZwdCKOXzAHfrzYx6oBSvFLVoMiZ6sCYTuumAQjZ?= =?us-ascii?Q?2LYptSFUGyX0K1GPrIfD4gIbsm75ETyK3C3OoUv0lPXgPvG8cU75/xJPPGEs?= =?us-ascii?Q?IyC9qjjbPCmZaHcBlz6u98t5euoDPAJOESflCIjwP70swFRkRo/Yk2jpzLA0?= =?us-ascii?Q?IpbY3+NxaICGA/H9OEvTxq/ECZ6YddkWPs5KPs1jyCapnHIzJrf4Okgmofzb?= =?us-ascii?Q?XAUaFQpkXn5TYRX36irJScLej/z5uNO3CHD6DbeBgvUshgaI0gBW0ku78DAi?= =?us-ascii?Q?2IW7IXJR2lLTgQbk51V9VkP2ZHb8pAK+as9UylUxY2NhtiZLNNQgRgxItlH5?= =?us-ascii?Q?/sHnp6NNJDicpMHIC1254wV6DscNB/VBv9kZK6n3I34sWWrnp2K4XNt0zP9b?= =?us-ascii?Q?G/0zqJsNw8ITDylxo+02iU7+IQ71qMlPUfyuiLfjUjrpUAZ+K7H3Iw1UanM+?= =?us-ascii?Q?rbO8VCWSoBaLtzxvrrO8H8Bfr+n2BBWnkOzme3JUmRTI1wRgVjqP/3JBqUCI?= =?us-ascii?Q?UL7U2P1nUXQ0fGh6MQDKOKlWK9BSEdJ25V5VIfBKUV2E1iPLVN0YqpdHuca2?= =?us-ascii?Q?pKSlYUIR+bYSO8IzKc08E10/cOmvVvMSpO4GfaTwSB9P1CRvHkIgmn1QNOGD?= =?us-ascii?Q?xnEv240aVTMDoNKQKR/o7ImogoEZZ9u4FAOaEcUtUMPZZgkDVjSaKXWrPr2Y?= =?us-ascii?Q?5fOVTv761FHN8Cwug2qgEB9NaDpJEKJvGVNNar7fSbxnjJvKS0WY7ebLjVzc?= =?us-ascii?Q?+qg8nohtb62ldNMalTuo849I1nQCdBQrs8k0zWXnSIO3kg6WT2dR81M1tToG?= =?us-ascii?Q?k4ee/5UpKbsmSuVDnKTGoszOZ6qv2e8WyWxMTDq3OL+mK8LzKaDsJIV3wQ9t?= =?us-ascii?Q?ED31ncHo8wNRxqOkKbjVxnq4Lmxu+E2Z0tbigOOR3oRsPUREYNYeBrwemoU9?= =?us-ascii?Q?NH6XwAL7NrGryzm2ZmFwfi1CL95Mur07nGiTw5oGjLuFIUWdckf+0xXriCHc?= =?us-ascii?Q?tJWR0t9nm4w/c58emCH6UqdaRrZTjpH5PpSxuqBSHQcWL79nwxFLJpfUjQBH?= =?us-ascii?Q?phWIMi0S6r3EjtjHb9nJiRkaEx2sW4YDRIrgtfrbdUBzhjLWzyOtewzHEnFj?= =?us-ascii?Q?ZnasfW2VFRPoKQkRtiEFUI78zJBH3ksU5CyxCh95zQ3QFwYqe8vON2ev1ZL6?= =?us-ascii?Q?y9vuK0i4w6FT21PhN4gI9iLzDH29lKQxYYaBO5tfy/3qxO6kVgyDTXoLCTxZ?= =?us-ascii?Q?QIaCWCk9QyGyoHXJcgOUz30TGQZTMVN4pKAI?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700013)(1800799024)(82310400026)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2025 11:55:55.7687 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dc6ec36c-f52a-497d-9702-08ddaf283fb9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PPF8CAB220A1 Content-Type: text/plain; charset="utf-8" From: Yevgeny Kliteynik Kernel HWS only uses FDB tables and, as such, creates two lower level containers (RTCs) for each matcher: one for RX and one for TX. Allow these RTCs to differ in size by converting the size part of the matcher attribute to a two element array. Signed-off-by: Vlad Dogaru Reviewed-by: Yevgeny Kliteynik Signed-off-by: Mark Bloch --- .../mellanox/mlx5/core/steering/hws/bwc.c | 7 +- .../mellanox/mlx5/core/steering/hws/debug.c | 10 +- .../mellanox/mlx5/core/steering/hws/matcher.c | 107 ++++++++++++------ .../mellanox/mlx5/core/steering/hws/mlx5hws.h | 28 +++-- 4 files changed, 104 insertions(+), 48 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c b/d= rivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c index 665e6e285db5..009641e6c874 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c @@ -48,7 +48,7 @@ static void hws_bwc_unlock_all_queues(struct mlx5hws_cont= ext *ctx) =20 static void hws_bwc_matcher_init_attr(struct mlx5hws_bwc_matcher *bwc_matc= her, u32 priority, - u8 size_log, + u8 size_log_rx, u8 size_log_tx, struct mlx5hws_matcher_attr *attr) { struct mlx5hws_bwc_matcher *first_matcher =3D @@ -62,7 +62,8 @@ static void hws_bwc_matcher_init_attr(struct mlx5hws_bwc_= matcher *bwc_matcher, attr->optimize_flow_src =3D MLX5HWS_MATCHER_FLOW_SRC_ANY; attr->insert_mode =3D MLX5HWS_MATCHER_INSERT_BY_HASH; attr->distribute_mode =3D MLX5HWS_MATCHER_DISTRIBUTE_BY_HASH; - attr->rule.num_log =3D size_log; + attr->size[MLX5HWS_MATCHER_SIZE_TYPE_RX].rule.num_log =3D size_log_rx; + attr->size[MLX5HWS_MATCHER_SIZE_TYPE_TX].rule.num_log =3D size_log_tx; attr->resizable =3D true; attr->max_num_of_at_attach =3D MLX5HWS_BWC_MATCHER_ATTACH_AT_NUM; =20 @@ -93,6 +94,7 @@ int mlx5hws_bwc_matcher_create_simple(struct mlx5hws_bwc_= matcher *bwc_matcher, hws_bwc_matcher_init_attr(bwc_matcher, priority, MLX5HWS_BWC_MATCHER_INIT_SIZE_LOG, + MLX5HWS_BWC_MATCHER_INIT_SIZE_LOG, &attr); =20 bwc_matcher->priority =3D priority; @@ -696,6 +698,7 @@ static int hws_bwc_matcher_move(struct mlx5hws_bwc_matc= her *bwc_matcher) hws_bwc_matcher_init_attr(bwc_matcher, bwc_matcher->priority, bwc_matcher->size_log, + bwc_matcher->size_log, &matcher_attr); =20 old_matcher =3D bwc_matcher->matcher; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/debug.c b= /drivers/net/ethernet/mellanox/mlx5/core/steering/hws/debug.c index f9b75aefcaa7..2ec8cb10139a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/debug.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/debug.c @@ -99,17 +99,19 @@ hws_debug_dump_matcher_attr(struct seq_file *f, struct = mlx5hws_matcher *matcher) { struct mlx5hws_matcher_attr *attr =3D &matcher->attr; =20 - seq_printf(f, "%d,0x%llx,%d,%d,%d,%d,%d,%d,%d,%d\n", + seq_printf(f, "%d,0x%llx,%d,%d,%d,%d,%d,%d,%d,%d,-1,-1,%d,%d\n", MLX5HWS_DEBUG_RES_TYPE_MATCHER_ATTR, HWS_PTR_TO_ID(matcher), attr->priority, attr->mode, - attr->table.sz_row_log, - attr->table.sz_col_log, + attr->size[MLX5HWS_MATCHER_SIZE_TYPE_RX].table.sz_row_log, + attr->size[MLX5HWS_MATCHER_SIZE_TYPE_RX].table.sz_col_log, attr->optimize_using_rule_idx, attr->optimize_flow_src, attr->insert_mode, - attr->distribute_mode); + attr->distribute_mode, + attr->size[MLX5HWS_MATCHER_SIZE_TYPE_TX].table.sz_row_log, + attr->size[MLX5HWS_MATCHER_SIZE_TYPE_TX].table.sz_col_log); =20 return 0; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c= b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c index b0fcaf508e06..f3ea09caba2b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c @@ -468,12 +468,16 @@ static int hws_matcher_create_rtc(struct mlx5hws_matc= her *matcher) struct mlx5hws_cmd_rtc_create_attr rtc_attr =3D {0}; struct mlx5hws_match_template *mt =3D matcher->mt; struct mlx5hws_context *ctx =3D matcher->tbl->ctx; + union mlx5hws_matcher_size *size_rx, *size_tx; struct mlx5hws_table *tbl =3D matcher->tbl; u32 obj_id; int ret; =20 - rtc_attr.log_size =3D attr->table.sz_row_log; - rtc_attr.log_depth =3D attr->table.sz_col_log; + size_rx =3D &attr->size[MLX5HWS_MATCHER_SIZE_TYPE_RX]; + size_tx =3D &attr->size[MLX5HWS_MATCHER_SIZE_TYPE_TX]; + + rtc_attr.log_size =3D size_rx->table.sz_row_log; + rtc_attr.log_depth =3D size_rx->table.sz_col_log; rtc_attr.is_frst_jumbo =3D mlx5hws_matcher_mt_is_jumbo(mt); rtc_attr.is_scnd_range =3D 0; rtc_attr.miss_ft_id =3D matcher->end_ft_id; @@ -525,6 +529,8 @@ static int hws_matcher_create_rtc(struct mlx5hws_matche= r *matcher) } =20 if (tbl->type =3D=3D MLX5HWS_TABLE_TYPE_FDB) { + rtc_attr.log_size =3D size_tx->table.sz_row_log; + rtc_attr.log_depth =3D size_tx->table.sz_col_log; rtc_attr.ste_base =3D matcher->match_ste.ste_1_base; rtc_attr.table_type =3D mlx5hws_table_get_res_fw_ft_type(tbl->type, true= ); =20 @@ -562,23 +568,33 @@ hws_matcher_check_attr_sz(struct mlx5hws_cmd_query_ca= ps *caps, struct mlx5hws_matcher *matcher) { struct mlx5hws_matcher_attr *attr =3D &matcher->attr; + struct mlx5hws_context *ctx =3D matcher->tbl->ctx; + union mlx5hws_matcher_size *size; + int i; =20 - if (attr->table.sz_col_log > caps->rtc_log_depth_max) { - mlx5hws_err(matcher->tbl->ctx, "Matcher depth exceeds limit %d\n", - caps->rtc_log_depth_max); - return -EOPNOTSUPP; - } + for (i =3D 0; i < 2; i++) { + size =3D &attr->size[i]; =20 - if (attr->table.sz_col_log + attr->table.sz_row_log > caps->ste_alloc_log= _max) { - mlx5hws_err(matcher->tbl->ctx, "Total matcher size exceeds limit %d\n", - caps->ste_alloc_log_max); - return -EOPNOTSUPP; - } + if (size->table.sz_col_log > caps->rtc_log_depth_max) { + mlx5hws_err(ctx, "Matcher depth exceeds limit %d\n", + caps->rtc_log_depth_max); + return -EOPNOTSUPP; + } =20 - if (attr->table.sz_col_log + attr->table.sz_row_log < caps->ste_alloc_log= _gran) { - mlx5hws_err(matcher->tbl->ctx, "Total matcher size below limit %d\n", - caps->ste_alloc_log_gran); - return -EOPNOTSUPP; + if (size->table.sz_col_log + size->table.sz_row_log > + caps->ste_alloc_log_max) { + mlx5hws_err(ctx, + "Total matcher size exceeds limit %d\n", + caps->ste_alloc_log_max); + return -EOPNOTSUPP; + } + + if (size->table.sz_col_log + size->table.sz_row_log < + caps->ste_alloc_log_gran) { + mlx5hws_err(ctx, "Total matcher size below limit %d\n", + caps->ste_alloc_log_gran); + return -EOPNOTSUPP; + } } =20 return 0; @@ -666,6 +682,7 @@ static int hws_matcher_bind_mt(struct mlx5hws_matcher *= matcher) { struct mlx5hws_cmd_ste_create_attr ste_attr =3D {}; struct mlx5hws_context *ctx =3D matcher->tbl->ctx; + union mlx5hws_matcher_size *size; int ret; =20 /* Calculate match, range and hash definers */ @@ -682,11 +699,11 @@ static int hws_matcher_bind_mt(struct mlx5hws_matcher= *matcher) =20 /* Create an STE range each for RX and TX. */ ste_attr.table_type =3D FS_FT_FDB_RX; + size =3D &matcher->attr.size[MLX5HWS_MATCHER_SIZE_TYPE_RX]; ste_attr.log_obj_range =3D matcher->attr.optimize_flow_src =3D=3D - MLX5HWS_MATCHER_FLOW_SRC_VPORT ? - 0 : matcher->attr.table.sz_col_log + - matcher->attr.table.sz_row_log; + MLX5HWS_MATCHER_FLOW_SRC_VPORT ? + 0 : size->table.sz_col_log + size->table.sz_row_log; =20 ret =3D mlx5hws_cmd_ste_create(ctx->mdev, &ste_attr, &matcher->match_ste.ste_0_base); @@ -696,11 +713,11 @@ static int hws_matcher_bind_mt(struct mlx5hws_matcher= *matcher) } =20 ste_attr.table_type =3D FS_FT_FDB_TX; + size =3D &matcher->attr.size[MLX5HWS_MATCHER_SIZE_TYPE_TX]; ste_attr.log_obj_range =3D matcher->attr.optimize_flow_src =3D=3D - MLX5HWS_MATCHER_FLOW_SRC_WIRE ? - 0 : matcher->attr.table.sz_col_log + - matcher->attr.table.sz_row_log; + MLX5HWS_MATCHER_FLOW_SRC_WIRE ? + 0 : size->table.sz_col_log + size->table.sz_row_log; =20 ret =3D mlx5hws_cmd_ste_create(ctx->mdev, &ste_attr, &matcher->match_ste.ste_1_base); @@ -735,6 +752,10 @@ hws_matcher_validate_insert_mode(struct mlx5hws_cmd_qu= ery_caps *caps, { struct mlx5hws_matcher_attr *attr =3D &matcher->attr; struct mlx5hws_context *ctx =3D matcher->tbl->ctx; + union mlx5hws_matcher_size *size_rx, *size_tx; + + size_rx =3D &matcher->attr.size[MLX5HWS_MATCHER_SIZE_TYPE_RX]; + size_tx =3D &matcher->attr.size[MLX5HWS_MATCHER_SIZE_TYPE_TX]; =20 switch (attr->insert_mode) { case MLX5HWS_MATCHER_INSERT_BY_HASH: @@ -745,7 +766,7 @@ hws_matcher_validate_insert_mode(struct mlx5hws_cmd_que= ry_caps *caps, break; =20 case MLX5HWS_MATCHER_INSERT_BY_INDEX: - if (attr->table.sz_col_log) { + if (size_rx->table.sz_col_log || size_tx->table.sz_col_log) { mlx5hws_err(ctx, "Matcher with INSERT_BY_INDEX supports only Nx1 table = size\n"); return -EOPNOTSUPP; } @@ -765,7 +786,10 @@ hws_matcher_validate_insert_mode(struct mlx5hws_cmd_qu= ery_caps *caps, return -EOPNOTSUPP; } =20 - if (attr->table.sz_row_log > MLX5_IFC_RTC_LINEAR_LOOKUP_TBL_LOG_MAX) { + if (size_rx->table.sz_row_log > + MLX5_IFC_RTC_LINEAR_LOOKUP_TBL_LOG_MAX || + size_tx->table.sz_row_log > + MLX5_IFC_RTC_LINEAR_LOOKUP_TBL_LOG_MAX) { mlx5hws_err(ctx, "Matcher with linear distribute: rows exceed limit %d= ", MLX5_IFC_RTC_LINEAR_LOOKUP_TBL_LOG_MAX); return -EOPNOTSUPP; @@ -789,6 +813,10 @@ hws_matcher_process_attr(struct mlx5hws_cmd_query_caps= *caps, struct mlx5hws_matcher *matcher) { struct mlx5hws_matcher_attr *attr =3D &matcher->attr; + union mlx5hws_matcher_size *size_rx, *size_tx; + + size_rx =3D &attr->size[MLX5HWS_MATCHER_SIZE_TYPE_RX]; + size_tx =3D &attr->size[MLX5HWS_MATCHER_SIZE_TYPE_TX]; =20 if (hws_matcher_validate_insert_mode(caps, matcher)) return -EOPNOTSUPP; @@ -800,8 +828,12 @@ hws_matcher_process_attr(struct mlx5hws_cmd_query_caps= *caps, =20 /* Convert number of rules to the required depth */ if (attr->mode =3D=3D MLX5HWS_MATCHER_RESOURCE_MODE_RULE && - attr->insert_mode =3D=3D MLX5HWS_MATCHER_INSERT_BY_HASH) - attr->table.sz_col_log =3D hws_matcher_rules_to_tbl_depth(attr->rule.num= _log); + attr->insert_mode =3D=3D MLX5HWS_MATCHER_INSERT_BY_HASH) { + size_rx->table.sz_col_log =3D + hws_matcher_rules_to_tbl_depth(size_rx->rule.num_log); + size_tx->table.sz_col_log =3D + hws_matcher_rules_to_tbl_depth(size_tx->rule.num_log); + } =20 matcher->flags |=3D attr->resizable ? MLX5HWS_MATCHER_FLAGS_RESIZABLE : 0; matcher->flags |=3D attr->isolated_matcher_end_ft_id ? @@ -862,14 +894,19 @@ static int hws_matcher_create_col_matcher(struct mlx5hws_matcher *matcher) { struct mlx5hws_context *ctx =3D matcher->tbl->ctx; + union mlx5hws_matcher_size *size_rx, *size_tx; struct mlx5hws_matcher *col_matcher; - int ret; + int i, ret; + + size_rx =3D &matcher->attr.size[MLX5HWS_MATCHER_SIZE_TYPE_RX]; + size_tx =3D &matcher->attr.size[MLX5HWS_MATCHER_SIZE_TYPE_TX]; =20 if (matcher->attr.mode !=3D MLX5HWS_MATCHER_RESOURCE_MODE_RULE || matcher->attr.insert_mode =3D=3D MLX5HWS_MATCHER_INSERT_BY_INDEX) return 0; =20 - if (!hws_matcher_requires_col_tbl(matcher->attr.rule.num_log)) + if (!hws_matcher_requires_col_tbl(size_rx->rule.num_log) && + !hws_matcher_requires_col_tbl(size_tx->rule.num_log)) return 0; =20 col_matcher =3D kzalloc(sizeof(*matcher), GFP_KERNEL); @@ -886,10 +923,16 @@ hws_matcher_create_col_matcher(struct mlx5hws_matcher= *matcher) col_matcher->flags |=3D MLX5HWS_MATCHER_FLAGS_COLLISION; col_matcher->attr.mode =3D MLX5HWS_MATCHER_RESOURCE_MODE_HTABLE; col_matcher->attr.optimize_flow_src =3D matcher->attr.optimize_flow_src; - col_matcher->attr.table.sz_row_log =3D matcher->attr.rule.num_log; - col_matcher->attr.table.sz_col_log =3D MLX5HWS_MATCHER_ASSURED_COL_TBL_DE= PTH; - if (col_matcher->attr.table.sz_row_log > MLX5HWS_MATCHER_ASSURED_ROW_RATI= O) - col_matcher->attr.table.sz_row_log -=3D MLX5HWS_MATCHER_ASSURED_ROW_RATI= O; + for (i =3D 0; i < 2; i++) { + union mlx5hws_matcher_size *dst =3D &col_matcher->attr.size[i]; + union mlx5hws_matcher_size *src =3D &matcher->attr.size[i]; + + dst->table.sz_row_log =3D src->rule.num_log; + dst->table.sz_col_log =3D MLX5HWS_MATCHER_ASSURED_COL_TBL_DEPTH; + if (dst->table.sz_row_log > MLX5HWS_MATCHER_ASSURED_ROW_RATIO) + dst->table.sz_row_log -=3D + MLX5HWS_MATCHER_ASSURED_ROW_RATIO; + } =20 col_matcher->attr.max_num_of_at_attach =3D matcher->attr.max_num_of_at_at= tach; col_matcher->attr.isolated_matcher_end_ft_id =3D diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws.h= b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws.h index a1295a311b70..59c14745ed0c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws.h @@ -93,6 +93,23 @@ enum mlx5hws_matcher_distribute_mode { MLX5HWS_MATCHER_DISTRIBUTE_BY_LINEAR =3D 0x1, }; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Leon Romanovsky , Jonathan Corbet , , , , , "Yevgeny Kliteynik" , Vlad Dogaru , Mark Bloch Subject: [PATCH net-next 6/8] net/mlx5: HWS, Track matcher sizes individually Date: Thu, 19 Jun 2025 14:55:20 +0300 Message-ID: <20250619115522.68469-7-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250619115522.68469-1-mbloch@nvidia.com> References: <20250619115522.68469-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37D:EE_|PH7PR12MB8108:EE_ X-MS-Office365-Filtering-Correlation-Id: 95f47cd7-eb50-466c-dec1-08ddaf28434f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?WHUh4ELgGtMGRN/WYmaku+bxCWtJ1T/NhErDTCxlWWGldHzt4KVm5QBB3xGH?= =?us-ascii?Q?VQkC0WBQuwPSysPUNlLTKNH0Ds3btVQ7aQsLWMi0DjJPyAiPlLgofmCKuQM1?= =?us-ascii?Q?FrGb1uS5QSJgvPSc9H2niFc2NLEG6YmHDq8qnedgAxVE89KOzx7WQUeU8rHW?= =?us-ascii?Q?eE8z7eSUKhIG7oV76ZYdWtD6CfDZt/MAPH8/50pfTUOzlfOTxfKL2u2fvuhY?= =?us-ascii?Q?xunqvAkXyW6B/zc0jYhXefYD6qHzrPB6zWyXS3n00VX3UD6wFG7O7hTUDv1q?= =?us-ascii?Q?V89yLXA5gJXdSjvK+pz4MpkywisYVxvGQAAeZ2HJo3cDGVFFmTIEZTV5FBYB?= =?us-ascii?Q?DsZpojgRPewC0p3+Gd1IU3WrVg/+t4U90Bie4InhFOHABMaPfyIITeQVgcG6?= =?us-ascii?Q?H7oL+OtnVign5VZbWOFpxzjFstsmz1kQ/lnvFG1gQd82JZ7voYaoXxV/oOCm?= =?us-ascii?Q?CQYdSKoRh5vlX7ngc3fuz6aG/s8FKM7nfp2EreNXEkj6rzGzQPc0ZKgyIWAK?= =?us-ascii?Q?+TevtBWuVBxy6UJvDUONQx7C9zVph4sTg6YIrGMzXIZJ6TzeSrS2EMzyh51x?= =?us-ascii?Q?jl4PIoBIvfpLCEiSOi4F5QQLCdfZU1k/5E7mi0D2J8BhAdOWI7V3RNhO/z/7?= =?us-ascii?Q?LqQJGTYOrJFqlzXUKrcGOr6Q1cuk1DLukojbdti4qBGC6XLuy4s/qYOIZFOl?= =?us-ascii?Q?8mzuTp6qHkABJZ2R3tuqljFOWprtG3WDe51EESbhLf+wZuxDiV6dPu+qL3ab?= =?us-ascii?Q?mLbEyGYut3NMQelMtdkib+egkNsmhIdhsrJyxs4q16+aGn4/FqP6bZzJNpVc?= =?us-ascii?Q?CeDCFK1m/HFVHJhPc7nwa/+zyjg9q2pBCDUkNahdgQWSpI5LfqWxcXvKtJny?= =?us-ascii?Q?8JPWBCryv513f48b+kZB+GaKNQ0YEeCKt/TBbBpAYOjSXW2pdKxLFoKVEsP4?= =?us-ascii?Q?vMcNwY1HpQpf6sOr2DGoInY5t6r4Gf9hDN9e6ODiZ/7dK9c6ZL0XkA2tKxX3?= =?us-ascii?Q?inO7Y7WoCYEiAl/toJyLYOlIP8lsZFbhId3od4Lopn7891icCqazk+fqEAef?= =?us-ascii?Q?pSRLK2/Or7Zn8IxZq3bAXejIVvymajbdGjFMJh7I2/fzBptparqnOCXU4GDy?= =?us-ascii?Q?3ox0sgVVlR+l+JBFotjvFcq1q58q1gpyJnuB80WmnqsvbAFEAzgwrEgFPN6B?= =?us-ascii?Q?DUckhmazGIQLb5ciQ2+F9b6aECnJmDp0ftWf2js6ywoi0ajKsDgaPYd1Rwhn?= =?us-ascii?Q?m2BAcDnM6huC44hzeI6GVgKYx5gwmv8ogQSuX/HgJ4gg8KW+VH51r8jqDd0p?= =?us-ascii?Q?YjCjNOX1fN4DzafOOr6LVJnb7YxHAi1+IEOdi8vUGuX6J3J2PAlRyhxGvvp7?= =?us-ascii?Q?OY8+FTnxtzZ6xcskUt+ywli57Yh/kq529jzLEIYMWen9vmtqMYKIXNTbb/df?= =?us-ascii?Q?w4kBVPxYJBBwBjuipzUN0RXB45ykmuODsPTAHMHO52oM2FEZsqMuh9VbpnW5?= =?us-ascii?Q?PlfbGpMcwCSVXDX4TPLHSEldWtUQhqg8w47Y?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2025 11:56:01.8029 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 95f47cd7-eb50-466c-dec1-08ddaf28434f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8108 Content-Type: text/plain; charset="utf-8" From: Yevgeny Kliteynik Track and grow matcher sizes individually for RX and TX RTCs. This allows RX-only or TX-only use cases to effectively halve the device resources they use. For testing we used a simple module that inserts 1M RX-only rules and measured the number of pages the device requests, and memory usage as reported by `free -h`. Pages Memory Before this patch: 300k 1.5GiB After this patch: 160k 900MiB Signed-off-by: Vlad Dogaru Reviewed-by: Yevgeny Kliteynik Signed-off-by: Mark Bloch --- .../mellanox/mlx5/core/steering/hws/bwc.c | 213 +++++++++++++----- .../mellanox/mlx5/core/steering/hws/bwc.h | 14 +- 2 files changed, 167 insertions(+), 60 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c b/d= rivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c index 009641e6c874..0a7903cf75e8 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c @@ -93,12 +93,11 @@ int mlx5hws_bwc_matcher_create_simple(struct mlx5hws_bw= c_matcher *bwc_matcher, =20 hws_bwc_matcher_init_attr(bwc_matcher, priority, - MLX5HWS_BWC_MATCHER_INIT_SIZE_LOG, - MLX5HWS_BWC_MATCHER_INIT_SIZE_LOG, + bwc_matcher->rx_size.size_log, + bwc_matcher->tx_size.size_log, &attr); =20 bwc_matcher->priority =3D priority; - bwc_matcher->size_log =3D MLX5HWS_BWC_MATCHER_INIT_SIZE_LOG; =20 bwc_matcher->size_of_at_array =3D MLX5HWS_BWC_MATCHER_ATTACH_AT_NUM; bwc_matcher->at =3D kcalloc(bwc_matcher->size_of_at_array, @@ -150,6 +149,20 @@ int mlx5hws_bwc_matcher_create_simple(struct mlx5hws_b= wc_matcher *bwc_matcher, return -EINVAL; } =20 +static void +hws_bwc_matcher_init_size_rxtx(struct mlx5hws_bwc_matcher_size *size) +{ + size->size_log =3D MLX5HWS_BWC_MATCHER_INIT_SIZE_LOG; + atomic_set(&size->num_of_rules, 0); + atomic_set(&size->rehash_required, false); +} + +static void hws_bwc_matcher_init_size(struct mlx5hws_bwc_matcher *bwc_matc= her) +{ + hws_bwc_matcher_init_size_rxtx(&bwc_matcher->rx_size); + hws_bwc_matcher_init_size_rxtx(&bwc_matcher->tx_size); +} + struct mlx5hws_bwc_matcher * mlx5hws_bwc_matcher_create(struct mlx5hws_table *table, u32 priority, @@ -170,8 +183,7 @@ mlx5hws_bwc_matcher_create(struct mlx5hws_table *table, if (!bwc_matcher) return NULL; =20 - atomic_set(&bwc_matcher->num_of_rules, 0); - atomic_set(&bwc_matcher->rehash_required, false); + hws_bwc_matcher_init_size(bwc_matcher); =20 /* Check if the required match params can be all matched * in single STE, otherwise complex matcher is needed. @@ -221,12 +233,13 @@ int mlx5hws_bwc_matcher_destroy_simple(struct mlx5hws= _bwc_matcher *bwc_matcher) =20 int mlx5hws_bwc_matcher_destroy(struct mlx5hws_bwc_matcher *bwc_matcher) { - u32 num_of_rules =3D atomic_read(&bwc_matcher->num_of_rules); + u32 rx_rules =3D atomic_read(&bwc_matcher->rx_size.num_of_rules); + u32 tx_rules =3D atomic_read(&bwc_matcher->tx_size.num_of_rules); =20 - if (num_of_rules) + if (rx_rules || tx_rules) mlx5hws_err(bwc_matcher->matcher->tbl->ctx, - "BWC matcher destroy: matcher still has %d rules\n", - num_of_rules); + "BWC matcher destroy: matcher still has %u RX and %u TX rules\n", + rx_rules, tx_rules); =20 if (bwc_matcher->complex) mlx5hws_bwc_matcher_destroy_complex(bwc_matcher); @@ -386,6 +399,16 @@ hws_bwc_rule_destroy_hws_sync(struct mlx5hws_bwc_rule = *bwc_rule, return 0; } =20 +static void hws_bwc_rule_cnt_dec(struct mlx5hws_bwc_rule *bwc_rule) +{ + struct mlx5hws_bwc_matcher *bwc_matcher =3D bwc_rule->bwc_matcher; + + if (!bwc_rule->skip_rx) + atomic_dec(&bwc_matcher->rx_size.num_of_rules); + if (!bwc_rule->skip_tx) + atomic_dec(&bwc_matcher->tx_size.num_of_rules); +} + int mlx5hws_bwc_rule_destroy_simple(struct mlx5hws_bwc_rule *bwc_rule) { struct mlx5hws_bwc_matcher *bwc_matcher =3D bwc_rule->bwc_matcher; @@ -402,7 +425,7 @@ int mlx5hws_bwc_rule_destroy_simple(struct mlx5hws_bwc_= rule *bwc_rule) mutex_lock(queue_lock); =20 ret =3D hws_bwc_rule_destroy_hws_sync(bwc_rule, &attr); - atomic_dec(&bwc_matcher->num_of_rules); + hws_bwc_rule_cnt_dec(bwc_rule); hws_bwc_rule_list_remove(bwc_rule); =20 mutex_unlock(queue_lock); @@ -489,25 +512,27 @@ hws_bwc_rule_update_sync(struct mlx5hws_bwc_rule *bwc= _rule, } =20 static bool -hws_bwc_matcher_size_maxed_out(struct mlx5hws_bwc_matcher *bwc_matcher) +hws_bwc_matcher_size_maxed_out(struct mlx5hws_bwc_matcher *bwc_matcher, + struct mlx5hws_bwc_matcher_size *size) { struct mlx5hws_cmd_query_caps *caps =3D bwc_matcher->matcher->tbl->ctx->c= aps; =20 /* check the match RTC size */ - return (bwc_matcher->size_log + MLX5HWS_MATCHER_ASSURED_MAIN_TBL_DEPTH + + return (size->size_log + MLX5HWS_MATCHER_ASSURED_MAIN_TBL_DEPTH + MLX5HWS_BWC_MATCHER_SIZE_LOG_STEP) > (caps->ste_alloc_log_max - 1); } =20 static bool hws_bwc_matcher_rehash_size_needed(struct mlx5hws_bwc_matcher *bwc_matcher, + struct mlx5hws_bwc_matcher_size *size, u32 num_of_rules) { - if (unlikely(hws_bwc_matcher_size_maxed_out(bwc_matcher))) + if (unlikely(hws_bwc_matcher_size_maxed_out(bwc_matcher, size))) return false; =20 if (unlikely((num_of_rules * 100 / MLX5HWS_BWC_MATCHER_REHASH_PERCENT_TH)= >=3D - (1UL << bwc_matcher->size_log))) + (1UL << size->size_log))) return true; =20 return false; @@ -564,20 +589,21 @@ hws_bwc_matcher_extend_at(struct mlx5hws_bwc_matcher = *bwc_matcher, } =20 static int -hws_bwc_matcher_extend_size(struct mlx5hws_bwc_matcher *bwc_matcher) +hws_bwc_matcher_extend_size(struct mlx5hws_bwc_matcher *bwc_matcher, + struct mlx5hws_bwc_matcher_size *size) { struct mlx5hws_context *ctx =3D bwc_matcher->matcher->tbl->ctx; struct mlx5hws_cmd_query_caps *caps =3D ctx->caps; =20 - if (unlikely(hws_bwc_matcher_size_maxed_out(bwc_matcher))) { + if (unlikely(hws_bwc_matcher_size_maxed_out(bwc_matcher, size))) { mlx5hws_err(ctx, "Can't resize matcher: depth exceeds limit %d\n", caps->rtc_log_depth_max); return -ENOMEM; } =20 - bwc_matcher->size_log =3D - min(bwc_matcher->size_log + MLX5HWS_BWC_MATCHER_SIZE_LOG_STEP, - caps->ste_alloc_log_max - MLX5HWS_MATCHER_ASSURED_MAIN_TBL_DEPTH); + size->size_log =3D min(size->size_log + MLX5HWS_BWC_MATCHER_SIZE_LOG_STEP, + caps->ste_alloc_log_max - + MLX5HWS_MATCHER_ASSURED_MAIN_TBL_DEPTH); =20 return 0; } @@ -697,8 +723,8 @@ static int hws_bwc_matcher_move(struct mlx5hws_bwc_matc= her *bwc_matcher) =20 hws_bwc_matcher_init_attr(bwc_matcher, bwc_matcher->priority, - bwc_matcher->size_log, - bwc_matcher->size_log, + bwc_matcher->rx_size.size_log, + bwc_matcher->tx_size.size_log, &matcher_attr); =20 old_matcher =3D bwc_matcher->matcher; @@ -736,21 +762,39 @@ static int hws_bwc_matcher_move(struct mlx5hws_bwc_ma= tcher *bwc_matcher) static int hws_bwc_matcher_rehash_size(struct mlx5hws_bwc_matcher *bwc_matcher) { + bool need_rx_rehash, need_tx_rehash; int ret; =20 - /* If the current matcher size is already at its max size, we can't - * do the rehash. Skip it and try adding the rule again - perhaps - * there was some change. + need_rx_rehash =3D atomic_read(&bwc_matcher->rx_size.rehash_required); + need_tx_rehash =3D atomic_read(&bwc_matcher->tx_size.rehash_required); + + /* It is possible that another rule has already performed rehash. + * Need to check again if we really need rehash. */ - if (hws_bwc_matcher_size_maxed_out(bwc_matcher)) + if (!need_rx_rehash && !need_tx_rehash) return 0; =20 - /* It is possible that other rule has already performed rehash. - * Need to check again if we really need rehash. + /* If the current matcher RX/TX size is already at its max size, + * it can't be rehashed. */ - if (!atomic_read(&bwc_matcher->rehash_required) && - !hws_bwc_matcher_rehash_size_needed(bwc_matcher, - atomic_read(&bwc_matcher->num_of_rules))) + if (need_rx_rehash && + hws_bwc_matcher_size_maxed_out(bwc_matcher, + &bwc_matcher->rx_size)) { + atomic_set(&bwc_matcher->rx_size.rehash_required, false); + need_rx_rehash =3D false; + } + if (need_tx_rehash && + hws_bwc_matcher_size_maxed_out(bwc_matcher, + &bwc_matcher->tx_size)) { + atomic_set(&bwc_matcher->tx_size.rehash_required, false); + need_tx_rehash =3D false; + } + + /* If both RX and TX rehash flags are now off, it means that whatever + * we wanted to rehash is now at its max size - no rehash can be done. + * Return and try adding the rule again - perhaps there was some change. + */ + if (!need_rx_rehash && !need_tx_rehash) return 0; =20 /* Now we're done all the checking - do the rehash: @@ -759,12 +803,22 @@ hws_bwc_matcher_rehash_size(struct mlx5hws_bwc_matche= r *bwc_matcher) * - move all the rules to the new matcher * - destroy the old matcher */ + atomic_set(&bwc_matcher->rx_size.rehash_required, false); + atomic_set(&bwc_matcher->tx_size.rehash_required, false); =20 - atomic_set(&bwc_matcher->rehash_required, false); + if (need_rx_rehash) { + ret =3D hws_bwc_matcher_extend_size(bwc_matcher, + &bwc_matcher->rx_size); + if (ret) + return ret; + } =20 - ret =3D hws_bwc_matcher_extend_size(bwc_matcher); - if (ret) - return ret; + if (need_tx_rehash) { + ret =3D hws_bwc_matcher_extend_size(bwc_matcher, + &bwc_matcher->tx_size); + if (ret) + return ret; + } =20 return hws_bwc_matcher_move(bwc_matcher); } @@ -816,6 +870,62 @@ static int hws_bwc_rule_get_at_idx(struct mlx5hws_bwc_= rule *bwc_rule, return at_idx; } =20 +static void hws_bwc_rule_cnt_inc_rxtx(struct mlx5hws_bwc_rule *bwc_rule, + struct mlx5hws_bwc_matcher_size *size) +{ + u32 num_of_rules =3D atomic_inc_return(&size->num_of_rules); + + if (unlikely(hws_bwc_matcher_rehash_size_needed(bwc_rule->bwc_matcher, + size, num_of_rules))) + atomic_set(&size->rehash_required, true); +} + +static void hws_bwc_rule_cnt_inc(struct mlx5hws_bwc_rule *bwc_rule) +{ + struct mlx5hws_bwc_matcher *bwc_matcher =3D bwc_rule->bwc_matcher; + + if (!bwc_rule->skip_rx) + hws_bwc_rule_cnt_inc_rxtx(bwc_rule, &bwc_matcher->rx_size); + if (!bwc_rule->skip_tx) + hws_bwc_rule_cnt_inc_rxtx(bwc_rule, &bwc_matcher->tx_size); +} + +static int hws_bwc_rule_cnt_inc_with_rehash(struct mlx5hws_bwc_rule *bwc_r= ule, + u16 bwc_queue_idx) +{ + struct mlx5hws_bwc_matcher *bwc_matcher =3D bwc_rule->bwc_matcher; + struct mlx5hws_context *ctx =3D bwc_matcher->matcher->tbl->ctx; + struct mutex *queue_lock; /* Protect the queue */ + int ret; + + hws_bwc_rule_cnt_inc(bwc_rule); + + if (!atomic_read(&bwc_matcher->rx_size.rehash_required) && + !atomic_read(&bwc_matcher->tx_size.rehash_required)) + return 0; + + queue_lock =3D hws_bwc_get_queue_lock(ctx, bwc_queue_idx); + mutex_unlock(queue_lock); + + hws_bwc_lock_all_queues(ctx); + ret =3D hws_bwc_matcher_rehash_size(bwc_matcher); + hws_bwc_unlock_all_queues(ctx); + + mutex_lock(queue_lock); + + if (likely(!ret)) + return 0; + + /* Failed to rehash. Print a diagnostic and rollback the counters. */ + mlx5hws_err(ctx, + "BWC rule insertion: rehash to sizes [%d, %d] failed (%d)\n", + bwc_matcher->rx_size.size_log, + bwc_matcher->tx_size.size_log, ret); + hws_bwc_rule_cnt_dec(bwc_rule); + + return ret; +} + int mlx5hws_bwc_rule_create_simple(struct mlx5hws_bwc_rule *bwc_rule, u32 *match_param, struct mlx5hws_rule_action rule_actions[], @@ -826,7 +936,6 @@ int mlx5hws_bwc_rule_create_simple(struct mlx5hws_bwc_r= ule *bwc_rule, struct mlx5hws_context *ctx =3D bwc_matcher->matcher->tbl->ctx; struct mlx5hws_rule_attr rule_attr; struct mutex *queue_lock; /* Protect the queue */ - u32 num_of_rules; int ret =3D 0; int at_idx; =20 @@ -844,26 +953,10 @@ int mlx5hws_bwc_rule_create_simple(struct mlx5hws_bwc= _rule *bwc_rule, return -EINVAL; } =20 - /* check if number of rules require rehash */ - num_of_rules =3D atomic_inc_return(&bwc_matcher->num_of_rules); - - if (unlikely(hws_bwc_matcher_rehash_size_needed(bwc_matcher, num_of_rules= ))) { + ret =3D hws_bwc_rule_cnt_inc_with_rehash(bwc_rule, bwc_queue_idx); + if (unlikely(ret)) { mutex_unlock(queue_lock); - - hws_bwc_lock_all_queues(ctx); - ret =3D hws_bwc_matcher_rehash_size(bwc_matcher); - hws_bwc_unlock_all_queues(ctx); - - if (ret) { - mlx5hws_err(ctx, "BWC rule insertion: rehash size [%d -> %d] failed (%d= )\n", - bwc_matcher->size_log - MLX5HWS_BWC_MATCHER_SIZE_LOG_STEP, - bwc_matcher->size_log, - ret); - atomic_dec(&bwc_matcher->num_of_rules); - return ret; - } - - mutex_lock(queue_lock); + return ret; } =20 ret =3D hws_bwc_rule_create_sync(bwc_rule, @@ -881,8 +974,11 @@ int mlx5hws_bwc_rule_create_simple(struct mlx5hws_bwc_= rule *bwc_rule, * It could be because there was collision, or some other problem. * Try rehash by size and insert rule again - last chance. */ + if (!bwc_rule->skip_rx) + atomic_set(&bwc_matcher->rx_size.rehash_required, true); + if (!bwc_rule->skip_tx) + atomic_set(&bwc_matcher->tx_size.rehash_required, true); =20 - atomic_set(&bwc_matcher->rehash_required, true); mutex_unlock(queue_lock); =20 hws_bwc_lock_all_queues(ctx); @@ -891,7 +987,7 @@ int mlx5hws_bwc_rule_create_simple(struct mlx5hws_bwc_r= ule *bwc_rule, =20 if (ret) { mlx5hws_err(ctx, "BWC rule insertion: rehash failed (%d)\n", ret); - atomic_dec(&bwc_matcher->num_of_rules); + hws_bwc_rule_cnt_dec(bwc_rule); return ret; } =20 @@ -907,7 +1003,7 @@ int mlx5hws_bwc_rule_create_simple(struct mlx5hws_bwc_= rule *bwc_rule, if (unlikely(ret)) { mutex_unlock(queue_lock); mlx5hws_err(ctx, "BWC rule insertion failed (%d)\n", ret); - atomic_dec(&bwc_matcher->num_of_rules); + hws_bwc_rule_cnt_dec(bwc_rule); return ret; } =20 @@ -937,6 +1033,9 @@ mlx5hws_bwc_rule_create(struct mlx5hws_bwc_matcher *bw= c_matcher, if (unlikely(!bwc_rule)) return NULL; =20 + mlx5hws_rule_skip(bwc_matcher->matcher, flow_source, + &bwc_rule->skip_rx, &bwc_rule->skip_tx); + bwc_queue_idx =3D hws_bwc_gen_queue_idx(ctx); =20 if (bwc_matcher->complex) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h b/d= rivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h index d21fc247a510..1e9de6b9222c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h @@ -19,6 +19,13 @@ #define MLX5HWS_BWC_POLLING_TIMEOUT 60 =20 struct mlx5hws_bwc_matcher_complex_data; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Leon Romanovsky , Jonathan Corbet , , , , , "Yevgeny Kliteynik" , Vlad Dogaru , Mark Bloch Subject: [PATCH net-next 7/8] net/mlx5: HWS, Shrink empty matchers Date: Thu, 19 Jun 2025 14:55:21 +0300 Message-ID: <20250619115522.68469-8-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250619115522.68469-1-mbloch@nvidia.com> References: <20250619115522.68469-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F0:EE_|MN6PR12MB8469:EE_ X-MS-Office365-Filtering-Correlation-Id: c4082114-c1de-42b2-bf51-08ddaf284489 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|7416014|376014|30052699003|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?VD6pLIoLjmWZV1EVq68nxaJjvGA6UdoM08/RmREfQdlRBHuPF6WI+IJGH0SF?= =?us-ascii?Q?rbAM4F5lSK44wjYZF3wOR57MJ/PV+mvBI91xI7H8TaNumBwLBDK8ozMF/nFH?= =?us-ascii?Q?VD1KE8gdR1zdSGz8ijJpPzAekHS+Zmnp9+ROfajUtgYeWuE+o5+MMapD8hBg?= =?us-ascii?Q?GzHB90i1BlOo92PVD51DoRo9d0iLHRxHQz9lsC9xRD27fM0qwc2S28tXWKfL?= =?us-ascii?Q?2zeBPVmoPtcMrs/yhz1wDidq8GkTU7AdgIMVtf/GlgYcJsWqYwC6pLBUw+C6?= =?us-ascii?Q?3/PtZKhjviOjtEket8OF7zzOwAwOqJB/bTMxDiGjG49Mgdr5ZXgjiGe4gUvD?= =?us-ascii?Q?KP3gooqK0/30klzNgNsGz3UhGak32/Z183JeW2j+EUExyortlmgdGoYLOILu?= =?us-ascii?Q?lWzi5ovZ2k3/KOpNLVZyOTt+aa730XA9uLKCJdOIgwrQKLsJu+r/aqV+Blav?= =?us-ascii?Q?0FQRu/ncoVZ2/MHqvFZ8a4P2eglg2rijc76NVtJl5DAIf4OwYoIeNtcXIWt4?= =?us-ascii?Q?z9LHBoS5jkucK+ZU2kdW8MdSe/Ecqa29D8mvl0ZRwzCzOU5ZcIojfVzzvVkr?= =?us-ascii?Q?MxbfrHZfdmjqBVXLbTfVMHteCv6J6SeOTt4VTARwu/icGJTgu6HWmK6l+OVg?= =?us-ascii?Q?UZGMYG6o7J+A1AlOAmSDBqXJ1PHWGUm5b8uPDT+TSCLwyGSU0K/sEQ0Mms4M?= =?us-ascii?Q?SwroNAMIuJ1HEQRpXEnlVNgwmYMch9QI5SM4PjZjRKclJAJnb6pf5NtG+HoO?= =?us-ascii?Q?Cwp65zT9B1xU/qfyH9PcXXsaUb1VJte9QY+/8srpB4Ht4YsKf+/575u+nSg/?= =?us-ascii?Q?YT2KK07Nsb7j0aE8SRHWSuDecDTLEWr8C5R8Of0oUX1CE1U2nI1lDKP6DALr?= =?us-ascii?Q?VdJEynzircSiV2tLYmoedx8nDkbuUqTdXmLk16BWT4zV0R67F3ACcUYLrL6e?= =?us-ascii?Q?eMQ2tyHT0FxqemAsz8fGCnW4JwhXHYy9q7y+QOOtig0cYY8C8cbrnjBCsjYe?= =?us-ascii?Q?cAsPy4eNi7L5zhxiMLLqE8GzO88u0y7MhoLupVxIeI+ej9G/tDIm3Cjb7iXp?= =?us-ascii?Q?R8e9UJHG46huGQHxUPDW5s2q4NVI9nryeq4NVZBOv3J13TlXsURMSgXWTrw9?= =?us-ascii?Q?RFGgcWKqTqUB4PPt7SPCX6VIAmxxhOkMSpzXVpZPRki3d5dM9VGcIJOYvuKi?= =?us-ascii?Q?diS5G+r+xwXu0brywB4FcRqLFY2cJY8FzTmjKqHzOqbhP1lk+G2eO2g5Dwi0?= =?us-ascii?Q?TPjo5nvk9dtXFYnLJb0elKC+amYlRFdroyneqL/9A6wm9E8vV5Y2jAfnRWMj?= =?us-ascii?Q?1jmtOzT5h10MS32QrcGtKn8oxpgfhr/mXQM6NV5/vomY+2fDhyA/vDUuiHpM?= =?us-ascii?Q?dm6tKyenb635S34MKaQ2e9sQjVb8xN6Qb4auIqEZDkLiurTcmbqSLlkXQ1Zh?= =?us-ascii?Q?22FFvVjRFAGkEiO+P8X3u8PLtg2Cp0NhxidOt5zQdREDejjw0e+NnAFTAQJq?= =?us-ascii?Q?A7wJb4OH9+UP3svFGCI2+0eH7O9lVu/w/6ng?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(7416014)(376014)(30052699003)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2025 11:56:03.9660 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c4082114-c1de-42b2-bf51-08ddaf284489 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN6PR12MB8469 Content-Type: text/plain; charset="utf-8" From: Yevgeny Kliteynik Matcher size is dynamic: it starts at initial size, and then it grows through rehash as more and more rules are added to this matcher. When rules are deleted, matcher's size is not decreased. Rehash approach is greedy. The idea is: if the matcher got to a certain size at some point, chances are - it will get to this size again, so it is better to avoid costly rehash operations whenever possible. However, when all the rules of the matcher are deleted, this should be viewed as special case. If the matcher actually got to the point where it has zero rules, it might be an indication that some usecase from the past is no longer happening. This is where some ICM can be freed. This patch handles this case: when a number of rules in a matcher goes down to zero, the matcher's tables are shrunk to the initial size. Signed-off-by: Yevgeny Kliteynik Reviewed-by: Vlad Dogaru Signed-off-by: Mark Bloch --- .../mellanox/mlx5/core/steering/hws/bwc.c | 68 ++++++++++++++++++- 1 file changed, 67 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c b/d= rivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c index 0a7903cf75e8..b7098c7d2112 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c @@ -3,6 +3,8 @@ =20 #include "internal.h" =20 +static int hws_bwc_matcher_move(struct mlx5hws_bwc_matcher *bwc_matcher); + static u16 hws_bwc_gen_queue_idx(struct mlx5hws_context *ctx) { /* assign random queue */ @@ -409,6 +411,70 @@ static void hws_bwc_rule_cnt_dec(struct mlx5hws_bwc_ru= le *bwc_rule) atomic_dec(&bwc_matcher->tx_size.num_of_rules); } =20 +static int +hws_bwc_matcher_rehash_shrink(struct mlx5hws_bwc_matcher *bwc_matcher) +{ + struct mlx5hws_bwc_matcher_size *rx_size =3D &bwc_matcher->rx_size; + struct mlx5hws_bwc_matcher_size *tx_size =3D &bwc_matcher->tx_size; + + /* It is possible that another thread has added a rule. + * Need to check again if we really need rehash/shrink. + */ + if (atomic_read(&rx_size->num_of_rules) || + atomic_read(&tx_size->num_of_rules)) + return 0; + + /* If the current matcher RX/TX size is already at its initial size. */ + if (rx_size->size_log =3D=3D MLX5HWS_BWC_MATCHER_INIT_SIZE_LOG && + tx_size->size_log =3D=3D MLX5HWS_BWC_MATCHER_INIT_SIZE_LOG) + return 0; + + /* Now we've done all the checking - do the shrinking: + * - reset match RTC size to the initial size + * - create new matcher + * - move the rules, which will not do anything as the matcher is empty + * - destroy the old matcher + */ + + rx_size->size_log =3D MLX5HWS_BWC_MATCHER_INIT_SIZE_LOG; + tx_size->size_log =3D MLX5HWS_BWC_MATCHER_INIT_SIZE_LOG; + + return hws_bwc_matcher_move(bwc_matcher); +} + +static int hws_bwc_rule_cnt_dec_with_shrink(struct mlx5hws_bwc_rule *bwc_r= ule, + u16 bwc_queue_idx) +{ + struct mlx5hws_bwc_matcher *bwc_matcher =3D bwc_rule->bwc_matcher; + struct mlx5hws_context *ctx =3D bwc_matcher->matcher->tbl->ctx; + struct mutex *queue_lock; /* Protect the queue */ + int ret; + + hws_bwc_rule_cnt_dec(bwc_rule); + + if (atomic_read(&bwc_matcher->rx_size.num_of_rules) || + atomic_read(&bwc_matcher->tx_size.num_of_rules)) + return 0; + + /* Matcher has no more rules - shrink it to save ICM. */ + + queue_lock =3D hws_bwc_get_queue_lock(ctx, bwc_queue_idx); + mutex_unlock(queue_lock); + + hws_bwc_lock_all_queues(ctx); + ret =3D hws_bwc_matcher_rehash_shrink(bwc_matcher); + hws_bwc_unlock_all_queues(ctx); + + mutex_lock(queue_lock); + + if (unlikely(ret)) + mlx5hws_err(ctx, + "BWC rule deletion: shrinking empty matcher failed (%d)\n", + ret); + + return ret; +} + int mlx5hws_bwc_rule_destroy_simple(struct mlx5hws_bwc_rule *bwc_rule) { struct mlx5hws_bwc_matcher *bwc_matcher =3D bwc_rule->bwc_matcher; @@ -425,8 +491,8 @@ int mlx5hws_bwc_rule_destroy_simple(struct mlx5hws_bwc_= rule *bwc_rule) mutex_lock(queue_lock); =20 ret =3D hws_bwc_rule_destroy_hws_sync(bwc_rule, &attr); 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Thu, 19 Jun 2025 04:56:00 -0700 From: Mark Bloch To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Leon Romanovsky , Jonathan Corbet , , , , , Moshe Shemesh , Yevgeny Kliteynik , Mark Bloch Subject: [PATCH net-next 8/8] net/mlx5: Add HWS as secondary steering mode Date: Thu, 19 Jun 2025 14:55:22 +0300 Message-ID: <20250619115522.68469-9-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250619115522.68469-1-mbloch@nvidia.com> References: <20250619115522.68469-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F3:EE_|DM4PR12MB6397:EE_ X-MS-Office365-Filtering-Correlation-Id: 4ffa70bf-638b-4b6b-8c68-08ddaf284936 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?wRh7XIPZKSAo9YrlRHx16ujl82S4UNzH7hMMLO1F0h8kbrolasn9XTlLAaQf?= =?us-ascii?Q?x6UlsUv738rLbVv6elvpZJA605UTD5NVr+3jQOgpaOPRcRfGXcY9Qeg/Cnly?= =?us-ascii?Q?crm4bZoQ1JuvfNVP3XSa9d23UzfkVGCZ/WxZWtyEFwF+vtdH7DIiudUjDgfS?= =?us-ascii?Q?AqVWwXsY6TutipZrWpJEGvKSgPacSW9KammcyPjIIZcC8k7eKSdF9f8Z4pWL?= =?us-ascii?Q?kcKvUZab9yNiqmd35ysFMZoUu5ZTPK7lUSKA7lB76Di6bzwuX93xqeSKbV12?= =?us-ascii?Q?TrkVQPPpdJFVP+5cObSz1K9LH89+wbbjJe81GkrUiXQxLrxSVymGG+XYOp05?= =?us-ascii?Q?ymNrO9MVbhHTBydZecyFmlEL/Vzv1Oebfr5beWpJNGwMLOwL59ayjpr3b1zr?= =?us-ascii?Q?vsEAViyjXLS1rw9cKzSsbAMGGYyj/u9jpV6qVT+NCJGOW/FZwBSCXe0rs6Rg?= =?us-ascii?Q?j7iW6KluBFIYm+VtneOBAfBa4ca7BMu9FAOefQ0EkGhZbchXs36wn/uwS7wI?= =?us-ascii?Q?L8jeav0EC6JKNwtdp8S9gluINQojVvgLoVw7Bf/Clb1eHmsn5np+pRppW61Y?= =?us-ascii?Q?mSm/sAYFkaFeDuAf5op9Y3bKUlkGEw/QJcyHlwi7LzbA/Nb5wMXhd7GCJuv0?= =?us-ascii?Q?aj7vSE3PPdeHgLEqD40tjjkCTzzWEUGKe9KD/jVIb2B8aajqGfub9zclaBMR?= =?us-ascii?Q?ZxsRxbF/Bp131RXBTg+ffabMwwFZfI7rPRq1n+NvRC4lLOXzPaqnaFgu8KVt?= =?us-ascii?Q?OreVpjwYhKGgJbXqt8m2HXoxzTVfZOx6bPBpCITBbdv3DG3wlPQevTY3liL3?= =?us-ascii?Q?zz8rdsHuP2qVueOQB8b1I1esNW7YT9H/uvkrlDzcQBbT+8dEHFvlAqTlm8MS?= =?us-ascii?Q?ZvygqMCMdPtlFwGq7YPMh0nd1dGsuCLq3v4b2dYqwJD/l+MTrwfPuAXEJEAZ?= =?us-ascii?Q?Xq7J3QJf0QVImpmebQoM1Vp8I6XgUQgANwoxJUmYI6lwtUjwAoTw9ljwpl/r?= =?us-ascii?Q?lBpxrGOnzumSiCrOnwCiITPCDXY2LR/f4rbvVwdBc1GrIGu+yNsia8OmcBoW?= =?us-ascii?Q?5BmQ7mtPeK3piJu+eqdD1/lxPiungt3lan3XsMbs7mUyW1Ya2ouJwwPZtqzs?= =?us-ascii?Q?oRcWJdeh1h4L8Pvv7p0UPYt+sJnz9cMFeP1LINTbM4KC6EzAd/DwGZA/EW2P?= =?us-ascii?Q?GNtTVoShybiHLE+iWbMB/TcQM6BWET7jayGSAucIEUeLZpkP3kU+NFdv2Vva?= =?us-ascii?Q?TyYNWTKa1PqIW5W7jV8nvQeCbuiEj3jolh9H2hvp7LGSOsXuktMslFR536NH?= =?us-ascii?Q?WtVrof7Eb5VCoN+1onPVXrSBuZOlW3lOEw6XqlAPvAUA5OPGrEY+J8Y00FNJ?= =?us-ascii?Q?vaqgrxK+tUdsHbKylpWfRHbgLe6K6jguf8/6TJlGA0LpJsyiQI4TUYzrU9u/?= =?us-ascii?Q?HA1qLNBqwbkpOkOmiy3l9UZC8A+tMUtaStJZfWjBx7wKy1FtnnkvJpT4Rf7H?= =?us-ascii?Q?wLen8QuxxfiOoOSevwXA3trYfTyfOpV19S0p?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2025 11:56:11.8040 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4ffa70bf-638b-4b6b-8c68-08ddaf284936 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6397 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh Add HW Steering (HWS) as a secondary option for device steering mode. If the device does not support SW Steering (SWS), HW Steering will be used as the default, provided it is supported. FW Steering will now be selected as the default only if both HWS and SWS are unavailable. Signed-off-by: Moshe Shemesh Reviewed-by: Yevgeny Kliteynik Signed-off-by: Mark Bloch --- drivers/net/ethernet/mellanox/mlx5/core/fs_core.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/fs_core.c index a8046200d376..f30fc793e1fb 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c @@ -3919,6 +3919,8 @@ int mlx5_fs_core_alloc(struct mlx5_core_dev *dev) =20 if (mlx5_fs_dr_is_supported(dev)) steering->mode =3D MLX5_FLOW_STEERING_MODE_SMFS; + else if (mlx5_fs_hws_is_supported(dev)) + steering->mode =3D MLX5_FLOW_STEERING_MODE_HMFS; else steering->mode =3D MLX5_FLOW_STEERING_MODE_DMFS; =20 --=20 2.34.1