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Thu, 19 Jun 2025 04:37:45 -0700 From: Mark Bloch To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Leon Romanovsky , Jonathan Corbet , , , , , Dragos Tatulea , Mark Bloch Subject: [PATCH net-next 5/5] net/mlx5e: Make PCIe congestion event thresholds configurable Date: Thu, 19 Jun 2025 14:37:21 +0300 Message-ID: <20250619113721.60201-6-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250619113721.60201-1-mbloch@nvidia.com> References: <20250619113721.60201-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00036F3C:EE_|DS0PR12MB9323:EE_ X-MS-Office365-Filtering-Correlation-Id: b32bed53-355f-4247-8d0d-08ddaf25bfb7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|7416014|376014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?KthX3GGuTC1gku/XclxF+/nXlrYCkORTpqykF/4+gEfVEGvdc3ht+UOIcCrA?= =?us-ascii?Q?ryv0wfw+EUJNSHJV6oAa49TTHokU13xgOSje+8wKFmJEg36HAAjM35vnz4G9?= =?us-ascii?Q?qRWkt2DoOArxN5TDrGHHIFcZM7xVSPmiGUQIXD5ZPrzl/KINQ5n+YvdNV+Nn?= =?us-ascii?Q?c0MOoSOeJ6Sz+eOaVBwnfPRVi9HXkpONI6Wd+3OW+xQ9NSkh7afuFX5ogH9l?= =?us-ascii?Q?Vd/UDrLR2MDY+JeZN7jh3fgS8uoUn84lpfO0DGjwzOxIbtcBK44uNr3EqcQz?= =?us-ascii?Q?Tk2ibFhkU//cQt/A3BxwXuM43OysrhQ/9es8lRgkYC9qgDx5Revtk+bWcSSx?= =?us-ascii?Q?yXGVpB5Yqri9yDNGkSVysEZr/PPNiDSGFZtHqyJis92QFLJerzBHBhV/bweC?= =?us-ascii?Q?3Mm9Ajz8HPvcsqVsWyWiqNtFTs7oShoZIKf7ThUx0LXJFK2i7D1MM+0bBEzo?= =?us-ascii?Q?x6kDfS5RiwOoFBpXKix9Qrt3RtfSYH457isUyNISB+51x2nShCbiSF7mnDNG?= =?us-ascii?Q?ayapppD5tj3/IFWqQ1dqawhCCoebHFMEQ5zH2Ss9LBJJYcf88iG3xkzbNvoE?= =?us-ascii?Q?t6TJMcxXO3Q6pg38cI3OTx3FlEZZsoirL+HybdAxV0dqJg+ZBmzqKv37JMzp?= =?us-ascii?Q?bluZ3zVMEQBoeVffEQZvWbXTY+rRv0ci/2ULDLg7Yg2JARayhN05pVlzo1Nr?= =?us-ascii?Q?WjAqunwhoPwnR8N+/zDJ+sE6cbeyNrp8mXtojQGPDsIoqxY408bCIHeLB56Y?= =?us-ascii?Q?tBbKn+A7Vd955D0uV5IKSK1aajhn/ngLJa6arlhNyB9+q41FMB1P73eqPKgF?= =?us-ascii?Q?2uCJ0yi9nALfjGVcl7xpV21S7Q7/41xQ/rZIvv+84pMGAsVwc9yF22MZgtUh?= =?us-ascii?Q?CMGO2kzyZiQTzWq8h6RH5nR3UKS2hg/soT/vLSE2e3YEkFBinOR5ZokuV+kB?= =?us-ascii?Q?xhy2T0KFOlyLj8IYP+MUrlXRPQTyfSSVw7rAnmxmFHOtL4n+ZhsXIgs/AEIc?= =?us-ascii?Q?3jU2pHEv1RxQunKYhvY+83m6tmJEmUIUlhtSuIbNkiQW6QRxKl81WG/nm3VW?= =?us-ascii?Q?q1TS22sU+Cp5Sx9QZQ2IuH5tuB1rrUKUbhU/B/q5YZ6ApiESlFXyRpwr6eql?= =?us-ascii?Q?LQTVFvncxX1Z7spy+eope3SomMpPXZJ7R1j0QU6BWaMobv59ec7lQsrQ+PxL?= =?us-ascii?Q?9RJ5xAxnettkuMY/QkrTkTjxrG8BnuU7foNDvq8NBba/VwGntBL3U1iR1n4x?= =?us-ascii?Q?eKDda49WU9qfD1m2dC3RB0VT0W1RstM9RoJrJX6O6bF7XvF1AwOK/f4Hj92f?= =?us-ascii?Q?SxR1cC/2+SP9WNFsEtX8ujYvMlKgC/WC9VPLEOV8rEnKpU/Sn7Y63HsCN55O?= =?us-ascii?Q?w2PoMu1i6qrSeyrWKssqs2OP9nwAfimTdS2LGR0qKg9tM2wygrp6KUJPSEWD?= =?us-ascii?Q?+wzKU2WSn5NQMe0ne4mNBqx/noQ+fRoRIlVAzusQckTnN1x9sKi3QwiKIbba?= =?us-ascii?Q?uObNTTSLNtkSMFU5dNwvxBFeG6awO8yS5eCk?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(7416014)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2025 11:38:02.0175 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b32bed53-355f-4247-8d0d-08ddaf25bfb7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F3C.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9323 Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea Add a new sysfs entry for reading and configuring the PCIe congestion event thresholds. The format is the following: Units are 0.01 %. Accepted values are in range (0, 10000]. When new thresholds are configured, a object modify operation will happen. The set function is updated accordingly to act as a modify as well. The threshold configuration is stored and queried directly in the firmware. To prevent fat fingering the numbers, read them initially as u64. Signed-off-by: Dragos Tatulea Reviewed-by: Tariq Toukan Signed-off-by: Mark Bloch --- .../mellanox/mlx5/core/en/pcie_cong_event.c | 152 +++++++++++++++++- 1 file changed, 144 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c b= /drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c index a24e5465ceeb..a74d1e15c92e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c @@ -39,9 +39,13 @@ struct mlx5e_pcie_cong_event { =20 /* For ethtool stats group. */ struct mlx5e_pcie_cong_stats stats; + + struct device_attribute attr; }; =20 /* In units of 0.01 % */ +#define MLX5E_PCIE_CONG_THRESH_MAX 10000 + static const struct mlx5e_pcie_cong_thresh default_thresh_config =3D { .inbound_high =3D 9000, .inbound_low =3D 7500, @@ -97,6 +101,7 @@ MLX5E_DEFINE_STATS_GRP(pcie_cong, 0); static int mlx5_cmd_pcie_cong_event_set(struct mlx5_core_dev *dev, const struct mlx5e_pcie_cong_thresh *config, + bool modify, u64 *obj_id) { u32 in[MLX5_ST_SZ_DW(pcie_cong_event_cmd_in)] =3D {}; @@ -108,8 +113,16 @@ mlx5_cmd_pcie_cong_event_set(struct mlx5_core_dev *dev, hdr =3D MLX5_ADDR_OF(pcie_cong_event_cmd_in, in, hdr); cong_obj =3D MLX5_ADDR_OF(pcie_cong_event_cmd_in, in, cong_obj); =20 - MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, - MLX5_CMD_OP_CREATE_GENERAL_OBJECT); + if (!modify) { + MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, + MLX5_CMD_OP_CREATE_GENERAL_OBJECT); + } else { + MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, + MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); + MLX5_SET(general_obj_in_cmd_hdr, in, obj_id, *obj_id); + MLX5_SET64(pcie_cong_event_obj, cong_obj, modify_select_field, + MLX5_PCIE_CONG_EVENT_MOD_THRESH); + } =20 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT); @@ -131,10 +144,12 @@ mlx5_cmd_pcie_cong_event_set(struct mlx5_core_dev *de= v, if (err) return err; =20 - *obj_id =3D MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); + if (!modify) + *obj_id =3D MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); =20 - mlx5_core_dbg(dev, "PCIe congestion event (obj_id=3D%llu) created. Config= : in: [%u, %u], out: [%u, %u]\n", + mlx5_core_dbg(dev, "PCIe congestion event (obj_id=3D%llu) %s. Config: in:= [%u, %u], out: [%u, %u]\n", *obj_id, + modify ? "modified" : "created", config->inbound_high, config->inbound_low, config->outbound_high, config->outbound_low); =20 @@ -160,13 +175,13 @@ static int mlx5_cmd_pcie_cong_event_destroy(struct ml= x5_core_dev *dev, =20 static int mlx5_cmd_pcie_cong_event_query(struct mlx5_core_dev *dev, u64 obj_id, - u32 *state) + u32 *state, + struct mlx5e_pcie_cong_thresh *config) { u32 in[MLX5_ST_SZ_DW(pcie_cong_event_cmd_in)] =3D {}; u32 out[MLX5_ST_SZ_DW(pcie_cong_event_cmd_out)]; void *obj; void *hdr; - u8 cong; int err; =20 hdr =3D MLX5_ADDR_OF(pcie_cong_event_cmd_in, in, hdr); @@ -184,6 +199,8 @@ static int mlx5_cmd_pcie_cong_event_query(struct mlx5_c= ore_dev *dev, obj =3D MLX5_ADDR_OF(pcie_cong_event_cmd_out, out, cong_obj); =20 if (state) { + u8 cong; + cong =3D MLX5_GET(pcie_cong_event_obj, obj, inbound_cong_state); if (cong =3D=3D MLX5E_CONG_HIGH_STATE) *state |=3D MLX5E_INBOUND_CONG; @@ -193,6 +210,19 @@ static int mlx5_cmd_pcie_cong_event_query(struct mlx5_= core_dev *dev, *state |=3D MLX5E_OUTBOUND_CONG; } =20 + if (config) { + *config =3D (struct mlx5e_pcie_cong_thresh) { + .inbound_low =3D MLX5_GET(pcie_cong_event_obj, obj, + inbound_cong_low_threshold), + .inbound_high =3D MLX5_GET(pcie_cong_event_obj, obj, + inbound_cong_high_threshold), + .outbound_low =3D MLX5_GET(pcie_cong_event_obj, obj, + outbound_cong_low_threshold), + .outbound_high =3D MLX5_GET(pcie_cong_event_obj, obj, + outbound_cong_high_threshold), + }; + } + return 0; } =20 @@ -210,7 +240,7 @@ static void mlx5e_pcie_cong_event_work(struct work_stru= ct *work) dev =3D priv->mdev; =20 err =3D mlx5_cmd_pcie_cong_event_query(dev, cong_event->obj_id, - &new_cong_state); + &new_cong_state, NULL); if (err) { mlx5_core_warn(dev, "Error %d when querying PCIe cong event object (obj_= id=3D%llu).\n", err, cong_event->obj_id); @@ -249,6 +279,101 @@ static int mlx5e_pcie_cong_event_handler(struct notif= ier_block *nb, return NOTIFY_OK; } =20 +static bool mlx5e_thresh_check_val(u64 val) +{ + return val > 0 && val <=3D MLX5E_PCIE_CONG_THRESH_MAX; +} + +static bool +mlx5e_thresh_config_check_order(const struct mlx5e_pcie_cong_thresh *confi= g) +{ + if (config->inbound_high <=3D config->inbound_low) + return false; + + if (config->outbound_high <=3D config->outbound_low) + return false; + + return true; +} + +#define MLX5E_PCIE_CONG_THRESH_SYSFS_VALUES 4 + +static ssize_t thresh_config_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct mlx5e_pcie_cong_thresh config =3D {}; + struct mlx5e_pcie_cong_event *cong_event; + u64 outbound_high, outbound_low; + u64 inbound_high, inbound_low; + struct mlx5e_priv *priv; + int ret; + int err; + + cong_event =3D container_of(attr, struct mlx5e_pcie_cong_event, attr); + priv =3D cong_event->priv; + + ret =3D sscanf(buf, "%llu %llu %llu %llu", + &inbound_low, &inbound_high, + &outbound_low, &outbound_high); + if (ret !=3D MLX5E_PCIE_CONG_THRESH_SYSFS_VALUES) { + mlx5_core_err(priv->mdev, "Invalid format for PCIe congestion threshold = configuration. Expected %d, got %d.\n", + MLX5E_PCIE_CONG_THRESH_SYSFS_VALUES, ret); + return -EINVAL; + } + + if (!mlx5e_thresh_check_val(inbound_high) || + !mlx5e_thresh_check_val(inbound_low) || + !mlx5e_thresh_check_val(outbound_high) || + !mlx5e_thresh_check_val(outbound_low)) { + mlx5_core_err(priv->mdev, "Invalid values for PCIe congestion threshold = configuration. Valid range [1, %d]\n", + MLX5E_PCIE_CONG_THRESH_MAX); + return -EINVAL; + } + + config =3D (struct mlx5e_pcie_cong_thresh) { + .inbound_low =3D inbound_low, + .inbound_high =3D inbound_high, + .outbound_low =3D outbound_low, + .outbound_high =3D outbound_high, + + }; + + if (!mlx5e_thresh_config_check_order(&config)) { + mlx5_core_err(priv->mdev, "Invalid order of values for PCIe congestion t= hreshold configuration.\n"); + return -EINVAL; + } + + err =3D mlx5_cmd_pcie_cong_event_set(priv->mdev, &config, + true, &cong_event->obj_id); + + return err ? err : count; +} + +static ssize_t thresh_config_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct mlx5e_pcie_cong_event *cong_event; + struct mlx5e_pcie_cong_thresh config; + struct mlx5e_priv *priv; + int err; + + cong_event =3D container_of(attr, struct mlx5e_pcie_cong_event, attr); + priv =3D cong_event->priv; + + err =3D mlx5_cmd_pcie_cong_event_query(priv->mdev, cong_event->obj_id, + NULL, &config); + + if (err) + return err; + + return sysfs_emit(buf, "%u %u %u %u\n", + config.inbound_low, config.inbound_high, + config.outbound_low, config.outbound_high); +} + bool mlx5e_pcie_cong_event_supported(struct mlx5_core_dev *dev) { u64 features =3D MLX5_CAP_GEN_2_64(dev, general_obj_types_127_64); @@ -283,7 +408,7 @@ int mlx5e_pcie_cong_event_init(struct mlx5e_priv *priv) cong_event->priv =3D priv; =20 err =3D mlx5_cmd_pcie_cong_event_set(mdev, &default_thresh_config, - &cong_event->obj_id); + false, &cong_event->obj_id); if (err) { mlx5_core_warn(mdev, "Error creating a PCIe congestion event object\n"); goto err_free; @@ -295,10 +420,20 @@ int mlx5e_pcie_cong_event_init(struct mlx5e_priv *pri= v) goto err_obj_destroy; } =20 + cong_event->attr =3D (struct device_attribute)__ATTR_RW(thresh_config); + err =3D sysfs_create_file(&mdev->device->kobj, + &cong_event->attr.attr); + if (err) { + mlx5_core_warn(mdev, "Error creating a sysfs entry for pcie_cong limits.= \n"); + goto err_unregister_nb; + } + priv->cong_event =3D cong_event; =20 return 0; =20 +err_unregister_nb: + mlx5_eq_notifier_unregister(mdev, &cong_event->nb); err_obj_destroy: mlx5_cmd_pcie_cong_event_destroy(mdev, cong_event->obj_id); err_free: @@ -316,6 +451,7 @@ void mlx5e_pcie_cong_event_cleanup(struct mlx5e_priv *p= riv) return; =20 priv->cong_event =3D NULL; + sysfs_remove_file(&mdev->device->kobj, &cong_event->attr.attr); =20 mlx5_eq_notifier_unregister(mdev, &cong_event->nb); cancel_work_sync(&cong_event->work); --=20 2.34.1