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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Leon Romanovsky , Jonathan Corbet , , , , , Dragos Tatulea , Mark Bloch Subject: [PATCH net-next 4/5] net/mlx5e: Add device PCIe congestion ethtool stats Date: Thu, 19 Jun 2025 14:37:20 +0300 Message-ID: <20250619113721.60201-5-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250619113721.60201-1-mbloch@nvidia.com> References: <20250619113721.60201-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD7:EE_|LV3PR12MB9437:EE_ X-MS-Office365-Filtering-Correlation-Id: b7105d3d-d9d1-44f4-4ba8-08ddaf25b96c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?SSkCN+QxztGLPgzzezXzRMOMGUdSleSuoWgFNFPS44OkqCBzOIjXu60S+J9i?= =?us-ascii?Q?uz/p9xZp2DTD7aMTcOVzem7w2cZXF9GSLUpOFPQ5Z+cvl3uV0wO8OMCnOMHM?= =?us-ascii?Q?Jhv3+O7nBwz/PTJIUpjtZR8/X1RWRYeVoxBc78CdwQ7xC0yPTUJ7kmrboxqK?= =?us-ascii?Q?2d9M/IhV0fW5cYb4s3p57p/gj25fHx4AKPDJwhw0TEBpN6j5y5IPmbAk7237?= =?us-ascii?Q?X7moWE6iLjrPH19j4JcLpqGcIjJ7GUPuoX6C3e6NGzyTsDPWQa4ZSOqjLL62?= =?us-ascii?Q?PxHxSAs9kbAknf/aQCLLrxjAQ16oHDJgllWO/b30r4Vlfh2O31LvjpFIBtwo?= =?us-ascii?Q?Fq91tw1sn+XplcHg3zGWNHDNMKSzq9duKLfE3uaEyzz+UPmT3NNElw2RjJB3?= =?us-ascii?Q?HU6Bf/o3ZMIi70GByQiYRrAQ+yRCgMOjrslkzq1br53pglZ33z3/nxMj9QsS?= =?us-ascii?Q?hSKz4FUyXX7AO7BxAUUe1zzuYrvKuY8e+KkPU4tx8HIlgZ2VYae3fk7x4D+f?= =?us-ascii?Q?GNYPs8hrQbqtCm2Kw3JEUmbi4Ipe3g1c/Hv1umFLUYu68e9q6EY/2ww3uNKU?= =?us-ascii?Q?Z78Ts/fImyAThwi9lA5fOObNeF1e6xRl7c23XCFlzbefST0mxaH0+VXJ6WD3?= =?us-ascii?Q?riF7K/qIoK0NIj/ND1HvoNpZ7q6KxFuyVjwf53Fn/zeFLa+u6OtwJ72rbdvZ?= =?us-ascii?Q?X2c3SxLaj7j2JlVj+75hN6KzQGnt4JmIvEkGLqomhL6NGEFGo0neCOLf/0+x?= =?us-ascii?Q?55wpOxVz7xNc4Hv/jUILMBq51cdDT0vFlXOhdXBiL/WqqQVFEV2/hoHlqWsh?= =?us-ascii?Q?Ki5iEdYKiW32FjhjWghPqB3cOVyxH9uMpr3y5S7DP+1QfQzlzZAc3Z+YoTuK?= =?us-ascii?Q?hgqf+M4vEARgAOVYL96It15OumBQjtUXNHMCSILdan+vayL2wqSFNQgXxqB9?= =?us-ascii?Q?UEMMMv72rG03FV+sR5y0yQdMzuT+VnQcCFGfLkPc3Tz5RMNF5mOr1qp+th4E?= =?us-ascii?Q?ZXRw0BYsJyzCkJ9tlhoQtBHFxb/htTqY7wVqM1l6PEVAX9CT7kGkYubRdj7V?= =?us-ascii?Q?qHLBZ4DFLLbn9olJrSjzdhE0lv2thst37YOwZlsNsj6TY1cI2f7U5W+LEI21?= =?us-ascii?Q?+Vh3bce2Zozy3u7QI2+hvlvfyw2JViieuwJAfxLN7ocfK6Uk6EjobHh0lG+G?= =?us-ascii?Q?RotmPJWw2GfONEKs7DLyMh5i17aiYJonVcJOMmj4X4pzNGNyWDCVaVYTgTXr?= =?us-ascii?Q?XwuTCIuc5VePVcbnbk8NtctpDtwGY5b4RuCGha+hXl7Q/Sn0pNkzt3IyQQde?= =?us-ascii?Q?EfRIl/ZvZDZ3q1/fFs/T2tNlaQXlSS6A9o8dHsZ6gHSXoOgHd3aVeBwNzJst?= =?us-ascii?Q?26CUpqb7qFsOgmjz2mB1whmGf0O7KB/dj6ZAD7zKw8XL7Ks1wWO+MhsI5Bad?= =?us-ascii?Q?zb4fNQlUpRXA/U7kOHjp/P2euQKuNLK7cu5sYtVckNkVS8aY24n/akmA2fVz?= =?us-ascii?Q?vdVZkUKgue1KHVzJJ8xMsdR3rWZSs+dhb3n+?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2025 11:37:51.5002 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b7105d3d-d9d1-44f4-4ba8-08ddaf25b96c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9437 Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea Implement the PCIe Congestion Event notifier which triggers a work item to query the PCIe Congestion Event object. The result of the congestion state is reflected in the new ethtool stats: * pci_bw_inbound_high: the device has crossed the high threshold for inbound PCIe traffic. * pci_bw_inbound_low: the device has crossed the low threshold for inbound PCIe traffic * pci_bw_outbound_high: the device has crossed the high threshold for outbound PCIe traffic. * pci_bw_outbound_low: the device has crossed the low threshold for outbound PCIe traffic The high and low thresholds are currently configured at 90% and 75%. These are hysteresis thresholds which help to check if the PCI bus on the device side is in a congested state. If low + 1 =3D high then the device is in a congested state. If low =3D=3D = high then the device is not in a congested state. The counters are also documented. A follow-up patch will make the thresholds configurable. Signed-off-by: Dragos Tatulea Reviewed-by: Tariq Toukan Signed-off-by: Mark Bloch --- .../ethernet/mellanox/mlx5/counters.rst | 32 ++++ .../mellanox/mlx5/core/en/pcie_cong_event.c | 175 ++++++++++++++++++ .../ethernet/mellanox/mlx5/core/en_stats.c | 1 + .../ethernet/mellanox/mlx5/core/en_stats.h | 1 + drivers/net/ethernet/mellanox/mlx5/core/eq.c | 4 + 5 files changed, 213 insertions(+) diff --git a/Documentation/networking/device_drivers/ethernet/mellanox/mlx5= /counters.rst b/Documentation/networking/device_drivers/ethernet/mellanox/m= lx5/counters.rst index 43d72c8b713b..754c81436408 100644 --- a/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/counte= rs.rst +++ b/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/counte= rs.rst @@ -1341,3 +1341,35 @@ Device Counters - The number of times the device owned queue had not enough buffers allocated. - Error + + * - `pci_bw_inbound_high` + - The number of times the device crossed the high inbound pcie bandwi= dth + threshold. To be compared to pci_bw_inbound_low to check if the dev= ice + is in a congested state. + If pci_bw_inbound_high =3D=3D pci_bw_inbound_low then the device is= not congested. + If pci_bw_inbound_high > pci_bw_inbound_low then the device is cong= ested. + - Tnformative + + * - `pci_bw_inbound_low` + - The number of times the device crossed the low inbound PCIe bandwid= th + threshold. To be compared to pci_bw_inbound_high to check if the de= vice + is in a congested state. + If pci_bw_inbound_high =3D=3D pci_bw_inbound_low then the device is= not congested. + If pci_bw_inbound_high > pci_bw_inbound_low then the device is cong= ested. + - Informative + + * - `pci_bw_outbound_high` + - The number of times the device crossed the high outbound pcie bandw= idth + threshold. To be compared to pci_bw_outbound_low to check if the de= vice + is in a congested state. + If pci_bw_outbound_high =3D=3D pci_bw_outbound_low then the device = is not congested. + If pci_bw_outbound_high > pci_bw_outbound_low then the device is co= ngested. + - Informative + + * - `pci_bw_outbound_low` + - The number of times the device crossed the low outbound PCIe bandwi= dth + threshold. To be compared to pci_bw_outbound_high to check if the d= evice + is in a congested state. + If pci_bw_outbound_high =3D=3D pci_bw_outbound_low then the device = is not congested. + If pci_bw_outbound_high > pci_bw_outbound_low then the device is co= ngested. + - Informative diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c b= /drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c index 95a6db9d30b3..a24e5465ceeb 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c @@ -4,6 +4,13 @@ #include "en.h" #include "pcie_cong_event.h" =20 +#define MLX5E_CONG_HIGH_STATE 0x7 + +enum { + MLX5E_INBOUND_CONG =3D BIT(0), + MLX5E_OUTBOUND_CONG =3D BIT(1), +}; + struct mlx5e_pcie_cong_thresh { u16 inbound_high; u16 inbound_low; @@ -11,10 +18,27 @@ struct mlx5e_pcie_cong_thresh { u16 outbound_low; }; =20 +struct mlx5e_pcie_cong_stats { + u32 pci_bw_inbound_high; + u32 pci_bw_inbound_low; + u32 pci_bw_outbound_high; + u32 pci_bw_outbound_low; +}; + struct mlx5e_pcie_cong_event { u64 obj_id; =20 struct mlx5e_priv *priv; + + /* For event notifier and workqueue. */ + struct work_struct work; + struct mlx5_nb nb; + + /* Stores last read state. */ + u8 state; + + /* For ethtool stats group. */ + struct mlx5e_pcie_cong_stats stats; }; =20 /* In units of 0.01 % */ @@ -25,6 +49,51 @@ static const struct mlx5e_pcie_cong_thresh default_thres= h_config =3D { .outbound_low =3D 7500, }; =20 +static const struct counter_desc mlx5e_pcie_cong_stats_desc[] =3D { + { MLX5E_DECLARE_STAT(struct mlx5e_pcie_cong_stats, + pci_bw_inbound_high) }, + { MLX5E_DECLARE_STAT(struct mlx5e_pcie_cong_stats, + pci_bw_inbound_low) }, + { MLX5E_DECLARE_STAT(struct mlx5e_pcie_cong_stats, + pci_bw_outbound_high) }, + { MLX5E_DECLARE_STAT(struct mlx5e_pcie_cong_stats, + pci_bw_outbound_low) }, +}; + +#define NUM_PCIE_CONG_COUNTERS ARRAY_SIZE(mlx5e_pcie_cong_stats_desc) + +static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(pcie_cong) +{ + return priv->cong_event ? NUM_PCIE_CONG_COUNTERS : 0; +} + +static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(pcie_cong) {} + +static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(pcie_cong) +{ + if (!priv->cong_event) + return; + + for (int i =3D 0; i < NUM_PCIE_CONG_COUNTERS; i++) + ethtool_puts(data, mlx5e_pcie_cong_stats_desc[i].format); +} + +static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(pcie_cong) +{ + if (!priv->cong_event) + return; + + for (int i =3D 0; i < NUM_PCIE_CONG_COUNTERS; i++) { + u32 ctr =3D MLX5E_READ_CTR32_CPU(&priv->cong_event->stats, + mlx5e_pcie_cong_stats_desc, + i); + + mlx5e_ethtool_put_stat(data, ctr); + } +} + +MLX5E_DEFINE_STATS_GRP(pcie_cong, 0); + static int mlx5_cmd_pcie_cong_event_set(struct mlx5_core_dev *dev, const struct mlx5e_pcie_cong_thresh *config, @@ -89,6 +158,97 @@ static int mlx5_cmd_pcie_cong_event_destroy(struct mlx5= _core_dev *dev, return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); } =20 +static int mlx5_cmd_pcie_cong_event_query(struct mlx5_core_dev *dev, + u64 obj_id, + u32 *state) +{ + u32 in[MLX5_ST_SZ_DW(pcie_cong_event_cmd_in)] =3D {}; + u32 out[MLX5_ST_SZ_DW(pcie_cong_event_cmd_out)]; + void *obj; + void *hdr; + u8 cong; + int err; + + hdr =3D MLX5_ADDR_OF(pcie_cong_event_cmd_in, in, hdr); + + MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, + MLX5_CMD_OP_QUERY_GENERAL_OBJECT); + MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, + MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT); + MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, obj_id); + + err =3D mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); + if (err) + return err; + + obj =3D MLX5_ADDR_OF(pcie_cong_event_cmd_out, out, cong_obj); + + if (state) { + cong =3D MLX5_GET(pcie_cong_event_obj, obj, inbound_cong_state); + if (cong =3D=3D MLX5E_CONG_HIGH_STATE) + *state |=3D MLX5E_INBOUND_CONG; + + cong =3D MLX5_GET(pcie_cong_event_obj, obj, outbound_cong_state); + if (cong =3D=3D MLX5E_CONG_HIGH_STATE) + *state |=3D MLX5E_OUTBOUND_CONG; + } + + return 0; +} + +static void mlx5e_pcie_cong_event_work(struct work_struct *work) +{ + struct mlx5e_pcie_cong_event *cong_event; + struct mlx5_core_dev *dev; + struct mlx5e_priv *priv; + u32 new_cong_state =3D 0; + u32 changes; + int err; + + cong_event =3D container_of(work, struct mlx5e_pcie_cong_event, work); + priv =3D cong_event->priv; + dev =3D priv->mdev; + + err =3D mlx5_cmd_pcie_cong_event_query(dev, cong_event->obj_id, + &new_cong_state); + if (err) { + mlx5_core_warn(dev, "Error %d when querying PCIe cong event object (obj_= id=3D%llu).\n", + err, cong_event->obj_id); + return; + } + + changes =3D cong_event->state ^ new_cong_state; + if (!changes) + return; + + cong_event->state =3D new_cong_state; + + if (changes & MLX5E_INBOUND_CONG) { + if (new_cong_state & MLX5E_INBOUND_CONG) + cong_event->stats.pci_bw_inbound_high++; + else + cong_event->stats.pci_bw_inbound_low++; + } + + if (changes & MLX5E_OUTBOUND_CONG) { + if (new_cong_state & MLX5E_OUTBOUND_CONG) + cong_event->stats.pci_bw_outbound_high++; + else + cong_event->stats.pci_bw_outbound_low++; + } +} + +static int mlx5e_pcie_cong_event_handler(struct notifier_block *nb, + unsigned long event, void *eqe) +{ + struct mlx5e_pcie_cong_event *cong_event; + + cong_event =3D mlx5_nb_cof(nb, struct mlx5e_pcie_cong_event, nb); + queue_work(cong_event->priv->wq, &cong_event->work); + + return NOTIFY_OK; +} + bool mlx5e_pcie_cong_event_supported(struct mlx5_core_dev *dev) { u64 features =3D MLX5_CAP_GEN_2_64(dev, general_obj_types_127_64); @@ -116,6 +276,10 @@ int mlx5e_pcie_cong_event_init(struct mlx5e_priv *priv) if (!cong_event) return -ENOMEM; =20 + INIT_WORK(&cong_event->work, mlx5e_pcie_cong_event_work); + MLX5_NB_INIT(&cong_event->nb, mlx5e_pcie_cong_event_handler, + OBJECT_CHANGE); + cong_event->priv =3D priv; =20 err =3D mlx5_cmd_pcie_cong_event_set(mdev, &default_thresh_config, @@ -125,10 +289,18 @@ int mlx5e_pcie_cong_event_init(struct mlx5e_priv *pri= v) goto err_free; } =20 + err =3D mlx5_eq_notifier_register(mdev, &cong_event->nb); + if (err) { + mlx5_core_warn(mdev, "Error registering notifier for the PCIe congestion= event\n"); + goto err_obj_destroy; + } + priv->cong_event =3D cong_event; =20 return 0; =20 +err_obj_destroy: + mlx5_cmd_pcie_cong_event_destroy(mdev, cong_event->obj_id); err_free: kvfree(cong_event); =20 @@ -145,6 +317,9 @@ void mlx5e_pcie_cong_event_cleanup(struct mlx5e_priv *p= riv) =20 priv->cong_event =3D NULL; =20 + mlx5_eq_notifier_unregister(mdev, &cong_event->nb); + cancel_work_sync(&cong_event->work); + if (mlx5_cmd_pcie_cong_event_destroy(mdev, cong_event->obj_id)) mlx5_core_warn(mdev, "Error destroying PCIe congestion event (obj_id=3D%= llu)\n", cong_event->obj_id); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c b/drivers/n= et/ethernet/mellanox/mlx5/core/en_stats.c index 19664fa7f217..87536f158d07 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c @@ -2612,6 +2612,7 @@ mlx5e_stats_grp_t mlx5e_nic_stats_grps[] =3D { #ifdef CONFIG_MLX5_MACSEC &MLX5E_STATS_GRP(macsec_hw), #endif + &MLX5E_STATS_GRP(pcie_cong), }; =20 unsigned int mlx5e_nic_stats_grps_num(struct mlx5e_priv *priv) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h b/drivers/n= et/ethernet/mellanox/mlx5/core/en_stats.h index def5dea1463d..72dbcc1928ef 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h @@ -535,5 +535,6 @@ extern MLX5E_DECLARE_STATS_GRP(ipsec_hw); extern MLX5E_DECLARE_STATS_GRP(ipsec_sw); extern MLX5E_DECLARE_STATS_GRP(ptp); extern MLX5E_DECLARE_STATS_GRP(macsec_hw); +extern MLX5E_DECLARE_STATS_GRP(pcie_cong); =20 #endif /* __MLX5_EN_STATS_H__ */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eq.c b/drivers/net/eth= ernet/mellanox/mlx5/core/eq.c index dfb079e59d85..db54f6d26591 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eq.c @@ -21,6 +21,7 @@ #include "pci_irq.h" #include "devlink.h" #include "en_accel/ipsec.h" +#include "en/pcie_cong_event.h" =20 enum { MLX5_EQE_OWNER_INIT_VAL =3D 0x1, @@ -585,6 +586,9 @@ static void gather_async_events_mask(struct mlx5_core_d= ev *dev, u64 mask[4]) async_event_mask |=3D (1ull << MLX5_EVENT_TYPE_OBJECT_CHANGE); =20 + if (mlx5e_pcie_cong_event_supported(dev)) + async_event_mask |=3D (1ull << MLX5_EVENT_TYPE_OBJECT_CHANGE); + mask[0] =3D async_event_mask; =20 if (MLX5_CAP_GEN(dev, event_cap)) --=20 2.34.1