From nobody Thu Oct 9 06:52:48 2025 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2063.outbound.protection.outlook.com [40.107.94.63]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B624322FE02; Thu, 19 Jun 2025 11:37:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.94.63 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750333069; cv=fail; b=izb6reOJjYeOnxKTWC9BmBn2u1x+7B2Xf295CG8sEM4EfyjMz1zcA7eG9U97VCZhxTiKeZpFazkT/aey2X3CB5bSGedb2Wcxw6ag6gVJfOGlDQgdekTr3XttqDVe11oc632WJ2sZgBVQDVZcqHX/BcHaa0xXOoQMYAz6san1j3g= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750333069; c=relaxed/simple; bh=Z95TPb9PRFN6Vdu7kG+TIojHGktb5kF6ijGqEWNlmi4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=W0MU63hqf8oXV+4TzzB5hRC4FK1v88uJnPgpy1XGZTtYsgSWWrn7SnP0s3mdkSAPDWRgPZNP5/TFYbQ6/I17I9jGmzIHnMFhGFnsYYPBlMpwfkXbH8OvXzOwPFrJynXk6b0wSHHzdwNQlz9MFfR4Dy4X+pDxXs5fLHfRfHDntrI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=MLQhP5kU; arc=fail smtp.client-ip=40.107.94.63 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="MLQhP5kU" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=EDhx9sxI/Z751smcu5ZPHzGGMC42AnmJv79HC9ch5en+PQ65r/UZSsfa+IUOPT8AdRHDag0PjqjCpbJHUUD0H/fBwpobCIQr9vW6kbxx/P9/yH9l1AucCPA66cUmn3HMZIVO3y/bbymz1/llMlHYxVL6xZZdi0aJucCuVDKQcF4iDGMiSd2fjmQzqpwawe1S5Lw88SfaJIIvrIHLmae4MnffcZGdcgHVlFKyDoDMxfBc8KO+z6rQFm22YSyLTLa8+LM3hHGQWjQZJN8Yrpx0vVVRpbAQo+7Q+4hViJJpndy3h2IdsGkBtfbS86hrlrcpqksbXrP0gXmPc4wQuNDx6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=jGMbsJQc2tZS9ACKiFpq7/FrBhMZOAgT3zvUuXRBgAc=; b=DLBhBdHvifanhzY0afHE4eTW/nqHSGoxSNqUOabRFhmVHSWWfOnOXlNcJAShbbqB3R/rNzZvD6aou27Q3T5xOAfmk+LVpxQWxTiAWXoXgcWPPNj/SWwKtZgO6ZB8yh1Sz9s5iISO9UkjEOza0ezcN+8gX/TgvuxpOZzVvTQzHTNBI6rf4LjNAL7EMgp99e3NaRbCDI/WjurEjvIiy6Tw17qSOxsu65FB2ret06PWGNgLRDuUTX6WNPzTNZJLExSu7zsGr0KO9Nk1Hs+Bh00Bea0v7xdpxkVx8s64z0DHbxAgtXCNpC7gQ9rBfE2TN+Q2uZeoA2mkXuXt2AgHg7fjTQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=davemloft.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jGMbsJQc2tZS9ACKiFpq7/FrBhMZOAgT3zvUuXRBgAc=; b=MLQhP5kU8qY8BCazykBtkTrG4QgSTho3CkY1uPP5f/0Zs6AqyV3z1WEb7pDJ9n6v9bflyU2Jy6IF6rlEgX3EpOZ5E21qmh/W2TPNVmvuhUpsy9q/CP2xb7kWY4GcoQGxYBJF0KX45WkLm2AfO/vRC1RGP6CiLP0xBKxpWoFMSxlN84Q9cqNQkJy6kW8j4DIcSN0Sc5UMYj2Dv9U7IINp1RZdjo3lUn08u8VEd2lgj93HcqPDK8mkWpkncuY9zkAU8PPlYVAJdgQl9CuNpmhrzJPc8yCW2/4IXhonlwke/EqW7JcRHodDGQO/VaqAkH5yq+2bJ2wPlyVPol1LD4vhNQ== Received: from DM6PR06CA0097.namprd06.prod.outlook.com (2603:10b6:5:336::30) by SA1PR12MB8744.namprd12.prod.outlook.com (2603:10b6:806:38c::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8835.29; Thu, 19 Jun 2025 11:37:43 +0000 Received: from CY4PEPF0000EDD6.namprd03.prod.outlook.com (2603:10b6:5:336:cafe::1c) by DM6PR06CA0097.outlook.office365.com (2603:10b6:5:336::30) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8835.34 via Frontend Transport; Thu, 19 Jun 2025 11:37:42 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by CY4PEPF0000EDD6.mail.protection.outlook.com (10.167.241.202) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8857.21 via Frontend Transport; Thu, 19 Jun 2025 11:37:42 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 19 Jun 2025 04:37:32 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Thu, 19 Jun 2025 04:37:31 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Thu, 19 Jun 2025 04:37:27 -0700 From: Mark Bloch To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Leon Romanovsky , Jonathan Corbet , , , , , Dragos Tatulea , Mark Bloch Subject: [PATCH mlx5-next 1/5] net/mlx5: Small refactor for general object capabilities Date: Thu, 19 Jun 2025 14:37:17 +0300 Message-ID: <20250619113721.60201-2-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250619113721.60201-1-mbloch@nvidia.com> References: <20250619113721.60201-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD6:EE_|SA1PR12MB8744:EE_ X-MS-Office365-Filtering-Correlation-Id: 1dbc9873-2762-4ab8-9489-08ddaf25b442 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?/u/ZckQSR9IdGEVrYVR+TSRtXA0iaASeOxsd7KjvEgXMfRL6ivFcZXf//Vzs?= =?us-ascii?Q?otTvcgpg2FiCEQnnr4jpUHm44N326baZMa/1q6+Y0Om51pBiG5AJsK8Qd/5f?= =?us-ascii?Q?Gy9bttOar4I1fOOkAoE/aA4mXrfL6LR9y46bfkAHO8F1+j++CY10K7ME8u6k?= =?us-ascii?Q?qYWQqRrusIrPYyxnTSCbSritozGGkr8WwnAlrBHiqvzABobGT7PrdFDz815y?= =?us-ascii?Q?+nxOjC0ccF7/PMSn6JFETTZ4SheTyaCJQqGYT2S4Ju/to4oyBILJb1kbeBsK?= =?us-ascii?Q?Bh4OgVRAQ2Hje+09eQmg+1Av4KDY+HsrwE81ICgP0Co67hRaxLjFaY0WWWW/?= =?us-ascii?Q?cBVXDkLGCqzxm0FwgLIfW9J6X1gy61lXBz57kcB+XGLisl1POGYCLuRlGj8n?= =?us-ascii?Q?YTlk1BUtaNy2gO9mSbLsMADfOliQgrirJ4PLHlmyKi1R30W2sp+hu/PpOo1d?= =?us-ascii?Q?mX8lDHIIPXnCWSfJoEn2gkLWvwB/ikmV311MUBGi27RazVeiLKRUKgKxtII1?= =?us-ascii?Q?i2mxTPjr7TgE9rbKQpdPyUMTIw9fk7FgZgo7wj9tNp3eswxD7mqUwW0Am+xB?= =?us-ascii?Q?ebW2F7Sk1BUE1inJI2k3DXg25CZgMR3KeO0kJAyv70tjy/AcqxWRPKi4WcWi?= =?us-ascii?Q?wrLF4mMYiJ+E6Sy4oWx/oTu5Qrg+ccgy4Ny5Nhrd5iX3IbXAXvuNM/bscb8v?= =?us-ascii?Q?v+SY9Yumoh5BvWmvy5ejK9dDUYERknPSERgAniH/eyt/+zWbqKEVS/nyVuVs?= =?us-ascii?Q?JggVHge1meo9/TB2hVmDT8bSfu/tOdfdJY4US6xwH/ACyIqjrhPs8vFMffzE?= =?us-ascii?Q?rY6+PBKvzDh8FWDQD78Xbi7DJ1qeKBY+esykprMVGHx1iPBh7LSqYJD1hl8O?= =?us-ascii?Q?rhTuucJq13qS7lNcZX3kljKeBq8ylqcQRKtXrh/4sl1jjZgfF4gA88cqdvJE?= =?us-ascii?Q?ZnhBt37jgf024RUBnEUHzeR6XoJCHLEVw2aq9yG+JoZNAB8e3CW+kCZMaLjz?= =?us-ascii?Q?zhKKjQ5090eK3zPNBEPKdEk47UayKR2KfzRCLr5CRi5aDUTsl4bQ3W7arFPF?= =?us-ascii?Q?p2ZFjlALXzou+vP3euy8VqvS0xlJWY1s6WYZqS8A8vL+amlBTocXWfh7+QbA?= =?us-ascii?Q?wu34tyIOaJm03t73dHw7OyqZh4yXz9WsK3D7MJVAMghMa7wIBVmKElxlwVjg?= =?us-ascii?Q?W7cMF/LxgnNTx6aFrj6vFsTj4g8yZNfRDyfL8/u8nWD7oGl67BKOofy+Xr53?= =?us-ascii?Q?JOIKJUmtYnBin9cY+hSm/fnNHzujzlhNhfbVUFeZdm7LKUo/MbM5mlo+QdPl?= =?us-ascii?Q?E4HAxvz5ADA+vzh5Q1hPvJI3m/nbKdt6rum2ilIuyyQZUEkyug5JAXpYBl5K?= =?us-ascii?Q?Abup+Eu07ZWStmzVnTFgSEAQXAvLjxqwDYPZiQl1YOmlNrMRwGN655o4tNBE?= =?us-ascii?Q?JFC2k3WWD6p85bDH9YcPvgISK4wM4Ax3OSQYcbEG1nBy3+8tbzKxsGF9KTTA?= =?us-ascii?Q?9I6Gl8s9CwqsjuP54JgpV1v4HB7wD8o9Z5Dt?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2025 11:37:42.8207 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1dbc9873-2762-4ab8-9489-08ddaf25b442 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD6.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8744 Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea Make enum for capability bits of general object types depend on the type definitions themselves. Make sure that capabilities in the [64,127] bit range are properly calculated (type id - 64). Signed-off-by: Dragos Tatulea Reviewed-by: Tariq Toukan Signed-off-by: Mark Bloch --- include/linux/mlx5/mlx5_ifc.h | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 2c09df4ee574..5c8f75605eac 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -12501,17 +12501,6 @@ struct mlx5_ifc_affiliated_event_header_bits { u8 obj_id[0x20]; }; =20 -enum { - MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY =3D BIT_ULL(0xc), - MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC =3D BIT_ULL(0x13), - MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER =3D BIT_ULL(0x20), - MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO =3D BIT_ULL(0x24), -}; - -enum { - MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL =3D BIT_ULL(0x13), -}; - enum { MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY =3D 0xc, MLX5_GENERAL_OBJECT_TYPES_IPSEC =3D 0x13, @@ -12523,6 +12512,22 @@ enum { MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS =3D 0xff15, }; =20 +enum { + MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY =3D + BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY), + MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC =3D + BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_IPSEC), + MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER =3D + BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_SAMPLER), + MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO =3D + BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO), +}; + +enum { + MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL =3D + BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL - 0x40), +}; + enum { MLX5_IPSEC_OBJECT_ICV_LEN_16B, }; --=20 2.34.1 From nobody Thu Oct 9 06:52:48 2025 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2074.outbound.protection.outlook.com [40.107.223.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 860E423B628; Thu, 19 Jun 2025 11:37:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.223.74 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750333073; cv=fail; b=ZT7FAH5GE1bMF7QvvgpYm1vuu7wMgY7dLHNsiL1octqVLy0ZNcRnlJR7pdqEymh96ViYrZ6g9uyjBMrK8tXmmXFB+Om/uf0YGfN38HPGLFs/9KzB8ROfXwes4qlp3Rk8oCD9JxQBeUmw1aEJBI8b74OZnGhqqDDHNmZ42VjHmkg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750333073; c=relaxed/simple; bh=zf/qBt5wEoOUX3Jt/Be/avjCf0anEwTXtB8fvTPthF0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hxk0/O3t8aT7RxAQBXTe1GTWk+i2bQHWacXPTGkqTR15S11F4wRkP/YEFwS/dQeBF1jfd9aLEIO1r+H9a9GGGv10H08ZieSrMneg0LE0UBLb9fndeHbCTvLfVuKN3uCtIygOKc2LQsjPXn/rXAxR6uBe8jXvCDtcvuN7yeezRtQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=n4PNPyqQ; arc=fail smtp.client-ip=40.107.223.74 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="n4PNPyqQ" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=pt9COKUK3tVOOIWew8krNnfum3K8VUd6JBRfXwZd05vXEumrbba3O1oShtenFWD7bwxXKYLAQR6EFWkpW4X8d+ACX7QxOQY8WQSTcb6lBAhOpZLnBRsyI8hj1/5IFaunIMEC4NzZZUqjKU8rfH4KvMoOVwQzFDWG3z0v9Ibc5ssTVVUohBRQapzFK/qkxkJLEX5AnLYTX+JFF/HZO1rMgAGRONUrITFzI0GuEfrIrkgyq/4aF0CNUVWCF2omLXUaRLOWFWE0KM84qM7LTEbUF8yO37cBpihY/flBDhX8ENBngU46N3LwlRGyT7aODNKwDytHIV381MzVCVP6DxO7BA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=5YLdx1uK6O2Djb6C4o61ns60JoQSKkpUeeqLjIILdIU=; b=pvQEqBscpJRiLrec22O+4lTyS9mKjCDv/7IDOjXfE81PUhPgpFvmIfSNJ6mFK1RDqv3rV1wD0r2scQQnKz/dVnCqR2iClyZL48m+dTBnJ4hT82xmb4NVCi1K9e0gX92gNxpHXODXoIEi3lfVZpfgMJvGoFJDYj3+LLLof7nw14yFc/a2/HI32dCtK/sDxqm4Od5R6ecUI8A1+1dJy58IUMVKGn4ADaKwyqm1QwyaekTkrI3mM4WGshrtV5FrjJWnjsphrT91PPT/mbypfy7bUeANKZWHJ2iCCN+AokpyMMgoJPSlMpFOwvXjN+7cTjXZaD0r63b/153OUBvp8Fhw8g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=davemloft.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=5YLdx1uK6O2Djb6C4o61ns60JoQSKkpUeeqLjIILdIU=; b=n4PNPyqQ2u3hj7LpgyruXuJdClEDPmQaaB0Pqkchv22p+3oNiPs2gX3Yt9FRcwi5q3gX3aaDUdo1/QwwOrj7JHcza633TI8EndEPyo+5rT4qa9+4Awv/1ZILeoQddnPrReRCJkEYrctXLdKiiyyWPC6zQfceVTotzHl0Pp9GMIwLmjTfklb390ATmRnWalmUdrtsU5artOCeUZJ4/qTBVYTHSlRK5x3IvTLSuLVMoWc4T44NVAkQzEUTX0ACTI/6oCuIjjNlyH6076Q9/dSPjX7lqAkyJ73DSPV+TnEbGnOPfUCJDDxczuVxXBYwl7Y9YBk6RD2xBIjjQcb/SaodBA== Received: from PH0P220CA0012.NAMP220.PROD.OUTLOOK.COM (2603:10b6:510:d3::35) by SN7PR12MB8057.namprd12.prod.outlook.com (2603:10b6:806:34a::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8835.28; Thu, 19 Jun 2025 11:37:46 +0000 Received: from CY4PEPF0000EDD1.namprd03.prod.outlook.com (2603:10b6:510:d3:cafe::12) by PH0P220CA0012.outlook.office365.com (2603:10b6:510:d3::35) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8835.35 via Frontend Transport; Thu, 19 Jun 2025 11:37:46 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by CY4PEPF0000EDD1.mail.protection.outlook.com (10.167.241.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8857.21 via Frontend Transport; Thu, 19 Jun 2025 11:37:45 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 19 Jun 2025 04:37:36 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Thu, 19 Jun 2025 04:37:36 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Thu, 19 Jun 2025 04:37:32 -0700 From: Mark Bloch To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Leon Romanovsky , Jonathan Corbet , , , , , Dragos Tatulea , Mark Bloch Subject: [PATCH mlx5-next 2/5] net/mlx5: Add IFC bits for PCIe Congestion Event object Date: Thu, 19 Jun 2025 14:37:18 +0300 Message-ID: <20250619113721.60201-3-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250619113721.60201-1-mbloch@nvidia.com> References: <20250619113721.60201-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD1:EE_|SN7PR12MB8057:EE_ X-MS-Office365-Filtering-Correlation-Id: 2bdf4e26-33d8-4ef5-16f8-08ddaf25b625 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|7416014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?5PcqY1OoaJQoo9XZUZgnlJqTlB+RfBacNB/JxAIzB2KHrKfrQqaloNLWYq6Q?= =?us-ascii?Q?wiDl7V34Z04XnWG7zq4CjEPiKhYYoiTOGgycxWvFblx0BL9Fi0jvtxk+qJlh?= =?us-ascii?Q?IMGK6Xg5ycZpDDGBooQdcwGAbrUALAYgXQVfC9uZbJpQkXaw7mMrPzQFbYrv?= =?us-ascii?Q?uaopjd0gL3C3qf1lx76JvAW7LwQr5PPKtXSae6z3uW0aB8tCZ5udnxLZWiHH?= =?us-ascii?Q?sEHz6RbzAQiyiRXIeq+fGlLkJT1g7w/as9iayKsq3w5iVXNpbT/P1Q/P4rHu?= =?us-ascii?Q?sw4QV46iaQRWYEcy61MQNhJ8KDs2tt6eowx3rFPMix/fLNWSUlVVoSaNwZq0?= =?us-ascii?Q?xfVKWOx6d4x6TW7mmzafnguSuT/mM259w2SSgwL/ITEbafdESj87/WIZWQ3U?= =?us-ascii?Q?Ir+7DBSXoevU8784CdzxsY3xJbpFBIVXpoIpWJpzcYFczKvPG4/9hMCJDZTR?= =?us-ascii?Q?rhboQtJUKtzhQzdzFrQB4qTy3wPnsjK1Lq+4tGBSIJGirwHlTE9d0zeRmoOW?= =?us-ascii?Q?r+9eb3TiDlXrnIwr8QCfqjhKL/PqTPcQmX95DNQsKTH/KhozFEscxcvAinuy?= =?us-ascii?Q?d2dgVIX9nkzM4wFIFQyTTBSw8jkSg4AfV0vJxuY6G1RlS1Wf1xbjGQuO8lTQ?= =?us-ascii?Q?BjzrJHEl5VkdBs9ZKCMxg3gz80y66t2iNAzkpkNdOvSHV6JQB1d1bMBtGmCE?= =?us-ascii?Q?E5ScMn2uWziV7gs2uCLJ8DMfwcSz86VHPniR3ttNnS6krFdu9zoxXfWtteC8?= =?us-ascii?Q?QJnMvXNtx540xrH8LU0vbI4y4AigCZxA6YuPtBN3DGfAfJPpUXzxjel/WlRZ?= =?us-ascii?Q?foj6THJDupY8ZJWA3idQFICPUtto1ver6UUOm1noG6xopsaMvzBzrUjiGdFA?= =?us-ascii?Q?+DfRhwaEcLwHzYc6IHMB8o8YUR7LXymnv0S4vLVOa+3/swmcB9O7Qcc1sYd9?= =?us-ascii?Q?Mlrcx9KfQ4nYvYRKCgdSNpMFWZTA9HWYK0PXqMCE+qvmW9ZSexYx7RFiYjiE?= =?us-ascii?Q?7Jjs1DVsgVrexWNA+Mhcm7Lh+NRdpk0TrIYd7sbuyq9HvLQyyAKRFsQXHHNV?= =?us-ascii?Q?3P86Dm9uayG74/4cW6JD9+Jp4Tm8nJJE5Tb7iAdCyix8Nandh2yC8hZZwViG?= =?us-ascii?Q?kWdj7d2H3gfrf1nBE4S9Wh2VakcRJ+hBuHsYnHnqF4jXo+iZbpZC6vBajc4U?= =?us-ascii?Q?/mq1WLY9hhnU5oUcOE85C45zJVcixJT7oLawmKU7AhHfLA1MU7eJVi2zFpMW?= =?us-ascii?Q?LxDRwtVERJAREaFuOkgn7dwUMDUsCuMFy+vUy56PBjhmQEb2wZjMlhATRS/g?= =?us-ascii?Q?8JFs049I9CmWR44QbCvxj53kWIi3v8+m5yV42d/k3kBUcX4xiYjLg7AhnNzM?= =?us-ascii?Q?Mkq8iGWl2kot58T8G87/pevFI/6eCab1EwUFztZXtQEMUlE448d+eHcbYXGq?= =?us-ascii?Q?bFg18CUdj77gNp11MCmbeQBXY143sd5OS0w3tYGtWkONOowfYuRKFXrJ5SCJ?= =?us-ascii?Q?AcihokHDPctcMgTk5PXBNJhitN0F/PdnB5W/?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(7416014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2025 11:37:45.9910 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2bdf4e26-33d8-4ef5-16f8-08ddaf25b625 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD1.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8057 Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea Add definitions for the PCIe Congestion Event object and the relevant FW command structures. Signed-off-by: Dragos Tatulea Reviewed-by: Tariq Toukan Signed-off-by: Mark Bloch --- include/linux/mlx5/mlx5_ifc.h | 40 +++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 5c8f75605eac..0e93f342be09 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -12509,6 +12509,7 @@ enum { MLX5_GENERAL_OBJECT_TYPES_MACSEC =3D 0x27, MLX5_GENERAL_OBJECT_TYPES_INT_KEK =3D 0x47, MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL =3D 0x53, + MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT =3D 0x58, MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS =3D 0xff15, }; =20 @@ -12526,6 +12527,8 @@ enum { enum { MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL =3D BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL - 0x40), + MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT =3D + BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT - 0x40), }; =20 enum { @@ -13284,4 +13287,41 @@ struct mlx5_ifc_mrtcq_reg_bits { u8 reserved_at_80[0x180]; }; =20 +struct mlx5_ifc_pcie_cong_event_obj_bits { + u8 modify_select_field[0x40]; + + u8 inbound_event_en[0x1]; + u8 outbound_event_en[0x1]; + u8 reserved_at_42[0x1e]; + + u8 reserved_at_60[0x1]; + u8 inbound_cong_state[0x3]; + u8 reserved_at_64[0x1]; + u8 outbound_cong_state[0x3]; + u8 reserved_at_68[0x18]; + + u8 inbound_cong_low_threshold[0x10]; + u8 inbound_cong_high_threshold[0x10]; + + u8 outbound_cong_low_threshold[0x10]; + u8 outbound_cong_high_threshold[0x10]; + + u8 reserved_at_e0[0x340]; +}; + +struct mlx5_ifc_pcie_cong_event_cmd_in_bits { + struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; + struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj; +}; + +struct mlx5_ifc_pcie_cong_event_cmd_out_bits { + struct mlx5_ifc_general_obj_out_cmd_hdr_bits hdr; + struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj; +}; + +enum mlx5e_pcie_cong_event_mod_field { + MLX5_PCIE_CONG_EVENT_MOD_EVENT_EN =3D BIT(0), + MLX5_PCIE_CONG_EVENT_MOD_THRESH =3D BIT(2), +}; + #endif /* MLX5_IFC_H */ --=20 2.34.1 From nobody Thu Oct 9 06:52:48 2025 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2051.outbound.protection.outlook.com [40.107.244.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8C5923D2A2; Thu, 19 Jun 2025 11:37:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.244.51 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750333077; cv=fail; b=TDPrT4Bb2fTEk81Qi2FC8qRQD4fj02v5GgCl1cSgdfyUSTvZryw4m0fX8SwL/uBB9C6S48BDFN4pHaIzUpS40r/kfBJ1jaQkWcN5y/aha0CfKD9xnwz730j/zXZjlzhA5NvBuOnoalckX1NPBfgPUeCfK53GNykWyaI6eIKI7dw= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750333077; c=relaxed/simple; bh=0+4dRyW07LR4cuqCp+TZ02zGweF7z+xv/pwOl/NEtHo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DIjjBrtd9v6xxIx11ZuVXaESRozaFN+vdovM4R0qi3ZqMJgpLFY/RoqPrfmshrosmYuiEDJgihkA4TXjcHaW2IItZCL8i/GvCQICBIk9F2crZuPM26Xb1zFstwJnY1RfyuMIcil6c1XzG2Z8ZQkLL4b3V2z93io9VzdT+0gPUsM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=fN/uIWVS; arc=fail smtp.client-ip=40.107.244.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="fN/uIWVS" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=rRVQ9/lIqcaY46vL6lzznH/yeerTbl153fVW7iU2UiPlb1x1+VnZMbDGjqIciwZPtbJzXCsmODZPYscBVjyGqVKev6jD4bQ45fioIudoqAOxwVxiNxDuWwmnME/ve7G7BbH7ud8Vggc+sHi8xRPgnE4H0O2vwtn0WY2/mZ6L7sjbfPOPVTeM5J9R7t1bjbEo7q2voHqMQ5r0GaP0vD35dyLCpvhbErjO3qAG2EV6Dxh590g5O+jtMAzVNRiclI7/E/c0lNij85cfbgyItXF6jXkjyMQO5SWZo91V9cbISlW582cfLeLEpcQM6hTZOwjajBNQkXEqsgxCSBVD+Gh1DA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=VYwhkyEtZjlYM162L7LKJv6e9UKotoD6Pzxf8Ts2qbg=; b=IsYD7zNFrT/qrjgzUxI1VM6ZWRtL5hiufEC6r3hk5oXTItcSdAbTRZqfk7PMs/AYbqWVfSLghnmUrUXMUY76kltI1d3GQhEMYmvluxk+kzeeFpmbQoV7UJ50Uvr6brJk+3E0FvIykLH/FtjGGKhy74tHKdvkbY4W/RM+X9bijswQxsrM6O/QZN8MyWgiPaofJ4RK04QcZR1e2+1Rzxlpvm1SsB1+TrclX0iR6ickTlHaSMSjHKu3sAUKtdozU/7YrALoi3KrIdnbr9FhZTNPmwv3lGregR8xo8RUH3GRCZghwOff1XDoVPPj3/iDcP1gNCHHHVUwxmmtworPMeUafw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=davemloft.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=VYwhkyEtZjlYM162L7LKJv6e9UKotoD6Pzxf8Ts2qbg=; b=fN/uIWVS7edNEzwjqtUYcfM00W5IhyIdsCvA8Cv5Tde013SFCADan6oDS7JsVHrNiD/5U7LgJo9gbqQecKOAkH+L2Bvr72JyyknPtZm+iZ65muYg4dbn3tC/6b3SN02eg0UkAo2G4XsDV62Puk+cfjQ6COaPEaEG94wZAgc+ZcaE5YYyQSjl9SmOEeSVEy/IIpX1JuQbDP2mfVeXIrVzEQ2QoN2KRNS3GHEyX6yhXCmEutJZ5VSWjqFkQtov1HCG8fqGw9vXu3oAqr9dMk3QwkS+S95i6HeJhJ0qEHWI2DxKEmp9ZPGyAnxH1c8p0xbrPQqRHldDLjPeNCakBZHdXw== Received: from BYAPR02CA0042.namprd02.prod.outlook.com (2603:10b6:a03:54::19) by PH0PR12MB5679.namprd12.prod.outlook.com (2603:10b6:510:14f::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8835.29; Thu, 19 Jun 2025 11:37:50 +0000 Received: from SN1PEPF00036F3E.namprd05.prod.outlook.com (2603:10b6:a03:54:cafe::a0) by BYAPR02CA0042.outlook.office365.com (2603:10b6:a03:54::19) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8857.23 via Frontend Transport; Thu, 19 Jun 2025 11:37:49 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SN1PEPF00036F3E.mail.protection.outlook.com (10.167.248.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8857.21 via Frontend Transport; Thu, 19 Jun 2025 11:37:49 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 19 Jun 2025 04:37:41 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Thu, 19 Jun 2025 04:37:40 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Thu, 19 Jun 2025 04:37:36 -0700 From: Mark Bloch To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Leon Romanovsky , Jonathan Corbet , , , , , Dragos Tatulea , Mark Bloch Subject: [PATCH net-next 3/5] net/mlx5e: Create/destroy PCIe Congestion Event object Date: Thu, 19 Jun 2025 14:37:19 +0300 Message-ID: <20250619113721.60201-4-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250619113721.60201-1-mbloch@nvidia.com> References: <20250619113721.60201-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00036F3E:EE_|PH0PR12MB5679:EE_ X-MS-Office365-Filtering-Correlation-Id: 733d0d20-b1ae-4004-60ec-08ddaf25b822 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?8u6q7lNn1Lv6iOKGCMk8eqAmXwYiQjpKdGYVAjJSFkkso5UxOICadyw29e/K?= =?us-ascii?Q?vyVrASo1jmw8xststLFFCfgGv7jYypZxCOe0moOrLGcNmScYirSC4b2o2OOs?= =?us-ascii?Q?Ik9FuQ23aNUU/DtUz7/0VLZHFPYPl9rmvxmYYLsF+dEETQF3lIdsnTBWbCl+?= =?us-ascii?Q?rm/uFPZ6HkhwgxFTc/zO/XMxdRUJQ3c6Oq9lSIdIePJQSlzZmnr2pNhcOLFz?= =?us-ascii?Q?YiEJFRlGr/XYdQSMWr45s2WqDx79VpYoLdTZuSGUqKiNG3Hhjw3I1gkzBi8i?= =?us-ascii?Q?AwC8r+ngQ4WWnJ2UX2QfWeNPLRVM7gNs3hrwaWn/JPT2jcdL4i8FDFgmtZwp?= =?us-ascii?Q?/oOC4oPw8gVhv9/jfciQsX1nL3Au8rRnFwaBokB5nkHzmPUqbwWWZGvWfEUW?= =?us-ascii?Q?JmX7Frs3DjygrNzvUd7AVmieh4j62P/PNZhcW/SHltZt0oVvu7QnFl+oe85n?= =?us-ascii?Q?yzRXdDW17X7VOVPcGEbJGZfJpRuFACALgxOywlGyHFoFUnPYv2ibTX21It5T?= =?us-ascii?Q?GQC6ytyBjMPWrf1WdPS4f9Nf2dHpbDgufHjynvxWBoMiUOQirHNsTMnuWACS?= =?us-ascii?Q?QTEB2FlTJBPyOevPlT0DRwAcJ26YaitCtlcqsL7Jw1W4+f6Bg/Pco/UGAJxh?= =?us-ascii?Q?OmUr+dY33/+Tv85pgp3FYRoEaNolmgJuETUuO+2Dprv4Qn0QlzBRRp/+XzxN?= =?us-ascii?Q?yLwQkStjAvIoGHZ74CphvOWgYPNjCm4wqvt4jG19xSnAaiTyWeMW/U0WM/MA?= =?us-ascii?Q?DqVKbgH792l54uznchpbRK8tQNXEH0lZMdBRBPRmzi8cxtBYt/v6wzrSpfK/?= =?us-ascii?Q?U+dFsVdHNzNcqSlnzGY2dm8uWbzI7uBm9sblo5sFJg5I3VRmv5Ba46MG9hKo?= =?us-ascii?Q?c24rm1yLmtN/fHazaVqNKZoAvRtw33E97XngeLjo5YYKsp3p7IUqBW5SQxGz?= =?us-ascii?Q?0xLi9Y2btVwBpaxad5WbU/ZJHGyoFtfkXx5xh3BRUGErNWOEwcYh4vOjVPnd?= =?us-ascii?Q?G+N4e2q6arTmGLZGOsIIHwq+jFic9NqggFmhlk42ns26n8UrP/NrFqzlLYb7?= =?us-ascii?Q?ExjjLYIDWY2NZWejocFk8wgH1D1dKDrY4i/BYekEpMFPilmbyHdbDLzePPz8?= =?us-ascii?Q?esFh6LVs8OFSqMVVof3J/f4MeZYsQcf2pLPQx+OiBKJnrdQgi7S3QjuHS7Li?= =?us-ascii?Q?NhPc6Hi4DKPkgMdslAeej2M6+0ZSOlXXy/Vvb4YcnaP31ibKbeHMQHfCf00v?= =?us-ascii?Q?b9l3dZSBVAJx0a/prfGJjghHluKJ6QvK6IBRVnev1qxQ34gi0MU1NpHKg6nm?= =?us-ascii?Q?rnj2PBEMG+7MKhcg9wx7DepG6hgfoTSPPYEPx1ND9igCFl8Hjv0pnAoXE0OC?= =?us-ascii?Q?ZjCgZbswBN3eHjWKty6LFfzrO59Vq/rv97dZ9l/86Y2gLHhLyAus82HNYeHZ?= =?us-ascii?Q?CI7PQgqI5h3o0ygsUZIbl6XG7p1O5zKGu6Huvwqf7bPWc35JpKg10kd5bSyu?= =?us-ascii?Q?WbauuwhZ8EU0mahFNyR12L6a6BOBZuKbL1TK?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(7416014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2025 11:37:49.3096 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 733d0d20-b1ae-4004-60ec-08ddaf25b822 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F3E.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5679 Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea Add initial infrastructure to create and destroy the PCIe Congestion Event object if the object is supported. The verb for the object creation function is "set" instead of "create" because the function will accommodate the modify operation as well in a subsequent patch. The next patches will hook it up to the event handler and will add actual functionality. Signed-off-by: Dragos Tatulea Reviewed-by: Tariq Toukan Signed-off-by: Mark Bloch --- .../net/ethernet/mellanox/mlx5/core/Makefile | 2 +- drivers/net/ethernet/mellanox/mlx5/core/en.h | 2 + .../mellanox/mlx5/core/en/pcie_cong_event.c | 153 ++++++++++++++++++ .../mellanox/mlx5/core/en/pcie_cong_event.h | 11 ++ .../net/ethernet/mellanox/mlx5/core/en_main.c | 3 + 5 files changed, 170 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_ev= ent.c create mode 100644 drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_ev= ent.h diff --git a/drivers/net/ethernet/mellanox/mlx5/core/Makefile b/drivers/net= /ethernet/mellanox/mlx5/core/Makefile index d292e6a9e22c..650df18a9216 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/Makefile +++ b/drivers/net/ethernet/mellanox/mlx5/core/Makefile @@ -29,7 +29,7 @@ mlx5_core-$(CONFIG_MLX5_CORE_EN) +=3D en/rqt.o en/tir.o e= n/rss.o en/rx_res.o \ en/reporter_tx.o en/reporter_rx.o en/params.o en/xsk/pool.o \ en/xsk/setup.o en/xsk/rx.o en/xsk/tx.o en/devlink.o en/ptp.o \ en/qos.o en/htb.o en/trap.o en/fs_tt_redirect.o en/selq.o \ - lib/crypto.o lib/sd.o + lib/crypto.o lib/sd.o en/pcie_cong_event.o =20 # # Netdev extra diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index 65a73913b9a2..784050bbf7f7 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -921,6 +921,8 @@ struct mlx5e_priv { struct notifier_block events_nb; struct notifier_block blocking_events_nb; =20 + struct mlx5e_pcie_cong_event *cong_event; + struct udp_tunnel_nic_info nic_info; #ifdef CONFIG_MLX5_CORE_EN_DCB struct mlx5e_dcbx dcbx; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c b= /drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c new file mode 100644 index 000000000000..95a6db9d30b3 --- /dev/null +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB +// Copyright (c) 2025, NVIDIA CORPORATION & AFFILIATES. + +#include "en.h" +#include "pcie_cong_event.h" + +struct mlx5e_pcie_cong_thresh { + u16 inbound_high; + u16 inbound_low; + u16 outbound_high; + u16 outbound_low; +}; + +struct mlx5e_pcie_cong_event { + u64 obj_id; + + struct mlx5e_priv *priv; +}; + +/* In units of 0.01 % */ +static const struct mlx5e_pcie_cong_thresh default_thresh_config =3D { + .inbound_high =3D 9000, + .inbound_low =3D 7500, + .outbound_high =3D 9000, + .outbound_low =3D 7500, +}; + +static int +mlx5_cmd_pcie_cong_event_set(struct mlx5_core_dev *dev, + const struct mlx5e_pcie_cong_thresh *config, + u64 *obj_id) +{ + u32 in[MLX5_ST_SZ_DW(pcie_cong_event_cmd_in)] =3D {}; + u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; + void *cong_obj; + void *hdr; + int err; + + hdr =3D MLX5_ADDR_OF(pcie_cong_event_cmd_in, in, hdr); + cong_obj =3D MLX5_ADDR_OF(pcie_cong_event_cmd_in, in, cong_obj); + + MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, + MLX5_CMD_OP_CREATE_GENERAL_OBJECT); + + MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, + MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT); + + MLX5_SET(pcie_cong_event_obj, cong_obj, inbound_event_en, 1); + MLX5_SET(pcie_cong_event_obj, cong_obj, outbound_event_en, 1); + + MLX5_SET(pcie_cong_event_obj, cong_obj, + inbound_cong_high_threshold, config->inbound_high); + MLX5_SET(pcie_cong_event_obj, cong_obj, + inbound_cong_low_threshold, config->inbound_low); + + MLX5_SET(pcie_cong_event_obj, cong_obj, + outbound_cong_high_threshold, config->outbound_high); + MLX5_SET(pcie_cong_event_obj, cong_obj, + outbound_cong_low_threshold, config->outbound_low); + + err =3D mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); + if (err) + return err; + + *obj_id =3D MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); + + mlx5_core_dbg(dev, "PCIe congestion event (obj_id=3D%llu) created. Config= : in: [%u, %u], out: [%u, %u]\n", + *obj_id, + config->inbound_high, config->inbound_low, + config->outbound_high, config->outbound_low); + + return 0; +} + +static int mlx5_cmd_pcie_cong_event_destroy(struct mlx5_core_dev *dev, + u64 obj_id) +{ + u32 in[MLX5_ST_SZ_DW(pcie_cong_event_cmd_in)] =3D {}; + u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; + void *hdr; + + hdr =3D MLX5_ADDR_OF(pcie_cong_event_cmd_in, in, hdr); + MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, + MLX5_CMD_OP_DESTROY_GENERAL_OBJECT); + MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, + MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT); + MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, obj_id); + + return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); +} + +bool mlx5e_pcie_cong_event_supported(struct mlx5_core_dev *dev) +{ + u64 features =3D MLX5_CAP_GEN_2_64(dev, general_obj_types_127_64); + + if (!(features & MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT)) + return false; + + if (dev->sd) + return false; + + return true; +} + +int mlx5e_pcie_cong_event_init(struct mlx5e_priv *priv) +{ + struct mlx5e_pcie_cong_event *cong_event; + struct mlx5_core_dev *mdev =3D priv->mdev; + int err; + + if (!mlx5e_pcie_cong_event_supported(mdev)) + return 0; + + cong_event =3D kvzalloc_node(sizeof(*cong_event), GFP_KERNEL, + mdev->priv.numa_node); + if (!cong_event) + return -ENOMEM; + + cong_event->priv =3D priv; + + err =3D mlx5_cmd_pcie_cong_event_set(mdev, &default_thresh_config, + &cong_event->obj_id); + if (err) { + mlx5_core_warn(mdev, "Error creating a PCIe congestion event object\n"); + goto err_free; + } + + priv->cong_event =3D cong_event; + + return 0; + +err_free: + kvfree(cong_event); + + return err; +} + +void mlx5e_pcie_cong_event_cleanup(struct mlx5e_priv *priv) +{ + struct mlx5e_pcie_cong_event *cong_event =3D priv->cong_event; + struct mlx5_core_dev *mdev =3D priv->mdev; + + if (!cong_event) + return; + + priv->cong_event =3D NULL; + + if (mlx5_cmd_pcie_cong_event_destroy(mdev, cong_event->obj_id)) + mlx5_core_warn(mdev, "Error destroying PCIe congestion event (obj_id=3D%= llu)\n", + cong_event->obj_id); + + kvfree(cong_event); +} diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.h b= /drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.h new file mode 100644 index 000000000000..bf1e3632d596 --- /dev/null +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ +/* Copyright (c) 2025, NVIDIA CORPORATION & AFFILIATES. */ + +#ifndef __MLX5_PCIE_CONG_EVENT_H__ +#define __MLX5_PCIE_CONG_EVENT_H__ + +bool mlx5e_pcie_cong_event_supported(struct mlx5_core_dev *dev); +int mlx5e_pcie_cong_event_init(struct mlx5e_priv *priv); +void mlx5e_pcie_cong_event_cleanup(struct mlx5e_priv *priv); + +#endif /* __MLX5_PCIE_CONG_EVENT_H__ */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index dca5ca51a470..c6c2139483e0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -76,6 +76,7 @@ #include "en/trap.h" #include "lib/devcom.h" #include "lib/sd.h" +#include "en/pcie_cong_event.h" =20 static bool mlx5e_hw_gro_supported(struct mlx5_core_dev *mdev) { @@ -5988,6 +5989,7 @@ static void mlx5e_nic_enable(struct mlx5e_priv *priv) if (mlx5e_monitor_counter_supported(priv)) mlx5e_monitor_counter_init(priv); =20 + mlx5e_pcie_cong_event_init(priv); mlx5e_hv_vhca_stats_create(priv); if (netdev->reg_state !=3D NETREG_REGISTERED) return; @@ -6027,6 +6029,7 @@ static void mlx5e_nic_disable(struct mlx5e_priv *priv) =20 mlx5e_nic_set_rx_mode(priv); =20 + mlx5e_pcie_cong_event_cleanup(priv); mlx5e_hv_vhca_stats_destroy(priv); if (mlx5e_monitor_counter_supported(priv)) mlx5e_monitor_counter_cleanup(priv); --=20 2.34.1 From nobody Thu Oct 9 06:52:48 2025 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2079.outbound.protection.outlook.com [40.107.93.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1F99227B95; Thu, 19 Jun 2025 11:37:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.93.79 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750333077; cv=fail; b=CdBBYMkFQgHG1uNT1aZ7sDPK1WlZIy2YXCcQmVw25g6RfOR/iG77vZbrTbVlAM84cUW0IaRokSzAzIUmHUXY3G6AdETfDCxCYmMR/dUMUFxGClDlSUKmn0QFaCDSA/Wk89P4n4k6seuYAh1+svcR5AClod2+MBeDRxfmgWNMITg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750333077; c=relaxed/simple; bh=JHPaq1aK4uBvzoAlhaqX85M3v1mTRP1RzP91z0anDrU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lqAeyFH7LxabHIKkhLvhQpj9hU2Ph/i+AmuRG4PLrjs0XK91JJe2JslMjXEPXp47t1sagLnChwXQ28oDg2k6VBoxQqF6GpNucvinHX0Vy9Ir81ZzJBMErdKjnrHlaSAfVMRPPYODtLuFv6/ENT8yZzw6x5PkldnsQIKaHZ4ohn8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=dNxvb8JI; arc=fail smtp.client-ip=40.107.93.79 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="dNxvb8JI" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=uSbprHTQWZY7M3jKtunoCJUObu6VhWKByYlaf9d4LqJfxg5g9bVXKukwCXtCfiu24YKC2dN76ID7mso0rwh7y+eyfyNmGUh3QcVELSqhMGBxiQUWPG3zQc4Kts7kDykOCWHNBcICCLwL+lukNAQE4H2sQGOMzUduFW0rcDXp3lXrlnnowyA+Yw2BX7X0SLuPsMeme0a6pBcPBjmhBoDN6IitSl35JiZe9ifVEy77tgLZt9kO+XLL/Uw11o072QQnbm+pEL5sflwLHmAgqsvojVEAdNaw05GWxC5JFit5t8p2SXe95D1mqTALrArosuHkgWtshP5K9gjgBjdQABHZlQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=heimAQqmzu7SlNagM27dhcYmHciDpHkAOaWUD+hd97M=; b=eNYW9GlrulKviZH2WdpWvgdu5RfeJgh7WRNh7z+j7SdbZaKvFt6AQKZ1pEd55qOyBC+VmZFbueO4xafCMXof/Q35EvmksAoN2rq4qYjypR30A4eCx9dhmRJ+ep2NJ5no0zOHWxLGiJM2VZqfeu9W/cltzCWWQfx36CZdYBZnW3JSx0PY0u74tVt7VVY7bvyqkk0BACTuPVr0zb5odqgoNlYANpb3x+3nb/QU69ad9Vr/aDczjRrfheqIL2LqVjISqjI20De2v9WLGu/ivEXKOsRaYUiCIPX/+U0uNONXXAp5NXLKHeZ8sGCzfWMMam470TW6WBHPogmevFRWG95JsA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=davemloft.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=heimAQqmzu7SlNagM27dhcYmHciDpHkAOaWUD+hd97M=; b=dNxvb8JI7g39oXyiyZVjyHxG3M4WO+mRZSXj4tWI3JNi2PmQCU8vaLiseFXlFgs43sEuxo0GHyPzApTRgzv0FfECu+s7NcPn/0JBELh+B78zsXU6SIMkS2hLX5RoizQYR3DjWreLyzUNPeI3TQdK0Uw5iGDC187SXzX91QGFlE6CCXXRVPxFbHq47PhvJul2eCDH+SnBrLkrzJ7psSRIzDEFWdemapY5xsY/PEygY602VJS0Pjv6ufRdgU2T4FRJxmHdKB+hwqcDM1FGxerKmpYz897Tk5iRQBkDxSm57r4+4M73siMAj8t5H8kwvQp4jGnPQ6NIzRFO/ohQOhrSPQ== Received: from CY5P221CA0076.NAMP221.PROD.OUTLOOK.COM (2603:10b6:930:9::26) by LV3PR12MB9437.namprd12.prod.outlook.com (2603:10b6:408:21d::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8835.29; Thu, 19 Jun 2025 11:37:52 +0000 Received: from CY4PEPF0000EDD7.namprd03.prod.outlook.com (2603:10b6:930:9:cafe::25) by CY5P221CA0076.outlook.office365.com (2603:10b6:930:9::26) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8835.34 via Frontend Transport; Thu, 19 Jun 2025 11:37:52 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by CY4PEPF0000EDD7.mail.protection.outlook.com (10.167.241.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8857.21 via Frontend Transport; Thu, 19 Jun 2025 11:37:51 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 19 Jun 2025 04:37:45 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Thu, 19 Jun 2025 04:37:45 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Thu, 19 Jun 2025 04:37:41 -0700 From: Mark Bloch To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Leon Romanovsky , Jonathan Corbet , , , , , Dragos Tatulea , Mark Bloch Subject: [PATCH net-next 4/5] net/mlx5e: Add device PCIe congestion ethtool stats Date: Thu, 19 Jun 2025 14:37:20 +0300 Message-ID: <20250619113721.60201-5-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250619113721.60201-1-mbloch@nvidia.com> References: <20250619113721.60201-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD7:EE_|LV3PR12MB9437:EE_ X-MS-Office365-Filtering-Correlation-Id: b7105d3d-d9d1-44f4-4ba8-08ddaf25b96c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?SSkCN+QxztGLPgzzezXzRMOMGUdSleSuoWgFNFPS44OkqCBzOIjXu60S+J9i?= =?us-ascii?Q?uz/p9xZp2DTD7aMTcOVzem7w2cZXF9GSLUpOFPQ5Z+cvl3uV0wO8OMCnOMHM?= =?us-ascii?Q?Jhv3+O7nBwz/PTJIUpjtZR8/X1RWRYeVoxBc78CdwQ7xC0yPTUJ7kmrboxqK?= =?us-ascii?Q?2d9M/IhV0fW5cYb4s3p57p/gj25fHx4AKPDJwhw0TEBpN6j5y5IPmbAk7237?= =?us-ascii?Q?X7moWE6iLjrPH19j4JcLpqGcIjJ7GUPuoX6C3e6NGzyTsDPWQa4ZSOqjLL62?= =?us-ascii?Q?PxHxSAs9kbAknf/aQCLLrxjAQ16oHDJgllWO/b30r4Vlfh2O31LvjpFIBtwo?= =?us-ascii?Q?Fq91tw1sn+XplcHg3zGWNHDNMKSzq9duKLfE3uaEyzz+UPmT3NNElw2RjJB3?= =?us-ascii?Q?HU6Bf/o3ZMIi70GByQiYRrAQ+yRCgMOjrslkzq1br53pglZ33z3/nxMj9QsS?= =?us-ascii?Q?hSKz4FUyXX7AO7BxAUUe1zzuYrvKuY8e+KkPU4tx8HIlgZ2VYae3fk7x4D+f?= =?us-ascii?Q?GNYPs8hrQbqtCm2Kw3JEUmbi4Ipe3g1c/Hv1umFLUYu68e9q6EY/2ww3uNKU?= =?us-ascii?Q?Z78Ts/fImyAThwi9lA5fOObNeF1e6xRl7c23XCFlzbefST0mxaH0+VXJ6WD3?= =?us-ascii?Q?riF7K/qIoK0NIj/ND1HvoNpZ7q6KxFuyVjwf53Fn/zeFLa+u6OtwJ72rbdvZ?= =?us-ascii?Q?X2c3SxLaj7j2JlVj+75hN6KzQGnt4JmIvEkGLqomhL6NGEFGo0neCOLf/0+x?= =?us-ascii?Q?55wpOxVz7xNc4Hv/jUILMBq51cdDT0vFlXOhdXBiL/WqqQVFEV2/hoHlqWsh?= =?us-ascii?Q?Ki5iEdYKiW32FjhjWghPqB3cOVyxH9uMpr3y5S7DP+1QfQzlzZAc3Z+YoTuK?= =?us-ascii?Q?hgqf+M4vEARgAOVYL96It15OumBQjtUXNHMCSILdan+vayL2wqSFNQgXxqB9?= =?us-ascii?Q?UEMMMv72rG03FV+sR5y0yQdMzuT+VnQcCFGfLkPc3Tz5RMNF5mOr1qp+th4E?= =?us-ascii?Q?ZXRw0BYsJyzCkJ9tlhoQtBHFxb/htTqY7wVqM1l6PEVAX9CT7kGkYubRdj7V?= =?us-ascii?Q?qHLBZ4DFLLbn9olJrSjzdhE0lv2thst37YOwZlsNsj6TY1cI2f7U5W+LEI21?= =?us-ascii?Q?+Vh3bce2Zozy3u7QI2+hvlvfyw2JViieuwJAfxLN7ocfK6Uk6EjobHh0lG+G?= =?us-ascii?Q?RotmPJWw2GfONEKs7DLyMh5i17aiYJonVcJOMmj4X4pzNGNyWDCVaVYTgTXr?= =?us-ascii?Q?XwuTCIuc5VePVcbnbk8NtctpDtwGY5b4RuCGha+hXl7Q/Sn0pNkzt3IyQQde?= =?us-ascii?Q?EfRIl/ZvZDZ3q1/fFs/T2tNlaQXlSS6A9o8dHsZ6gHSXoOgHd3aVeBwNzJst?= =?us-ascii?Q?26CUpqb7qFsOgmjz2mB1whmGf0O7KB/dj6ZAD7zKw8XL7Ks1wWO+MhsI5Bad?= =?us-ascii?Q?zb4fNQlUpRXA/U7kOHjp/P2euQKuNLK7cu5sYtVckNkVS8aY24n/akmA2fVz?= =?us-ascii?Q?vdVZkUKgue1KHVzJJ8xMsdR3rWZSs+dhb3n+?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2025 11:37:51.5002 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b7105d3d-d9d1-44f4-4ba8-08ddaf25b96c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9437 Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea Implement the PCIe Congestion Event notifier which triggers a work item to query the PCIe Congestion Event object. The result of the congestion state is reflected in the new ethtool stats: * pci_bw_inbound_high: the device has crossed the high threshold for inbound PCIe traffic. * pci_bw_inbound_low: the device has crossed the low threshold for inbound PCIe traffic * pci_bw_outbound_high: the device has crossed the high threshold for outbound PCIe traffic. * pci_bw_outbound_low: the device has crossed the low threshold for outbound PCIe traffic The high and low thresholds are currently configured at 90% and 75%. These are hysteresis thresholds which help to check if the PCI bus on the device side is in a congested state. If low + 1 =3D high then the device is in a congested state. If low =3D=3D = high then the device is not in a congested state. The counters are also documented. A follow-up patch will make the thresholds configurable. Signed-off-by: Dragos Tatulea Reviewed-by: Tariq Toukan Signed-off-by: Mark Bloch --- .../ethernet/mellanox/mlx5/counters.rst | 32 ++++ .../mellanox/mlx5/core/en/pcie_cong_event.c | 175 ++++++++++++++++++ .../ethernet/mellanox/mlx5/core/en_stats.c | 1 + .../ethernet/mellanox/mlx5/core/en_stats.h | 1 + drivers/net/ethernet/mellanox/mlx5/core/eq.c | 4 + 5 files changed, 213 insertions(+) diff --git a/Documentation/networking/device_drivers/ethernet/mellanox/mlx5= /counters.rst b/Documentation/networking/device_drivers/ethernet/mellanox/m= lx5/counters.rst index 43d72c8b713b..754c81436408 100644 --- a/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/counte= rs.rst +++ b/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/counte= rs.rst @@ -1341,3 +1341,35 @@ Device Counters - The number of times the device owned queue had not enough buffers allocated. - Error + + * - `pci_bw_inbound_high` + - The number of times the device crossed the high inbound pcie bandwi= dth + threshold. To be compared to pci_bw_inbound_low to check if the dev= ice + is in a congested state. + If pci_bw_inbound_high =3D=3D pci_bw_inbound_low then the device is= not congested. + If pci_bw_inbound_high > pci_bw_inbound_low then the device is cong= ested. + - Tnformative + + * - `pci_bw_inbound_low` + - The number of times the device crossed the low inbound PCIe bandwid= th + threshold. To be compared to pci_bw_inbound_high to check if the de= vice + is in a congested state. + If pci_bw_inbound_high =3D=3D pci_bw_inbound_low then the device is= not congested. + If pci_bw_inbound_high > pci_bw_inbound_low then the device is cong= ested. + - Informative + + * - `pci_bw_outbound_high` + - The number of times the device crossed the high outbound pcie bandw= idth + threshold. To be compared to pci_bw_outbound_low to check if the de= vice + is in a congested state. + If pci_bw_outbound_high =3D=3D pci_bw_outbound_low then the device = is not congested. + If pci_bw_outbound_high > pci_bw_outbound_low then the device is co= ngested. + - Informative + + * - `pci_bw_outbound_low` + - The number of times the device crossed the low outbound PCIe bandwi= dth + threshold. To be compared to pci_bw_outbound_high to check if the d= evice + is in a congested state. + If pci_bw_outbound_high =3D=3D pci_bw_outbound_low then the device = is not congested. + If pci_bw_outbound_high > pci_bw_outbound_low then the device is co= ngested. + - Informative diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c b= /drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c index 95a6db9d30b3..a24e5465ceeb 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c @@ -4,6 +4,13 @@ #include "en.h" #include "pcie_cong_event.h" =20 +#define MLX5E_CONG_HIGH_STATE 0x7 + +enum { + MLX5E_INBOUND_CONG =3D BIT(0), + MLX5E_OUTBOUND_CONG =3D BIT(1), +}; + struct mlx5e_pcie_cong_thresh { u16 inbound_high; u16 inbound_low; @@ -11,10 +18,27 @@ struct mlx5e_pcie_cong_thresh { u16 outbound_low; }; =20 +struct mlx5e_pcie_cong_stats { + u32 pci_bw_inbound_high; + u32 pci_bw_inbound_low; + u32 pci_bw_outbound_high; + u32 pci_bw_outbound_low; +}; + struct mlx5e_pcie_cong_event { u64 obj_id; =20 struct mlx5e_priv *priv; + + /* For event notifier and workqueue. */ + struct work_struct work; + struct mlx5_nb nb; + + /* Stores last read state. */ + u8 state; + + /* For ethtool stats group. */ + struct mlx5e_pcie_cong_stats stats; }; =20 /* In units of 0.01 % */ @@ -25,6 +49,51 @@ static const struct mlx5e_pcie_cong_thresh default_thres= h_config =3D { .outbound_low =3D 7500, }; =20 +static const struct counter_desc mlx5e_pcie_cong_stats_desc[] =3D { + { MLX5E_DECLARE_STAT(struct mlx5e_pcie_cong_stats, + pci_bw_inbound_high) }, + { MLX5E_DECLARE_STAT(struct mlx5e_pcie_cong_stats, + pci_bw_inbound_low) }, + { MLX5E_DECLARE_STAT(struct mlx5e_pcie_cong_stats, + pci_bw_outbound_high) }, + { MLX5E_DECLARE_STAT(struct mlx5e_pcie_cong_stats, + pci_bw_outbound_low) }, +}; + +#define NUM_PCIE_CONG_COUNTERS ARRAY_SIZE(mlx5e_pcie_cong_stats_desc) + +static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(pcie_cong) +{ + return priv->cong_event ? NUM_PCIE_CONG_COUNTERS : 0; +} + +static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(pcie_cong) {} + +static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(pcie_cong) +{ + if (!priv->cong_event) + return; + + for (int i =3D 0; i < NUM_PCIE_CONG_COUNTERS; i++) + ethtool_puts(data, mlx5e_pcie_cong_stats_desc[i].format); +} + +static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(pcie_cong) +{ + if (!priv->cong_event) + return; + + for (int i =3D 0; i < NUM_PCIE_CONG_COUNTERS; i++) { + u32 ctr =3D MLX5E_READ_CTR32_CPU(&priv->cong_event->stats, + mlx5e_pcie_cong_stats_desc, + i); + + mlx5e_ethtool_put_stat(data, ctr); + } +} + +MLX5E_DEFINE_STATS_GRP(pcie_cong, 0); + static int mlx5_cmd_pcie_cong_event_set(struct mlx5_core_dev *dev, const struct mlx5e_pcie_cong_thresh *config, @@ -89,6 +158,97 @@ static int mlx5_cmd_pcie_cong_event_destroy(struct mlx5= _core_dev *dev, return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); } =20 +static int mlx5_cmd_pcie_cong_event_query(struct mlx5_core_dev *dev, + u64 obj_id, + u32 *state) +{ + u32 in[MLX5_ST_SZ_DW(pcie_cong_event_cmd_in)] =3D {}; + u32 out[MLX5_ST_SZ_DW(pcie_cong_event_cmd_out)]; + void *obj; + void *hdr; + u8 cong; + int err; + + hdr =3D MLX5_ADDR_OF(pcie_cong_event_cmd_in, in, hdr); + + MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, + MLX5_CMD_OP_QUERY_GENERAL_OBJECT); + MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, + MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT); + MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, obj_id); + + err =3D mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); + if (err) + return err; + + obj =3D MLX5_ADDR_OF(pcie_cong_event_cmd_out, out, cong_obj); + + if (state) { + cong =3D MLX5_GET(pcie_cong_event_obj, obj, inbound_cong_state); + if (cong =3D=3D MLX5E_CONG_HIGH_STATE) + *state |=3D MLX5E_INBOUND_CONG; + + cong =3D MLX5_GET(pcie_cong_event_obj, obj, outbound_cong_state); + if (cong =3D=3D MLX5E_CONG_HIGH_STATE) + *state |=3D MLX5E_OUTBOUND_CONG; + } + + return 0; +} + +static void mlx5e_pcie_cong_event_work(struct work_struct *work) +{ + struct mlx5e_pcie_cong_event *cong_event; + struct mlx5_core_dev *dev; + struct mlx5e_priv *priv; + u32 new_cong_state =3D 0; + u32 changes; + int err; + + cong_event =3D container_of(work, struct mlx5e_pcie_cong_event, work); + priv =3D cong_event->priv; + dev =3D priv->mdev; + + err =3D mlx5_cmd_pcie_cong_event_query(dev, cong_event->obj_id, + &new_cong_state); + if (err) { + mlx5_core_warn(dev, "Error %d when querying PCIe cong event object (obj_= id=3D%llu).\n", + err, cong_event->obj_id); + return; + } + + changes =3D cong_event->state ^ new_cong_state; + if (!changes) + return; + + cong_event->state =3D new_cong_state; + + if (changes & MLX5E_INBOUND_CONG) { + if (new_cong_state & MLX5E_INBOUND_CONG) + cong_event->stats.pci_bw_inbound_high++; + else + cong_event->stats.pci_bw_inbound_low++; + } + + if (changes & MLX5E_OUTBOUND_CONG) { + if (new_cong_state & MLX5E_OUTBOUND_CONG) + cong_event->stats.pci_bw_outbound_high++; + else + cong_event->stats.pci_bw_outbound_low++; + } +} + +static int mlx5e_pcie_cong_event_handler(struct notifier_block *nb, + unsigned long event, void *eqe) +{ + struct mlx5e_pcie_cong_event *cong_event; + + cong_event =3D mlx5_nb_cof(nb, struct mlx5e_pcie_cong_event, nb); + queue_work(cong_event->priv->wq, &cong_event->work); + + return NOTIFY_OK; +} + bool mlx5e_pcie_cong_event_supported(struct mlx5_core_dev *dev) { u64 features =3D MLX5_CAP_GEN_2_64(dev, general_obj_types_127_64); @@ -116,6 +276,10 @@ int mlx5e_pcie_cong_event_init(struct mlx5e_priv *priv) if (!cong_event) return -ENOMEM; =20 + INIT_WORK(&cong_event->work, mlx5e_pcie_cong_event_work); + MLX5_NB_INIT(&cong_event->nb, mlx5e_pcie_cong_event_handler, + OBJECT_CHANGE); + cong_event->priv =3D priv; =20 err =3D mlx5_cmd_pcie_cong_event_set(mdev, &default_thresh_config, @@ -125,10 +289,18 @@ int mlx5e_pcie_cong_event_init(struct mlx5e_priv *pri= v) goto err_free; } =20 + err =3D mlx5_eq_notifier_register(mdev, &cong_event->nb); + if (err) { + mlx5_core_warn(mdev, "Error registering notifier for the PCIe congestion= event\n"); + goto err_obj_destroy; + } + priv->cong_event =3D cong_event; =20 return 0; =20 +err_obj_destroy: + mlx5_cmd_pcie_cong_event_destroy(mdev, cong_event->obj_id); err_free: kvfree(cong_event); =20 @@ -145,6 +317,9 @@ void mlx5e_pcie_cong_event_cleanup(struct mlx5e_priv *p= riv) =20 priv->cong_event =3D NULL; =20 + mlx5_eq_notifier_unregister(mdev, &cong_event->nb); + cancel_work_sync(&cong_event->work); + if (mlx5_cmd_pcie_cong_event_destroy(mdev, cong_event->obj_id)) mlx5_core_warn(mdev, "Error destroying PCIe congestion event (obj_id=3D%= llu)\n", cong_event->obj_id); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c b/drivers/n= et/ethernet/mellanox/mlx5/core/en_stats.c index 19664fa7f217..87536f158d07 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c @@ -2612,6 +2612,7 @@ mlx5e_stats_grp_t mlx5e_nic_stats_grps[] =3D { #ifdef CONFIG_MLX5_MACSEC &MLX5E_STATS_GRP(macsec_hw), #endif + &MLX5E_STATS_GRP(pcie_cong), }; =20 unsigned int mlx5e_nic_stats_grps_num(struct mlx5e_priv *priv) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h b/drivers/n= et/ethernet/mellanox/mlx5/core/en_stats.h index def5dea1463d..72dbcc1928ef 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h @@ -535,5 +535,6 @@ extern MLX5E_DECLARE_STATS_GRP(ipsec_hw); extern MLX5E_DECLARE_STATS_GRP(ipsec_sw); extern MLX5E_DECLARE_STATS_GRP(ptp); extern MLX5E_DECLARE_STATS_GRP(macsec_hw); +extern MLX5E_DECLARE_STATS_GRP(pcie_cong); =20 #endif /* __MLX5_EN_STATS_H__ */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eq.c b/drivers/net/eth= ernet/mellanox/mlx5/core/eq.c index dfb079e59d85..db54f6d26591 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eq.c @@ -21,6 +21,7 @@ #include "pci_irq.h" #include "devlink.h" #include "en_accel/ipsec.h" +#include "en/pcie_cong_event.h" =20 enum { MLX5_EQE_OWNER_INIT_VAL =3D 0x1, @@ -585,6 +586,9 @@ static void gather_async_events_mask(struct mlx5_core_d= ev *dev, u64 mask[4]) async_event_mask |=3D (1ull << MLX5_EVENT_TYPE_OBJECT_CHANGE); =20 + if (mlx5e_pcie_cong_event_supported(dev)) + async_event_mask |=3D (1ull << MLX5_EVENT_TYPE_OBJECT_CHANGE); + mask[0] =3D async_event_mask; =20 if (MLX5_CAP_GEN(dev, event_cap)) --=20 2.34.1 From nobody Thu Oct 9 06:52:48 2025 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2059.outbound.protection.outlook.com [40.107.243.59]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AAFDF22B59F; Thu, 19 Jun 2025 11:38:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.243.59 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750333089; cv=fail; b=b3JxB1OTFFC2x2sElopa17+eStlWhScVK5kusPVg0bT7gsdpCRRpBlEC1FvivDpRa5JFXABlHyf6hflvwwU21GGYjUp4h0dxjbVyV2YGl2lh4G7F2Y6NBmqp0oyciw7Ads/bpI++x6bz6KlR2fdsg/0erkRmSjBSTxIK7sFfiKI= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750333089; c=relaxed/simple; bh=PSxsQ4p/R+RUJ2+lcKybCiHQyzvbO2L8g4wXKG2NUWM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=oyln4SLjPYPDhpX0Rkkv5Q4gmMDevfBq3vRaQ2lk2uu6SJUz74rUdwBPceprOKnS6ktNKWmlQbof9DB3SJvmDQB0Qk3A38HcLi3YHjUl/x/GnYdT5gb/ePdPgkm49gVlEnzeJhYrnv7kLyboXvVw9su/9YNz4XJPVVZhFX8Rzto= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=qabH5bqx; arc=fail smtp.client-ip=40.107.243.59 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="qabH5bqx" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=CJt87HIKcncPX+LT/XWMr45MWb552vP8niFwldKUYgG/pGZrjJrBkmR3SxILIWkGOtPH8C0MbBNYRa25x6OxnlavqpZ4REzvhxdvv/4D98dAQVBytG6GaoupmUGr9DJwD9e/PYEDppZv4/ttkXUcGXAr8CUd8tuK0nQKLaFPPAPEH6rfbOjCfav3jqFMeahrBD0GqsiHepVsfCWHKV4DwbTTdh+T1uGfWLPPcR99NrEiXloza4PFP9JGhdOhuoUjvpFEXm/b4KxAzNxuGaIantwWlHgaYC6xnvtnyp0gBynqChC/Otfi7cfKidlG9BHVhTIbryymt0Soi+h2Bt9XMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=S933YdDqX1lB2xF1I1TdItjBbjuL08cJ96Aueu6pHm8=; b=yL/og3T+ZGNePGHunrPWqKvOOrip+Iu+bPtJGH5g4fOG7DURLIczHJUEBkTat45Z52UVB09Fl4fJ2cDMRsJbXY/NiggpSGL4teO17qH4HCqk6vQrYB5RJxbaGwWLpSLYVfjQQ6+xsCMlh2AI7uVmDz+PtqNBcooyVvFLJURKZ99Mdk5LZKxWzREVL6R06pq1si3bBnfGypsPZ+ZNeBUDjYVggWoFk9XyMHt0dUZC7E9LQ4K/BhNPzJgwxp8Q6e+/gHuDlcqTLzjvBHWg3eQBQLE+QPTL8XxTVN5NeYjRokez58J+PBcPlBxum+H1SFCtVYLOl6aadBicOiHJ5ZTekA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=davemloft.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=S933YdDqX1lB2xF1I1TdItjBbjuL08cJ96Aueu6pHm8=; b=qabH5bqxWpFP4+xL18AqVEBECXBjKCqBZJQ34YnwI9jqTTlye4qy3tK6vjE970/A7K6PDjZkMO+U4w3vOwbIcyop8WAEgEdIzlcQcleS5Ats0mVYfV6Wd8UpJnM36SvbJ5FyUwVbYfh/s889vMWvt6+k1sn1fUciD3rzVIc4AtfmAXDCN+I5uuECood50Qa41vbqXM22Y8qSJeuYlMVxNvh4LWMj1UXUKJv5whw6a0YcF4Wo4ziDN1yPNXFmn9ECQtn/3yiYX6QdWyH9Jkn8qC7NFvZIux4R/uon/Qro5Nj1OQAy9pw3Tx9vm+3Uim/fEnkdsp885QKWxFQ6GvgEmg== Received: from SJ0PR05CA0130.namprd05.prod.outlook.com (2603:10b6:a03:33d::15) by DS0PR12MB9323.namprd12.prod.outlook.com (2603:10b6:8:1b3::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8835.29; Thu, 19 Jun 2025 11:38:03 +0000 Received: from SN1PEPF00036F3C.namprd05.prod.outlook.com (2603:10b6:a03:33d:cafe::a4) by SJ0PR05CA0130.outlook.office365.com (2603:10b6:a03:33d::15) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8880.8 via Frontend Transport; Thu, 19 Jun 2025 11:38:02 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SN1PEPF00036F3C.mail.protection.outlook.com (10.167.248.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8857.21 via Frontend Transport; Thu, 19 Jun 2025 11:38:02 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 19 Jun 2025 04:37:49 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Thu, 19 Jun 2025 04:37:49 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Thu, 19 Jun 2025 04:37:45 -0700 From: Mark Bloch To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Simon Horman CC: , , , , Leon Romanovsky , Jonathan Corbet , , , , , Dragos Tatulea , Mark Bloch Subject: [PATCH net-next 5/5] net/mlx5e: Make PCIe congestion event thresholds configurable Date: Thu, 19 Jun 2025 14:37:21 +0300 Message-ID: <20250619113721.60201-6-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250619113721.60201-1-mbloch@nvidia.com> References: <20250619113721.60201-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00036F3C:EE_|DS0PR12MB9323:EE_ X-MS-Office365-Filtering-Correlation-Id: b32bed53-355f-4247-8d0d-08ddaf25bfb7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|7416014|376014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?KthX3GGuTC1gku/XclxF+/nXlrYCkORTpqykF/4+gEfVEGvdc3ht+UOIcCrA?= =?us-ascii?Q?ryv0wfw+EUJNSHJV6oAa49TTHokU13xgOSje+8wKFmJEg36HAAjM35vnz4G9?= =?us-ascii?Q?qRWkt2DoOArxN5TDrGHHIFcZM7xVSPmiGUQIXD5ZPrzl/KINQ5n+YvdNV+Nn?= =?us-ascii?Q?c0MOoSOeJ6Sz+eOaVBwnfPRVi9HXkpONI6Wd+3OW+xQ9NSkh7afuFX5ogH9l?= =?us-ascii?Q?Vd/UDrLR2MDY+JeZN7jh3fgS8uoUn84lpfO0DGjwzOxIbtcBK44uNr3EqcQz?= =?us-ascii?Q?Tk2ibFhkU//cQt/A3BxwXuM43OysrhQ/9es8lRgkYC9qgDx5Revtk+bWcSSx?= =?us-ascii?Q?yXGVpB5Yqri9yDNGkSVysEZr/PPNiDSGFZtHqyJis92QFLJerzBHBhV/bweC?= =?us-ascii?Q?3Mm9Ajz8HPvcsqVsWyWiqNtFTs7oShoZIKf7ThUx0LXJFK2i7D1MM+0bBEzo?= =?us-ascii?Q?x6kDfS5RiwOoFBpXKix9Qrt3RtfSYH457isUyNISB+51x2nShCbiSF7mnDNG?= =?us-ascii?Q?ayapppD5tj3/IFWqQ1dqawhCCoebHFMEQ5zH2Ss9LBJJYcf88iG3xkzbNvoE?= =?us-ascii?Q?t6TJMcxXO3Q6pg38cI3OTx3FlEZZsoirL+HybdAxV0dqJg+ZBmzqKv37JMzp?= =?us-ascii?Q?bluZ3zVMEQBoeVffEQZvWbXTY+rRv0ci/2ULDLg7Yg2JARayhN05pVlzo1Nr?= =?us-ascii?Q?WjAqunwhoPwnR8N+/zDJ+sE6cbeyNrp8mXtojQGPDsIoqxY408bCIHeLB56Y?= =?us-ascii?Q?tBbKn+A7Vd955D0uV5IKSK1aajhn/ngLJa6arlhNyB9+q41FMB1P73eqPKgF?= =?us-ascii?Q?2uCJ0yi9nALfjGVcl7xpV21S7Q7/41xQ/rZIvv+84pMGAsVwc9yF22MZgtUh?= =?us-ascii?Q?CMGO2kzyZiQTzWq8h6RH5nR3UKS2hg/soT/vLSE2e3YEkFBinOR5ZokuV+kB?= =?us-ascii?Q?xhy2T0KFOlyLj8IYP+MUrlXRPQTyfSSVw7rAnmxmFHOtL4n+ZhsXIgs/AEIc?= =?us-ascii?Q?3jU2pHEv1RxQunKYhvY+83m6tmJEmUIUlhtSuIbNkiQW6QRxKl81WG/nm3VW?= =?us-ascii?Q?q1TS22sU+Cp5Sx9QZQ2IuH5tuB1rrUKUbhU/B/q5YZ6ApiESlFXyRpwr6eql?= =?us-ascii?Q?LQTVFvncxX1Z7spy+eope3SomMpPXZJ7R1j0QU6BWaMobv59ec7lQsrQ+PxL?= =?us-ascii?Q?9RJ5xAxnettkuMY/QkrTkTjxrG8BnuU7foNDvq8NBba/VwGntBL3U1iR1n4x?= =?us-ascii?Q?eKDda49WU9qfD1m2dC3RB0VT0W1RstM9RoJrJX6O6bF7XvF1AwOK/f4Hj92f?= =?us-ascii?Q?SxR1cC/2+SP9WNFsEtX8ujYvMlKgC/WC9VPLEOV8rEnKpU/Sn7Y63HsCN55O?= =?us-ascii?Q?w2PoMu1i6qrSeyrWKssqs2OP9nwAfimTdS2LGR0qKg9tM2wygrp6KUJPSEWD?= =?us-ascii?Q?+wzKU2WSn5NQMe0ne4mNBqx/noQ+fRoRIlVAzusQckTnN1x9sKi3QwiKIbba?= =?us-ascii?Q?uObNTTSLNtkSMFU5dNwvxBFeG6awO8yS5eCk?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(7416014)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2025 11:38:02.0175 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b32bed53-355f-4247-8d0d-08ddaf25bfb7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F3C.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9323 Content-Type: text/plain; charset="utf-8" From: Dragos Tatulea Add a new sysfs entry for reading and configuring the PCIe congestion event thresholds. The format is the following: Units are 0.01 %. Accepted values are in range (0, 10000]. When new thresholds are configured, a object modify operation will happen. The set function is updated accordingly to act as a modify as well. The threshold configuration is stored and queried directly in the firmware. To prevent fat fingering the numbers, read them initially as u64. Signed-off-by: Dragos Tatulea Reviewed-by: Tariq Toukan Signed-off-by: Mark Bloch --- .../mellanox/mlx5/core/en/pcie_cong_event.c | 152 +++++++++++++++++- 1 file changed, 144 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c b= /drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c index a24e5465ceeb..a74d1e15c92e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/pcie_cong_event.c @@ -39,9 +39,13 @@ struct mlx5e_pcie_cong_event { =20 /* For ethtool stats group. */ struct mlx5e_pcie_cong_stats stats; + + struct device_attribute attr; }; =20 /* In units of 0.01 % */ +#define MLX5E_PCIE_CONG_THRESH_MAX 10000 + static const struct mlx5e_pcie_cong_thresh default_thresh_config =3D { .inbound_high =3D 9000, .inbound_low =3D 7500, @@ -97,6 +101,7 @@ MLX5E_DEFINE_STATS_GRP(pcie_cong, 0); static int mlx5_cmd_pcie_cong_event_set(struct mlx5_core_dev *dev, const struct mlx5e_pcie_cong_thresh *config, + bool modify, u64 *obj_id) { u32 in[MLX5_ST_SZ_DW(pcie_cong_event_cmd_in)] =3D {}; @@ -108,8 +113,16 @@ mlx5_cmd_pcie_cong_event_set(struct mlx5_core_dev *dev, hdr =3D MLX5_ADDR_OF(pcie_cong_event_cmd_in, in, hdr); cong_obj =3D MLX5_ADDR_OF(pcie_cong_event_cmd_in, in, cong_obj); =20 - MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, - MLX5_CMD_OP_CREATE_GENERAL_OBJECT); + if (!modify) { + MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, + MLX5_CMD_OP_CREATE_GENERAL_OBJECT); + } else { + MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, + MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); + MLX5_SET(general_obj_in_cmd_hdr, in, obj_id, *obj_id); + MLX5_SET64(pcie_cong_event_obj, cong_obj, modify_select_field, + MLX5_PCIE_CONG_EVENT_MOD_THRESH); + } =20 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT); @@ -131,10 +144,12 @@ mlx5_cmd_pcie_cong_event_set(struct mlx5_core_dev *de= v, if (err) return err; =20 - *obj_id =3D MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); + if (!modify) + *obj_id =3D MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); =20 - mlx5_core_dbg(dev, "PCIe congestion event (obj_id=3D%llu) created. Config= : in: [%u, %u], out: [%u, %u]\n", + mlx5_core_dbg(dev, "PCIe congestion event (obj_id=3D%llu) %s. Config: in:= [%u, %u], out: [%u, %u]\n", *obj_id, + modify ? "modified" : "created", config->inbound_high, config->inbound_low, config->outbound_high, config->outbound_low); =20 @@ -160,13 +175,13 @@ static int mlx5_cmd_pcie_cong_event_destroy(struct ml= x5_core_dev *dev, =20 static int mlx5_cmd_pcie_cong_event_query(struct mlx5_core_dev *dev, u64 obj_id, - u32 *state) + u32 *state, + struct mlx5e_pcie_cong_thresh *config) { u32 in[MLX5_ST_SZ_DW(pcie_cong_event_cmd_in)] =3D {}; u32 out[MLX5_ST_SZ_DW(pcie_cong_event_cmd_out)]; void *obj; void *hdr; - u8 cong; int err; =20 hdr =3D MLX5_ADDR_OF(pcie_cong_event_cmd_in, in, hdr); @@ -184,6 +199,8 @@ static int mlx5_cmd_pcie_cong_event_query(struct mlx5_c= ore_dev *dev, obj =3D MLX5_ADDR_OF(pcie_cong_event_cmd_out, out, cong_obj); =20 if (state) { + u8 cong; + cong =3D MLX5_GET(pcie_cong_event_obj, obj, inbound_cong_state); if (cong =3D=3D MLX5E_CONG_HIGH_STATE) *state |=3D MLX5E_INBOUND_CONG; @@ -193,6 +210,19 @@ static int mlx5_cmd_pcie_cong_event_query(struct mlx5_= core_dev *dev, *state |=3D MLX5E_OUTBOUND_CONG; } =20 + if (config) { + *config =3D (struct mlx5e_pcie_cong_thresh) { + .inbound_low =3D MLX5_GET(pcie_cong_event_obj, obj, + inbound_cong_low_threshold), + .inbound_high =3D MLX5_GET(pcie_cong_event_obj, obj, + inbound_cong_high_threshold), + .outbound_low =3D MLX5_GET(pcie_cong_event_obj, obj, + outbound_cong_low_threshold), + .outbound_high =3D MLX5_GET(pcie_cong_event_obj, obj, + outbound_cong_high_threshold), + }; + } + return 0; } =20 @@ -210,7 +240,7 @@ static void mlx5e_pcie_cong_event_work(struct work_stru= ct *work) dev =3D priv->mdev; =20 err =3D mlx5_cmd_pcie_cong_event_query(dev, cong_event->obj_id, - &new_cong_state); + &new_cong_state, NULL); if (err) { mlx5_core_warn(dev, "Error %d when querying PCIe cong event object (obj_= id=3D%llu).\n", err, cong_event->obj_id); @@ -249,6 +279,101 @@ static int mlx5e_pcie_cong_event_handler(struct notif= ier_block *nb, return NOTIFY_OK; } =20 +static bool mlx5e_thresh_check_val(u64 val) +{ + return val > 0 && val <=3D MLX5E_PCIE_CONG_THRESH_MAX; +} + +static bool +mlx5e_thresh_config_check_order(const struct mlx5e_pcie_cong_thresh *confi= g) +{ + if (config->inbound_high <=3D config->inbound_low) + return false; + + if (config->outbound_high <=3D config->outbound_low) + return false; + + return true; +} + +#define MLX5E_PCIE_CONG_THRESH_SYSFS_VALUES 4 + +static ssize_t thresh_config_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct mlx5e_pcie_cong_thresh config =3D {}; + struct mlx5e_pcie_cong_event *cong_event; + u64 outbound_high, outbound_low; + u64 inbound_high, inbound_low; + struct mlx5e_priv *priv; + int ret; + int err; + + cong_event =3D container_of(attr, struct mlx5e_pcie_cong_event, attr); + priv =3D cong_event->priv; + + ret =3D sscanf(buf, "%llu %llu %llu %llu", + &inbound_low, &inbound_high, + &outbound_low, &outbound_high); + if (ret !=3D MLX5E_PCIE_CONG_THRESH_SYSFS_VALUES) { + mlx5_core_err(priv->mdev, "Invalid format for PCIe congestion threshold = configuration. Expected %d, got %d.\n", + MLX5E_PCIE_CONG_THRESH_SYSFS_VALUES, ret); + return -EINVAL; + } + + if (!mlx5e_thresh_check_val(inbound_high) || + !mlx5e_thresh_check_val(inbound_low) || + !mlx5e_thresh_check_val(outbound_high) || + !mlx5e_thresh_check_val(outbound_low)) { + mlx5_core_err(priv->mdev, "Invalid values for PCIe congestion threshold = configuration. Valid range [1, %d]\n", + MLX5E_PCIE_CONG_THRESH_MAX); + return -EINVAL; + } + + config =3D (struct mlx5e_pcie_cong_thresh) { + .inbound_low =3D inbound_low, + .inbound_high =3D inbound_high, + .outbound_low =3D outbound_low, + .outbound_high =3D outbound_high, + + }; + + if (!mlx5e_thresh_config_check_order(&config)) { + mlx5_core_err(priv->mdev, "Invalid order of values for PCIe congestion t= hreshold configuration.\n"); + return -EINVAL; + } + + err =3D mlx5_cmd_pcie_cong_event_set(priv->mdev, &config, + true, &cong_event->obj_id); + + return err ? err : count; +} + +static ssize_t thresh_config_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct mlx5e_pcie_cong_event *cong_event; + struct mlx5e_pcie_cong_thresh config; + struct mlx5e_priv *priv; + int err; + + cong_event =3D container_of(attr, struct mlx5e_pcie_cong_event, attr); + priv =3D cong_event->priv; + + err =3D mlx5_cmd_pcie_cong_event_query(priv->mdev, cong_event->obj_id, + NULL, &config); + + if (err) + return err; + + return sysfs_emit(buf, "%u %u %u %u\n", + config.inbound_low, config.inbound_high, + config.outbound_low, config.outbound_high); +} + bool mlx5e_pcie_cong_event_supported(struct mlx5_core_dev *dev) { u64 features =3D MLX5_CAP_GEN_2_64(dev, general_obj_types_127_64); @@ -283,7 +408,7 @@ int mlx5e_pcie_cong_event_init(struct mlx5e_priv *priv) cong_event->priv =3D priv; =20 err =3D mlx5_cmd_pcie_cong_event_set(mdev, &default_thresh_config, - &cong_event->obj_id); + false, &cong_event->obj_id); if (err) { mlx5_core_warn(mdev, "Error creating a PCIe congestion event object\n"); goto err_free; @@ -295,10 +420,20 @@ int mlx5e_pcie_cong_event_init(struct mlx5e_priv *pri= v) goto err_obj_destroy; } =20 + cong_event->attr =3D (struct device_attribute)__ATTR_RW(thresh_config); + err =3D sysfs_create_file(&mdev->device->kobj, + &cong_event->attr.attr); + if (err) { + mlx5_core_warn(mdev, "Error creating a sysfs entry for pcie_cong limits.= \n"); + goto err_unregister_nb; + } + priv->cong_event =3D cong_event; =20 return 0; =20 +err_unregister_nb: + mlx5_eq_notifier_unregister(mdev, &cong_event->nb); err_obj_destroy: mlx5_cmd_pcie_cong_event_destroy(mdev, cong_event->obj_id); err_free: @@ -316,6 +451,7 @@ void mlx5e_pcie_cong_event_cleanup(struct mlx5e_priv *p= riv) return; =20 priv->cong_event =3D NULL; + sysfs_remove_file(&mdev->device->kobj, &cong_event->attr.attr); =20 mlx5_eq_notifier_unregister(mdev, &cong_event->nb); cancel_work_sync(&cong_event->work); --=20 2.34.1