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Reviewed-by: Lyude Paul Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/falcon.rs | 3 -- drivers/gpu/nova-core/firmware/fwsec.rs | 25 +++++++++ drivers/gpu/nova-core/gpu.rs | 90 +++++++++++++++++++++++++++++= ---- drivers/gpu/nova-core/regs.rs | 31 ++++++++++++ 4 files changed, 136 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index ba14cb24b80db89901191000a617bee683cbc060..fe4d3d458a6b105bfdd6257111d= 3eed8ed8aba7c 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -2,9 +2,6 @@ =20 //! Falcon microprocessor base support =20 -// To be removed when all code is used. -#![expect(dead_code)] - use core::ops::Deref; use core::time::Duration; use hal::FalconHal; diff --git a/drivers/gpu/nova-core/firmware/fwsec.rs b/drivers/gpu/nova-cor= e/firmware/fwsec.rs index de179c2011396fa789e868ec564b09eb48aa07ff..6058598ce76e25484cc4ebebd1b= e80b9dd1b469c 100644 --- a/drivers/gpu/nova-core/firmware/fwsec.rs +++ b/drivers/gpu/nova-core/firmware/fwsec.rs @@ -395,4 +395,29 @@ pub(crate) fn new( ucode: ucode_signed, }) } + + /// Loads the FWSEC firmware into `falcon` and execute it. + pub(crate) fn run( + &self, + dev: &Device, + falcon: &Falcon, + bar: &Bar0, + ) -> Result<()> { + // Reset falcon, load the firmware, and run it. + falcon + .reset(bar) + .inspect_err(|e| dev_err!(dev, "Failed to reset GSP falcon: {:= ?}\n", e))?; + falcon + .dma_load(bar, self) + .inspect_err(|e| dev_err!(dev, "Failed to load FWSEC firmware:= {:?}\n", e))?; + let (mbox0, _) =3D falcon + .boot(bar, Some(0), None) + .inspect_err(|e| dev_err!(dev, "Failed to boot FWSEC firmware:= {:?}\n", e))?; + if mbox0 !=3D 0 { + dev_err!(dev, "FWSEC firmware returned error {}\n", mbox0); + Err(EIO) + } else { + Ok(()) + } + } } diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index ba926162c1a016f7e1c88da50308fb0a8686924a..ae454c0e2fb4d485e99fbf9cd80= c2ebb89884887 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -188,6 +188,85 @@ fn drop(mut self: Pin<&mut Self>) { } =20 impl Gpu { + /// Helper function to load and run the FWSEC-FRTS firmware and confir= m that it has properly + /// created the WPR2 region. + /// + /// TODO: this needs to be moved into a larger type responsible for bo= oting the whole GSP + /// (`GspBooter`?). + fn run_fwsec_frts( + dev: &device::Device, + falcon: &Falcon, + bar: &Bar0, + bios: &Vbios, + fb_layout: &FbLayout, + ) -> Result<()> { + // Check that the WPR2 region does not already exists - if it does= , we cannot run + // FWSEC-FRTS until the GPU is reset. + if regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI::read(bar).higher_bound() != =3D 0 { + dev_err!( + dev, + "WPR2 region already exists - GPU needs to be reset to pro= ceed\n" + ); + return Err(EBUSY); + } + + let fwsec_frts =3D FwsecFirmware::new( + dev, + falcon, + bar, + bios, + FwsecCommand::Frts { + frts_addr: fb_layout.frts.start, + frts_size: fb_layout.frts.end - fb_layout.frts.start, + }, + )?; + + // Run FWSEC-FRTS to create the WPR2 region. + fwsec_frts.run(dev, falcon, bar)?; + + // SCRATCH_E contains the error code for FWSEC-FRTS. + let frts_status =3D regs::NV_PBUS_SW_SCRATCH_0E::read(bar).frts_er= r_code(); + if frts_status !=3D 0 { + dev_err!( + dev, + "FWSEC-FRTS returned with error code {:#x}", + frts_status + ); + + return Err(EIO); + } + + // Check that the WPR2 region has been created as we requested. + let (wpr2_lo, wpr2_hi) =3D ( + regs::NV_PFB_PRI_MMU_WPR2_ADDR_LO::read(bar).lower_bound(), + regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI::read(bar).higher_bound(), + ); + + match (wpr2_lo, wpr2_hi) { + (_, 0) =3D> { + dev_err!(dev, "WPR2 region not created after running FWSEC= -FRTS\n"); + + Err(EIO) + } + (wpr2_lo, _) if wpr2_lo !=3D fb_layout.frts.start =3D> { + dev_err!( + dev, + "WPR2 region created at unexpected address {:#x}; expe= cted {:#x}\n", + wpr2_lo, + fb_layout.frts.start, + ); + + Err(EIO) + } + (wpr2_lo, wpr2_hi) =3D> { + dev_dbg!(dev, "WPR2: {:#x}-{:#x}\n", wpr2_lo, wpr2_hi); + dev_dbg!(dev, "GPU instance built\n"); + + Ok(()) + } + } + } + pub(crate) fn new( pdev: &pci::Device, devres_bar: Devres, @@ -226,16 +305,7 @@ pub(crate) fn new( =20 let bios =3D Vbios::new(pdev, bar)?; =20 - let _fwsec_frts =3D FwsecFirmware::new( - pdev.as_ref(), - &gsp_falcon, - bar, - &bios, - FwsecCommand::Frts { - frts_addr: fb_layout.frts.start, - frts_size: fb_layout.frts.end - fb_layout.frts.start, - }, - )?; + Self::run_fwsec_frts(pdev.as_ref(), &gsp_falcon, bar, &bios, &fb_l= ayout)?; =20 Ok(pin_init!(Self { spec, diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 8ca7bcb5a93f4b60ee9ee488f26469af48e2f1d8..ccfaeed55cff90e66ac0acf37dc= bd0eb344994c5 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -42,6 +42,13 @@ pub(crate) fn chipset(self) -> Result { } } =20 +/* PBUS */ + +// TODO: this is an array of registers. +register!(NV_PBUS_SW_SCRATCH_0E@0x00001438 { + 31:16 frts_err_code as u16; +}); + /* PFB */ =20 register!(NV_PFB_NISO_FLUSH_SYSMEM_ADDR @ 0x00100c10 { @@ -73,6 +80,30 @@ pub(crate) fn usable_fb_size(self) -> u64 { } } =20 +register!(NV_PFB_PRI_MMU_WPR2_ADDR_LO@0x001fa824 { + 31:4 lo_val as u32, "Bits 12..40 of the lower (inclusive) bound of = the WPR2 region"; +}); + +impl NV_PFB_PRI_MMU_WPR2_ADDR_LO { + /// Returns the lower (inclusive) bound of the WPR2 region. + pub(crate) fn lower_bound(self) -> u64 { + (self.lo_val() as u64) << 12 + } +} + +register!(NV_PFB_PRI_MMU_WPR2_ADDR_HI@0x001fa828 { + 31:4 hi_val as u32, "Bits 12..40 of the higher (exclusive) bound of= the WPR2 region"; +}); + +impl NV_PFB_PRI_MMU_WPR2_ADDR_HI { + /// Returns the higher (exclusive) bound of the WPR2 region. + /// + /// A value of zero means the WPR2 region is not set. + pub(crate) fn higher_bound(self) -> u64 { + (self.hi_val() as u64) << 12 + } +} + /* PGC6 */ =20 register!(NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK @ 0x00118128= { --=20 2.49.0