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Do this early as it can be required to e.g. reset the GPU falcons. Chipsets capabilities differ in that respect, so this commit also introduces the FB HAL. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/fb.rs | 66 +++++++++++++++++++++++++++++++= ++++ drivers/gpu/nova-core/fb/hal.rs | 31 ++++++++++++++++ drivers/gpu/nova-core/fb/hal/ga100.rs | 45 ++++++++++++++++++++++++ drivers/gpu/nova-core/fb/hal/tu102.rs | 42 ++++++++++++++++++++++ drivers/gpu/nova-core/gpu.rs | 25 +++++++++++-- drivers/gpu/nova-core/nova_core.rs | 1 + drivers/gpu/nova-core/regs.rs | 10 ++++++ 7 files changed, 218 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs new file mode 100644 index 0000000000000000000000000000000000000000..308cd76edfee5a2e8a4cd979c20= da2ce51cb16a5 --- /dev/null +++ b/drivers/gpu/nova-core/fb.rs @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0 + +use kernel::prelude::*; +use kernel::types::ARef; +use kernel::{dev_warn, device}; + +use crate::dma::DmaObject; +use crate::driver::Bar0; +use crate::gpu::Chipset; + +mod hal; + +/// Type holding the sysmem flush memory page, a page of memory to be writ= ten into the +/// `NV_PFB_NISO_FLUSH_SYSMEM_ADDR*` registers and used to maintain memory= coherency. +/// +/// Users are responsible for manually calling [`Self::unregister`] before= dropping this object, or +/// the page might remain in use even after it has been freed. +pub(crate) struct SysmemFlush { + /// Chipset we are operating on. + chipset: Chipset, + device: ARef, + /// Keep the page alive as long as we need it. + page: DmaObject, +} + +impl SysmemFlush { + /// Allocate a memory page and register it as the sysmem flush page. + pub(crate) fn register( + dev: &device::Device, + bar: &Bar0, + chipset: Chipset, + ) -> Result { + let page =3D DmaObject::new(dev, kernel::bindings::PAGE_SIZE)?; + + hal::fb_hal(chipset).write_sysmem_flush_page(bar, page.dma_handle(= ))?; + + Ok(Self { + chipset, + device: dev.into(), + page, + }) + } + + /// Unregister the managed sysmem flush page. + /// + /// Users must make sure to call this method before dropping the objec= t. + pub(crate) fn unregister(self, bar: &Bar0) { + let hal =3D hal::fb_hal(self.chipset); + + if hal.read_sysmem_flush_page(bar) =3D=3D self.page.dma_handle() { + let _ =3D hal.write_sysmem_flush_page(bar, 0).inspect_err(|e| { + dev_warn!( + &self.device, + "failed to unregister sysmem flush page: {:?}", + e + ) + }); + } else { + // Another page has been registered after us for some reason -= warn as this is a bug. + dev_warn!( + &self.device, + "attempt to unregister a sysmem flush page that is not act= ive\n" + ); + } + } +} diff --git a/drivers/gpu/nova-core/fb/hal.rs b/drivers/gpu/nova-core/fb/hal= .rs new file mode 100644 index 0000000000000000000000000000000000000000..23eab57eec9f524e066d3324eb7= f5f2bf78481d2 --- /dev/null +++ b/drivers/gpu/nova-core/fb/hal.rs @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 + +use kernel::prelude::*; + +use crate::driver::Bar0; +use crate::gpu::Chipset; + +mod ga100; +mod tu102; + +pub(crate) trait FbHal { + /// Returns the address of the currently-registered sysmem flush page. + fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64; + + /// Register `addr` as the address of the sysmem flush page. + /// + /// This might fail if the address is too large for the receiving regi= ster. + fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result; +} + +/// Returns the HAL corresponding to `chipset`. +pub(super) fn fb_hal(chipset: Chipset) -> &'static dyn FbHal { + use Chipset::*; + + match chipset { + TU102 | TU104 | TU106 | TU117 | TU116 =3D> tu102::TU102_HAL, + GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD= 104 | AD106 | AD107 =3D> { + ga100::GA100_HAL + } + } +} diff --git a/drivers/gpu/nova-core/fb/hal/ga100.rs b/drivers/gpu/nova-core/= fb/hal/ga100.rs new file mode 100644 index 0000000000000000000000000000000000000000..7c10436c1c590d9b767c399b693= 70697fdf8d239 --- /dev/null +++ b/drivers/gpu/nova-core/fb/hal/ga100.rs @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 + +struct Ga100; + +use kernel::prelude::*; + +use crate::driver::Bar0; +use crate::fb::hal::FbHal; +use crate::regs; + +use super::tu102::FLUSH_SYSMEM_ADDR_SHIFT; + +pub(super) fn read_sysmem_flush_page_ga100(bar: &Bar0) -> u64 { + (regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::read(bar).adr_39_08() as u64) <<= FLUSH_SYSMEM_ADDR_SHIFT + | (regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI::read(bar).adr_63_40() a= s u64) + << FLUSH_SYSMEM_ADDR_SHIFT_HI +} + +pub(super) fn write_sysmem_flush_page_ga100(bar: &Bar0, addr: u64) { + regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI::default() + .set_adr_63_40((addr >> FLUSH_SYSMEM_ADDR_SHIFT_HI) as u32) + .write(bar); + regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::default() + .set_adr_39_08((addr >> FLUSH_SYSMEM_ADDR_SHIFT) as u32) + .write(bar); +} + +/// Shift applied to the sysmem address before it is written into +/// `NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI`, +const FLUSH_SYSMEM_ADDR_SHIFT_HI: u32 =3D 40; + +impl FbHal for Ga100 { + fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { + read_sysmem_flush_page_ga100(bar) + } + + fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { + write_sysmem_flush_page_ga100(bar, addr); + + Ok(()) + } +} + +const GA100: Ga100 =3D Ga100; +pub(super) const GA100_HAL: &dyn FbHal =3D &GA100; diff --git a/drivers/gpu/nova-core/fb/hal/tu102.rs b/drivers/gpu/nova-core/= fb/hal/tu102.rs new file mode 100644 index 0000000000000000000000000000000000000000..048859f9fd9d6cfb630da0a8c35= 13becf3ab62d6 --- /dev/null +++ b/drivers/gpu/nova-core/fb/hal/tu102.rs @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0 + +use crate::driver::Bar0; +use crate::fb::hal::FbHal; +use crate::regs; +use kernel::prelude::*; + +/// Shift applied to the sysmem address before it is written into `NV_PFB_= NISO_FLUSH_SYSMEM_ADDR`, +/// to be used by HALs. +pub(super) const FLUSH_SYSMEM_ADDR_SHIFT: u32 =3D 8; + +pub(super) fn read_sysmem_flush_page_gm107(bar: &Bar0) -> u64 { + (regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::read(bar).adr_39_08() as u64) <<= FLUSH_SYSMEM_ADDR_SHIFT +} + +pub(super) fn write_sysmem_flush_page_gm107(bar: &Bar0, addr: u64) -> Resu= lt { + // Check that the address doesn't overflow the receiving 32-bit regist= er. + if addr >> (u32::BITS + FLUSH_SYSMEM_ADDR_SHIFT) =3D=3D 0 { + regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::default() + .set_adr_39_08((addr >> FLUSH_SYSMEM_ADDR_SHIFT) as u32) + .write(bar); + + Ok(()) + } else { + Err(EINVAL) + } +} + +struct Tu102; + +impl FbHal for Tu102 { + fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { + read_sysmem_flush_page_gm107(bar) + } + + fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { + write_sysmem_flush_page_gm107(bar, addr) + } +} + +const TU102: Tu102 =3D Tu102; +pub(super) const TU102_HAL: &dyn FbHal =3D &TU102; diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index e44ff6fa07147c6dd1515c2c6c0df927a2257c85..768579dfdfc7e9e61c613202030= d2c7ee6054e2a 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -3,6 +3,7 @@ use kernel::{device, devres::Devres, error::code::*, pci, prelude::*}; =20 use crate::driver::Bar0; +use crate::fb::SysmemFlush; use crate::firmware::{Firmware, FIRMWARE_VERSION}; use crate::gfw; use crate::regs; @@ -158,12 +159,28 @@ fn new(bar: &Bar0) -> Result { } =20 /// Structure holding the resources required to operate the GPU. -#[pin_data] +#[pin_data(PinnedDrop)] pub(crate) struct Gpu { spec: Spec, /// MMIO mapping of PCI BAR 0 bar: Devres, fw: Firmware, + /// System memory page required for flushing all pending GPU-side memo= ry writes done through + /// PCIE into system memory. + /// + /// We use an `Option` so we can take the object during `drop`. It is = not accessed otherwise. + sysmem_flush: Option, +} + +#[pinned_drop] +impl PinnedDrop for Gpu { + fn drop(mut self: Pin<&mut Self>) { + // Unregister the sysmem flush page before we release it. + let _ =3D self + .sysmem_flush + .take() + .map(|sysmem_flush| self.bar.try_access_with(|b| sysmem_flush.= unregister(b))); + } } =20 impl Gpu { @@ -187,10 +204,14 @@ pub(crate) fn new( gfw::wait_gfw_boot_completion(bar) .inspect_err(|_| dev_err!(pdev.as_ref(), "GFW boot did not com= plete"))?; =20 + // System memory page required for sysmembar to properly flush int= o system memory. + let sysmem_flush =3D SysmemFlush::register(pdev.as_ref(), bar, spe= c.chipset)?; + Ok(pin_init!(Self { spec, bar: devres_bar, - fw + fw, + sysmem_flush: Some(sysmem_flush), })) } } diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nov= a_core.rs index 121fe5c11044a192212d0a64353b7acad58c796a..8ac04b8586e7314528e081464ed= 73ee615001e9b 100644 --- a/drivers/gpu/nova-core/nova_core.rs +++ b/drivers/gpu/nova-core/nova_core.rs @@ -4,6 +4,7 @@ =20 mod dma; mod driver; +mod fb; mod firmware; mod gfw; mod gpu; diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index cba442da51181971f209b338249307c11ac481e3..b599e7ddad57ed8defe03240565= 71ba46b926cf6 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -38,6 +38,16 @@ pub(crate) fn chipset(self) -> Result { } } =20 +/* PFB */ + +register!(NV_PFB_NISO_FLUSH_SYSMEM_ADDR @ 0x00100c10 { + 31:0 adr_39_08 as u32; +}); + +register!(NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI @ 0x00100c40 { + 23:0 adr_63_40 as u32; +}); + /* PGC6 */ =20 register!(NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK @ 0x00118128= { --=20 2.49.0