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Signed-off-by: Alexandre Courbot --- rust/kernel/dma.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rust/kernel/dma.rs b/rust/kernel/dma.rs index a33261c62e0c2d3c2c9e92a4c058faab594e5355..5fb54714a1600d97b30b24f3440= 81f5558d43452 100644 --- a/rust/kernel/dma.rs +++ b/rust/kernel/dma.rs @@ -212,7 +212,7 @@ pub fn start_ptr_mut(&mut self) -> *mut T { self.cpu_addr } =20 - /// Returns a DMA handle which may given to the device as the DMA addr= ess base of + /// Returns a DMA handle which may be given to the device as the DMA a= ddress base of /// the region. pub fn dma_handle(&self) -> bindings::dma_addr_t { self.dma_handle --=20 2.49.0 From nobody Fri Dec 19 02:53:47 2025 Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2079.outbound.protection.outlook.com [40.107.102.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3F6C25D214; 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Signed-off-by: Alexandre Courbot --- rust/kernel/dma.rs | 32 ++++++++++++++++++++++++++------ 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/rust/kernel/dma.rs b/rust/kernel/dma.rs index 5fb54714a1600d97b30b24f344081f5558d43452..15ff639b3067d0e4a39e181bbe7= 09a9c372a591a 100644 --- a/rust/kernel/dma.rs +++ b/rust/kernel/dma.rs @@ -114,9 +114,11 @@ pub mod attrs { /// /// # Invariants /// -/// For the lifetime of an instance of [`CoherentAllocation`], the `cpu_ad= dr` is a valid pointer -/// to an allocated region of consistent memory and `dma_handle` is the DM= A address base of -/// the region. +/// - For the lifetime of an instance of [`CoherentAllocation`], the `cpu_= addr` is a valid pointer +/// to an allocated region of consistent memory and `dma_handle` is the = DMA address base of the +/// region. +/// - The size in bytes of the allocation is equal to `size_of:: * coun= t`. +/// - `size_of:: * count` fits into a `usize`. // TODO // // DMA allocations potentially carry device resources (e.g.IOMMU mappings)= , hence for soundness @@ -179,9 +181,12 @@ pub fn alloc_attrs( if ret.is_null() { return Err(ENOMEM); } - // INVARIANT: We just successfully allocated a coherent region whi= ch is accessible for - // `count` elements, hence the cpu address is valid. We also hold = a refcounted reference - // to the device. + // INVARIANT: + // - We just successfully allocated a coherent region which is acc= essible for + // `count` elements, hence the cpu address is valid. We also hol= d a refcounted reference + // to the device. + // - The allocated `size` is equal to `size_of:: * count`. + // - The allocated `size` fits into a `usize`. Ok(Self { dev: dev.into(), dma_handle, @@ -201,6 +206,21 @@ pub fn alloc_coherent( CoherentAllocation::alloc_attrs(dev, count, gfp_flags, Attrs(0)) } =20 + /// Returns the number of elements `T` in this allocation. + /// + /// Note that this is not the size of the allocation in bytes, which i= s provided by + /// [`Self::size`]. + pub fn count(&self) -> usize { + self.count + } + + /// Returns the size in bytes of this allocation. + pub fn size(&self) -> usize { + // INVARIANT: The type invariant of `Self` guarantees that `size_o= f:: * count` fits into + // a `usize`. + self.count * core::mem::size_of::() + } + /// Returns the base address to the allocated region in the CPU's virt= ual address space. pub fn start_ptr(&self) -> *const T { self.cpu_addr --=20 2.49.0 From nobody Fri Dec 19 02:53:47 2025 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2075.outbound.protection.outlook.com [40.107.237.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 089AE25CC57; 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This can be done by adding said offset to the result of `dma_handle()`, but doing so on the client side carries the risk that the operation will go outside the bounds of the allocation. Thus, add a `dma_handle_with_offset` method that adds the desired offset after checking that it is still valid. Signed-off-by: Alexandre Courbot --- rust/kernel/dma.rs | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/rust/kernel/dma.rs b/rust/kernel/dma.rs index 15ff639b3067d0e4a39e181bbe709a9c372a591a..04546e58252d308e7a9f17bd2ea= e0aebfdc3c271 100644 --- a/rust/kernel/dma.rs +++ b/rust/kernel/dma.rs @@ -238,6 +238,20 @@ pub fn dma_handle(&self) -> bindings::dma_addr_t { self.dma_handle } =20 + /// Returns a DMA handle starting at `offset` (in units of `T`) which = may be given to the + /// device as the DMA address base of the region. + /// + /// Returns `EINVAL` if `offset` is not within the bounds of the alloc= ation. + pub fn dma_handle_with_offset(&self, offset: usize) -> Result { + if offset >=3D self.count { + Err(EINVAL) + } else { + // INVARIANT: The type invariant of `Self` guarantees that `si= ze_of:: * count` fits + // into a `usize`, and `offset` is inferior to `count`. + Ok(self.dma_handle + (offset * core::mem::size_of::()) as b= indings::dma_addr_t) + } + } + /// Returns a pointer to an element from the region with bounds checki= ng. `offset` is in /// units of `T`, not the number of bytes. /// --=20 2.49.0 From nobody Fri Dec 19 02:53:47 2025 Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2072.outbound.protection.outlook.com [40.107.102.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF63C25EF8F; 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Reviewed-by: Benno Lossin Signed-off-by: Alexandre Courbot Acked-by: Miguel Ojeda --- rust/kernel/error.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/rust/kernel/error.rs b/rust/kernel/error.rs index 3dee3139fcd4379b94748c0ba1965f4e1865b633..083c7b068cf4e185100de96e520= c54437898ee72 100644 --- a/rust/kernel/error.rs +++ b/rust/kernel/error.rs @@ -65,6 +65,7 @@ macro_rules! declare_err { declare_err!(EDOM, "Math argument out of domain of func."); declare_err!(ERANGE, "Math result not representable."); declare_err!(EOVERFLOW, "Value too large for defined data type."); + declare_err!(ETIMEDOUT, "Connection timed out."); declare_err!(ERESTARTSYS, "Restart the system call."); declare_err!(ERESTARTNOINTR, "System call was interrupted by a signal = and will be restarted."); declare_err!(ERESTARTNOHAND, "Restart if no handler."); --=20 2.49.0 From nobody Fri Dec 19 02:53:47 2025 Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2050.outbound.protection.outlook.com [40.107.102.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9FA6D26056D; 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Reviewed-by: Boqun Feng Signed-off-by: Alexandre Courbot Acked-by: Miguel Ojeda --- rust/kernel/sizes.rs | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/rust/kernel/sizes.rs b/rust/kernel/sizes.rs index 834c343e4170f507821b870e77afd08e2392911f..661e680d9330616478513a19fe2= f87f9521516d7 100644 --- a/rust/kernel/sizes.rs +++ b/rust/kernel/sizes.rs @@ -24,3 +24,27 @@ pub const SZ_256K: usize =3D bindings::SZ_256K as usize; /// 0x00080000 pub const SZ_512K: usize =3D bindings::SZ_512K as usize; +/// 0x00100000 +pub const SZ_1M: usize =3D bindings::SZ_1M as usize; +/// 0x00200000 +pub const SZ_2M: usize =3D bindings::SZ_2M as usize; +/// 0x00400000 +pub const SZ_4M: usize =3D bindings::SZ_4M as usize; +/// 0x00800000 +pub const SZ_8M: usize =3D bindings::SZ_8M as usize; +/// 0x01000000 +pub const SZ_16M: usize =3D bindings::SZ_16M as usize; +/// 0x02000000 +pub const SZ_32M: usize =3D bindings::SZ_32M as usize; +/// 0x04000000 +pub const SZ_64M: usize =3D bindings::SZ_64M as usize; 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Reviewed-by: Lyude Paul Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/regs/macros.rs | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/r= egs/macros.rs index 7ecc70efb3cd723b673cd72915e72b8a4a009f06..40bf9346cd0699ede05cfddff5d= 39822c696c164 100644 --- a/drivers/gpu/nova-core/regs/macros.rs +++ b/drivers/gpu/nova-core/regs/macros.rs @@ -114,7 +114,7 @@ fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::= core::fmt::Result { } } =20 - impl core::ops::BitOr for $name { + impl ::core::ops::BitOr for $name { type Output =3D Self; =20 fn bitor(self, rhs: Self) -> Self::Output { @@ -161,7 +161,7 @@ impl $name { (@check_field_bounds $hi:tt:$lo:tt $field:ident as bool) =3D> { #[allow(clippy::eq_op)] const _: () =3D { - kernel::build_assert!( + ::kernel::build_assert!( $hi =3D=3D $lo, concat!("boolean field `", stringify!($field), "` covers m= ore than one bit") ); @@ -172,7 +172,7 @@ impl $name { (@check_field_bounds $hi:tt:$lo:tt $field:ident as $type:tt) =3D> { #[allow(clippy::eq_op)] const _: () =3D { - kernel::build_assert!( + ::kernel::build_assert!( $hi >=3D $lo, concat!("field `", stringify!($field), "`'s MSB is smaller= than its LSB") ); @@ -234,7 +234,7 @@ impl $name { @leaf_accessor $name:ident $hi:tt:$lo:tt $field:ident as $type:ty { $process:expr } $to_type:ty =3D> $res_type:ty $(, $comment:l= iteral)?; ) =3D> { - kernel::macros::paste!( + ::kernel::macros::paste!( const [<$field:upper>]: ::core::ops::RangeInclusive =3D $lo..= =3D$hi; const [<$field:upper _MASK>]: u32 =3D ((((1 << $hi) - 1) << 1) + 1= ) - ((1 << $lo) - 1); const [<$field:upper _SHIFT>]: u32 =3D Self::[<$field:upper _MASK>= ].trailing_zeros(); @@ -246,7 +246,7 @@ impl $name { )? #[inline] pub(crate) fn $field(self) -> $res_type { - kernel::macros::paste!( + ::kernel::macros::paste!( const MASK: u32 =3D $name::[<$field:upper _MASK>]; const SHIFT: u32 =3D $name::[<$field:upper _SHIFT>]; ); @@ -255,7 +255,7 @@ pub(crate) fn $field(self) -> $res_type { $process(field) } =20 - kernel::macros::paste!( + ::kernel::macros::paste!( $( #[doc=3D"Sets the value of this field:"] #[doc=3D$comment] --=20 2.49.0 From nobody Fri Dec 19 02:53:47 2025 Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2049.outbound.protection.outlook.com [40.107.101.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45937266B56; 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Reviewed-by: Lyude Paul Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/regs/macros.rs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/r= egs/macros.rs index 40bf9346cd0699ede05cfddff5d39822c696c164..d7f09026390b4ccb1c969f2b29c= af07fa9204a77 100644 --- a/drivers/gpu/nova-core/regs/macros.rs +++ b/drivers/gpu/nova-core/regs/macros.rs @@ -94,6 +94,8 @@ macro_rules! register { register!(@io$name @ + $offset); }; =20 + // All rules below are helpers. + // Defines the wrapper `$name` type, as well as its relevant implement= ations (`Debug`, `BitOr`, // and conversion to regular `u32`). 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Expose the offset of each register using a type constant to avoid resorting to hardcoded values. Reviewed-by: Lyude Paul Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/regs/macros.rs | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/r= egs/macros.rs index d7f09026390b4ccb1c969f2b29caf07fa9204a77..7cd013f3c90bbd8ca437d4072ca= e8f11d7946fcd 100644 --- a/drivers/gpu/nova-core/regs/macros.rs +++ b/drivers/gpu/nova-core/regs/macros.rs @@ -78,7 +78,7 @@ macro_rules! register { $($fields:tt)* } ) =3D> { - register!(@common $name $(, $comment)?); + register!(@common $name @ $offset $(, $comment)?); register!(@field_accessors $name { $($fields)* }); register!(@io $name @ $offset); }; @@ -89,7 +89,7 @@ macro_rules! register { $($fields:tt)* } ) =3D> { - register!(@common $name $(, $comment)?); + register!(@common $name @ $offset $(, $comment)?); register!(@field_accessors $name { $($fields)* }); register!(@io$name @ + $offset); }; @@ -98,7 +98,7 @@ macro_rules! register { =20 // Defines the wrapper `$name` type, as well as its relevant implement= ations (`Debug`, `BitOr`, // and conversion to regular `u32`). - (@common $name:ident $(, $comment:literal)?) =3D> { + (@common $name:ident @ $offset:literal $(, $comment:literal)?) =3D> { $( #[doc=3D$comment] )? @@ -106,6 +106,11 @@ macro_rules! register { #[derive(Clone, Copy, Default)] pub(crate) struct $name(u32); =20 + #[allow(dead_code)] + impl $name { + pub(crate) const OFFSET: usize =3D $offset; + } + // TODO: display the raw hex value, then the value of all the fiel= ds. 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Expand the register!() macro to support a syntax indicating that a register type should be at the same offset as another one, but under a different name, and with different fields and documentation. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/regs/macros.rs | 40 ++++++++++++++++++++++++++++++++= ++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/r= egs/macros.rs index 7cd013f3c90bbd8ca437d4072cae8f11d7946fcd..e0e6fef3796f9dd2ce4e0223444= a05bcc53075a6 100644 --- a/drivers/gpu/nova-core/regs/macros.rs +++ b/drivers/gpu/nova-core/regs/macros.rs @@ -71,6 +71,20 @@ /// pr_info!("CPU CTL: {:#x}", cpuctl); /// cpuctl.set_start(true).write(&bar, CPU_BASE); /// ``` +/// +/// It is also possible to create a alias register by using the `=3D> ALIA= S` syntax. This is useful +/// for cases where a register's interpretation depends on the context: +/// +/// ```no_run +/// register!(SCRATCH_0 @ 0x0000100, "Scratch register 0" { +/// 31:0 value as u32, "Raw value"; +/// +/// register!(SCRATCH_0_BOOT_STATUS =3D> SCRATCH_0, "Boot status of the fi= rmware" { +/// 0:0 completed as bool, "Whether the firmware has completed boo= ting"; +/// ``` +/// +/// In this example, `SCRATCH_0_BOOT_STATUS` uses the same I/O address as = `SCRATCH_0`, while also +/// providing its own `completed` method. macro_rules! register { // Creates a register at a fixed offset of the MMIO space. ( @@ -83,6 +97,17 @@ macro_rules! register { register!(@io $name @ $offset); }; =20 + // Creates a alias register of fixed offset register `alias` with its = own fields. + ( + $name:ident =3D> $alias:ident $(, $comment:literal)? { + $($fields:tt)* + } + ) =3D> { + register!(@common $name @ $alias::OFFSET $(, $comment)?); + register!(@field_accessors $name { $($fields)* }); + register!(@io $name @ $alias::OFFSET); + }; + // Creates a register at a relative offset from a base address. ( $name:ident @ + $offset:literal $(, $comment:literal)? { @@ -94,11 +119,22 @@ macro_rules! register { register!(@io$name @ + $offset); }; =20 + // Creates a alias register of relative offset register `alias` with i= ts own fields. + ( + $name:ident =3D> + $alias:ident $(, $comment:literal)? { + $($fields:tt)* + } + ) =3D> { + register!(@common $name @ $alias::OFFSET $(, $comment)?); + register!(@field_accessors $name { $($fields)* }); + register!(@io $name @ + $alias::OFFSET); + }; + // All rules below are helpers. =20 // Defines the wrapper `$name` type, as well as its relevant implement= ations (`Debug`, `BitOr`, // and conversion to regular `u32`). - (@common $name:ident @ $offset:literal $(, $comment:literal)?) =3D> { + (@common $name:ident @ $offset:expr $(, $comment:literal)?) =3D> { $( #[doc=3D$comment] )? @@ -280,7 +316,7 @@ pub(crate) fn [](mut self, value: $to_type= ) -> Self { }; =20 // Creates the IO accessors for a fixed offset register. - (@io $name:ident @ $offset:literal) =3D> { + (@io $name:ident @ $offset:expr) =3D> { #[allow(dead_code)] impl $name { #[inline] --=20 2.49.0 From nobody Fri Dec 19 02:53:47 2025 Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2053.outbound.protection.outlook.com [40.107.101.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C993C26A0E7; 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Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/driver.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nova-core/driver.rs b/drivers/gpu/nova-core/driver= .rs index 8c86101c26cb5fe5eb9a3d03268338c6b58baef7..ffe25c7a2fdad289549460f7fd8= 7d6e09299a35c 100644 --- a/drivers/gpu/nova-core/driver.rs +++ b/drivers/gpu/nova-core/driver.rs @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 =20 -use kernel::{auxiliary, bindings, c_str, device::Core, pci, prelude::*}; +use kernel::{auxiliary, bindings, c_str, device::Core, pci, prelude::*, si= zes::SZ_16M}; =20 use crate::gpu::Gpu; =20 @@ -11,7 +11,7 @@ pub(crate) struct NovaCore { _reg: auxiliary::Registration, } =20 -const BAR0_SIZE: usize =3D 8; +const BAR0_SIZE: usize =3D SZ_16M; pub(crate) type Bar0 =3D pci::Bar; =20 kernel::pci_device_table!( --=20 2.49.0 From nobody Fri Dec 19 02:53:47 2025 Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2057.outbound.protection.outlook.com [40.107.100.57]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA37E25D559; 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Add a basic `wait_on` helper function to wait on such conditions expressed as a closure, with a timeout argument. This is temporary as we will switch to `read_poll_timeout` [1] once it is available. [1] https://lore.kernel.org/lkml/20250220070611.214262-8-fujita.tomonori@gm= ail.com/ Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/util.rs | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/gpu/nova-core/util.rs b/drivers/gpu/nova-core/util.rs index 332a64cfc6a9d7d787fbdc228887c0be53a97160..c50bfa5ab7fe385fae26c8909ae= 5984b96af618a 100644 --- a/drivers/gpu/nova-core/util.rs +++ b/drivers/gpu/nova-core/util.rs @@ -1,5 +1,10 @@ // SPDX-License-Identifier: GPL-2.0 =20 +use core::time::Duration; + +use kernel::prelude::*; +use kernel::time::Instant; + pub(crate) const fn to_lowercase_bytes(s: &str) -> [u8; N]= { let src =3D s.as_bytes(); let mut dst =3D [0; N]; @@ -19,3 +24,27 @@ pub(crate) const fn const_bytes_to_str(bytes: &[u8]) -> = &str { Err(_) =3D> kernel::build_error!("Bytes are not valid UTF-8."), } } + +/// Wait until `cond` is true or `timeout` elapsed. +/// +/// When `cond` evaluates to `Some`, its return value is returned. +/// +/// `Err(ETIMEDOUT)` is returned if `timeout` has been reached without `co= nd` evaluating to +/// `Some`. +/// +/// TODO: replace with `read_poll_timeout` once it is available. +/// (https://lore.kernel.org/lkml/20250220070611.214262-8-fujita.tomonori@= gmail.com/) +#[expect(dead_code)] +pub(crate) fn wait_on Option>(timeout: Duration, cond: F)= -> Result { + let start_time =3D Instant::now(); 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The driver must ensure that this step is completed before using the hardware. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/gfw.rs | 41 ++++++++++++++++++++++++++++++++++= ++++ drivers/gpu/nova-core/gpu.rs | 5 +++++ drivers/gpu/nova-core/nova_core.rs | 1 + drivers/gpu/nova-core/regs.rs | 25 +++++++++++++++++++++++ drivers/gpu/nova-core/util.rs | 1 - 5 files changed, 72 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nova-core/gfw.rs b/drivers/gpu/nova-core/gfw.rs new file mode 100644 index 0000000000000000000000000000000000000000..fa3f642bc814c7eea1ce1f2c2e2= 4e684d1ae5fda --- /dev/null +++ b/drivers/gpu/nova-core/gfw.rs @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! GPU Firmware (GFW) support. +//! +//! Upon reset, the GPU runs some firmware code from the BIOS to setup its= core parameters. Most of +//! the GPU is considered unusable until this step is completed, so we mus= t wait on it before +//! performing driver initialization. + +use core::time::Duration; + +use kernel::bindings; +use kernel::prelude::*; + +use crate::driver::Bar0; +use crate::regs; +use crate::util; + +/// Wait until `GFW` (GPU Firmware) completes, or a 4 seconds timeout elap= ses. +pub(crate) fn wait_gfw_boot_completion(bar: &Bar0) -> Result { + // TIMEOUT: arbitrarily large value. GFW starts running immediately af= ter the GPU is put out of + // reset, and should complete in less time than that. + util::wait_on(Duration::from_secs(4), || { + // Check that FWSEC has lowered its protection level before readin= g the GFW_BOOT + // status. + let gfw_booted =3D regs::NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_= LEVEL_MASK::read(bar) + .read_protection_level0() + && regs::NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT::read(= bar).completed(); + + if gfw_booted { + Some(()) + } else { + // Avoid busy-looping. + // SAFETY: msleep should be safe to call with any parameter. + // TODO: replace with [1] once it merges. + // [1] https://lore.kernel.org/rust-for-linux/20250423192857.1= 99712-6-fujita.tomonori@gmail.com/ + unsafe { bindings::msleep(1) }; + + None + } + }) +} diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 60b86f3702842dc2c8b06f092250a5bad3b97bf4..e44ff6fa07147c6dd1515c2c6c0= df927a2257c85 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -4,6 +4,7 @@ =20 use crate::driver::Bar0; use crate::firmware::{Firmware, FIRMWARE_VERSION}; +use crate::gfw; use crate::regs; use crate::util; use core::fmt; @@ -182,6 +183,10 @@ pub(crate) fn new( spec.revision ); =20 + // We must wait for GFW_BOOT completion before doing any significa= nt setup on the GPU. + gfw::wait_gfw_boot_completion(bar) + .inspect_err(|_| dev_err!(pdev.as_ref(), "GFW boot did not com= plete"))?; + Ok(pin_init!(Self { spec, bar: devres_bar, diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nov= a_core.rs index 618632f0abcc8f5ef6945a04fc084acc4ecbf20b..c3fde3e132ea658888851137ab4= 7fcb7b3637577 100644 --- a/drivers/gpu/nova-core/nova_core.rs +++ b/drivers/gpu/nova-core/nova_core.rs @@ -4,6 +4,7 @@ =20 mod driver; mod firmware; +mod gfw; mod gpu; mod regs; mod util; diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 5a12732303066f78b8ec5745096cef632ff3bfba..cba442da51181971f209b338249= 307c11ac481e3 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -37,3 +37,28 @@ pub(crate) fn chipset(self) -> Result { .and_then(Chipset::try_from) } } + +/* PGC6 */ + +register!(NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK @ 0x00118128= { + 0:0 read_protection_level0 as bool, "Set after FWSEC lowers its pr= otection level"; +}); + +// TODO: This is an array of registers. +register!(NV_PGC6_AON_SECURE_SCRATCH_GROUP_05 @ 0x00118234 { + 31:0 value as u32; +}); + +register!( + NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT =3D> NV_PGC6_AON_SECURE= _SCRATCH_GROUP_05, + "Scratch group 05 register 0 used as GFW boot progress indicator" { + 7:0 progress as u8, "Progress of GFW boot (0xff means completed= )"; + } +); + +impl NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT { + /// Returns `true` if GFW boot is completed. + pub(crate) fn completed(self) -> bool { + self.progress() =3D=3D 0xff + } +} diff --git a/drivers/gpu/nova-core/util.rs b/drivers/gpu/nova-core/util.rs index c50bfa5ab7fe385fae26c8909ae5984b96af618a..69f29238b25ed949b00def1b748= df3ff7567d83c 100644 --- a/drivers/gpu/nova-core/util.rs +++ b/drivers/gpu/nova-core/util.rs @@ -34,7 +34,6 @@ pub(crate) const fn const_bytes_to_str(bytes: &[u8]) -> &= str { /// /// TODO: replace with `read_poll_timeout` once it is available. /// (https://lore.kernel.org/lkml/20250220070611.214262-8-fujita.tomonori@= gmail.com/) -#[expect(dead_code)] pub(crate) fn wait_on Option>(timeout: Duration, cond: F)= -> Result { let start_time =3D Instant::now(); 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It is a light wrapper around CoherentAllocation. Reviewed-by: Lyude Paul Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/dma.rs | 61 ++++++++++++++++++++++++++++++++++= ++++ drivers/gpu/nova-core/nova_core.rs | 1 + 2 files changed, 62 insertions(+) diff --git a/drivers/gpu/nova-core/dma.rs b/drivers/gpu/nova-core/dma.rs new file mode 100644 index 0000000000000000000000000000000000000000..4b063aaef65ec4e2f476fc5ce9d= c25341b6660ca --- /dev/null +++ b/drivers/gpu/nova-core/dma.rs @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Simple DMA object wrapper. + +// To be removed when all code is used. +#![expect(dead_code)] + +use core::ops::{Deref, DerefMut}; + +use kernel::device; +use kernel::dma::CoherentAllocation; +use kernel::page::PAGE_SIZE; +use kernel::prelude::*; + +pub(crate) struct DmaObject { + dma: CoherentAllocation, +} + +impl DmaObject { + pub(crate) fn new(dev: &device::Device, len: usize) -> = Result { + let len =3D core::alloc::Layout::from_size_align(len, PAGE_SIZE) + .map_err(|_| EINVAL)? + .pad_to_align() + .size(); + let dma =3D CoherentAllocation::alloc_coherent(dev, len, GFP_KERNE= L | __GFP_ZERO)?; + + Ok(Self { dma }) + } + + pub(crate) fn from_data(dev: &device::Device, data: &[u= 8]) -> Result { + Self::new(dev, data.len()).map(|mut dma_obj| { + // TODO: replace with `CoherentAllocation::write()` once avail= able. + // SAFETY: + // - `dma_obj`'s size is at least `data.len()`. + // - We have just created this object and there is no other us= er at this stage. + unsafe { + core::ptr::copy_nonoverlapping( + data.as_ptr(), + dma_obj.dma.start_ptr_mut(), + data.len(), + ); + } + + dma_obj + }) + } +} + +impl Deref for DmaObject { + type Target =3D CoherentAllocation; + + fn deref(&self) -> &Self::Target { + &self.dma + } +} + +impl DerefMut for DmaObject { + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.dma + } +} diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nov= a_core.rs index c3fde3e132ea658888851137ab47fcb7b3637577..121fe5c11044a192212d0a64353= b7acad58c796a 100644 --- a/drivers/gpu/nova-core/nova_core.rs +++ b/drivers/gpu/nova-core/nova_core.rs @@ -2,6 +2,7 @@ =20 //! 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Do this early as it can be required to e.g. reset the GPU falcons. Chipsets capabilities differ in that respect, so this commit also introduces the FB HAL. Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/fb.rs | 66 +++++++++++++++++++++++++++++++= ++++ drivers/gpu/nova-core/fb/hal.rs | 31 ++++++++++++++++ drivers/gpu/nova-core/fb/hal/ga100.rs | 45 ++++++++++++++++++++++++ drivers/gpu/nova-core/fb/hal/tu102.rs | 42 ++++++++++++++++++++++ drivers/gpu/nova-core/gpu.rs | 25 +++++++++++-- drivers/gpu/nova-core/nova_core.rs | 1 + drivers/gpu/nova-core/regs.rs | 10 ++++++ 7 files changed, 218 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs new file mode 100644 index 0000000000000000000000000000000000000000..308cd76edfee5a2e8a4cd979c20= da2ce51cb16a5 --- /dev/null +++ b/drivers/gpu/nova-core/fb.rs @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0 + +use kernel::prelude::*; +use kernel::types::ARef; +use kernel::{dev_warn, device}; + +use crate::dma::DmaObject; +use crate::driver::Bar0; +use crate::gpu::Chipset; + +mod hal; + +/// Type holding the sysmem flush memory page, a page of memory to be writ= ten into the +/// `NV_PFB_NISO_FLUSH_SYSMEM_ADDR*` registers and used to maintain memory= coherency. +/// +/// Users are responsible for manually calling [`Self::unregister`] before= dropping this object, or +/// the page might remain in use even after it has been freed. +pub(crate) struct SysmemFlush { + /// Chipset we are operating on. + chipset: Chipset, + device: ARef, + /// Keep the page alive as long as we need it. + page: DmaObject, +} + +impl SysmemFlush { + /// Allocate a memory page and register it as the sysmem flush page. + pub(crate) fn register( + dev: &device::Device, + bar: &Bar0, + chipset: Chipset, + ) -> Result { + let page =3D DmaObject::new(dev, kernel::bindings::PAGE_SIZE)?; + + hal::fb_hal(chipset).write_sysmem_flush_page(bar, page.dma_handle(= ))?; + + Ok(Self { + chipset, + device: dev.into(), + page, + }) + } + + /// Unregister the managed sysmem flush page. + /// + /// Users must make sure to call this method before dropping the objec= t. + pub(crate) fn unregister(self, bar: &Bar0) { + let hal =3D hal::fb_hal(self.chipset); + + if hal.read_sysmem_flush_page(bar) =3D=3D self.page.dma_handle() { + let _ =3D hal.write_sysmem_flush_page(bar, 0).inspect_err(|e| { + dev_warn!( + &self.device, + "failed to unregister sysmem flush page: {:?}", + e + ) + }); + } else { + // Another page has been registered after us for some reason -= warn as this is a bug. + dev_warn!( + &self.device, + "attempt to unregister a sysmem flush page that is not act= ive\n" + ); + } + } +} diff --git a/drivers/gpu/nova-core/fb/hal.rs b/drivers/gpu/nova-core/fb/hal= .rs new file mode 100644 index 0000000000000000000000000000000000000000..23eab57eec9f524e066d3324eb7= f5f2bf78481d2 --- /dev/null +++ b/drivers/gpu/nova-core/fb/hal.rs @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 + +use kernel::prelude::*; + +use crate::driver::Bar0; +use crate::gpu::Chipset; + +mod ga100; +mod tu102; + +pub(crate) trait FbHal { + /// Returns the address of the currently-registered sysmem flush page. + fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64; + + /// Register `addr` as the address of the sysmem flush page. + /// + /// This might fail if the address is too large for the receiving regi= ster. + fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result; +} + +/// Returns the HAL corresponding to `chipset`. +pub(super) fn fb_hal(chipset: Chipset) -> &'static dyn FbHal { + use Chipset::*; + + match chipset { + TU102 | TU104 | TU106 | TU117 | TU116 =3D> tu102::TU102_HAL, + GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD= 104 | AD106 | AD107 =3D> { + ga100::GA100_HAL + } + } +} diff --git a/drivers/gpu/nova-core/fb/hal/ga100.rs b/drivers/gpu/nova-core/= fb/hal/ga100.rs new file mode 100644 index 0000000000000000000000000000000000000000..7c10436c1c590d9b767c399b693= 70697fdf8d239 --- /dev/null +++ b/drivers/gpu/nova-core/fb/hal/ga100.rs @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 + +struct Ga100; + +use kernel::prelude::*; + +use crate::driver::Bar0; +use crate::fb::hal::FbHal; +use crate::regs; + +use super::tu102::FLUSH_SYSMEM_ADDR_SHIFT; + +pub(super) fn read_sysmem_flush_page_ga100(bar: &Bar0) -> u64 { + (regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::read(bar).adr_39_08() as u64) <<= FLUSH_SYSMEM_ADDR_SHIFT + | (regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI::read(bar).adr_63_40() a= s u64) + << FLUSH_SYSMEM_ADDR_SHIFT_HI +} + +pub(super) fn write_sysmem_flush_page_ga100(bar: &Bar0, addr: u64) { + regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI::default() + .set_adr_63_40((addr >> FLUSH_SYSMEM_ADDR_SHIFT_HI) as u32) + .write(bar); + regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::default() + .set_adr_39_08((addr >> FLUSH_SYSMEM_ADDR_SHIFT) as u32) + .write(bar); +} + +/// Shift applied to the sysmem address before it is written into +/// `NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI`, +const FLUSH_SYSMEM_ADDR_SHIFT_HI: u32 =3D 40; + +impl FbHal for Ga100 { + fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { + read_sysmem_flush_page_ga100(bar) + } + + fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { + write_sysmem_flush_page_ga100(bar, addr); + + Ok(()) + } +} + +const GA100: Ga100 =3D Ga100; +pub(super) const GA100_HAL: &dyn FbHal =3D &GA100; diff --git a/drivers/gpu/nova-core/fb/hal/tu102.rs b/drivers/gpu/nova-core/= fb/hal/tu102.rs new file mode 100644 index 0000000000000000000000000000000000000000..048859f9fd9d6cfb630da0a8c35= 13becf3ab62d6 --- /dev/null +++ b/drivers/gpu/nova-core/fb/hal/tu102.rs @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0 + +use crate::driver::Bar0; +use crate::fb::hal::FbHal; +use crate::regs; +use kernel::prelude::*; + +/// Shift applied to the sysmem address before it is written into `NV_PFB_= NISO_FLUSH_SYSMEM_ADDR`, +/// to be used by HALs. +pub(super) const FLUSH_SYSMEM_ADDR_SHIFT: u32 =3D 8; + +pub(super) fn read_sysmem_flush_page_gm107(bar: &Bar0) -> u64 { + (regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::read(bar).adr_39_08() as u64) <<= FLUSH_SYSMEM_ADDR_SHIFT +} + +pub(super) fn write_sysmem_flush_page_gm107(bar: &Bar0, addr: u64) -> Resu= lt { + // Check that the address doesn't overflow the receiving 32-bit regist= er. + if addr >> (u32::BITS + FLUSH_SYSMEM_ADDR_SHIFT) =3D=3D 0 { + regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::default() + .set_adr_39_08((addr >> FLUSH_SYSMEM_ADDR_SHIFT) as u32) + .write(bar); + + Ok(()) + } else { + Err(EINVAL) + } +} + +struct Tu102; + +impl FbHal for Tu102 { + fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { + read_sysmem_flush_page_gm107(bar) + } + + fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { + write_sysmem_flush_page_gm107(bar, addr) + } +} + +const TU102: Tu102 =3D Tu102; +pub(super) const TU102_HAL: &dyn FbHal =3D &TU102; diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index e44ff6fa07147c6dd1515c2c6c0df927a2257c85..768579dfdfc7e9e61c613202030= d2c7ee6054e2a 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -3,6 +3,7 @@ use kernel::{device, devres::Devres, error::code::*, pci, prelude::*}; =20 use crate::driver::Bar0; +use crate::fb::SysmemFlush; use crate::firmware::{Firmware, FIRMWARE_VERSION}; use crate::gfw; use crate::regs; @@ -158,12 +159,28 @@ fn new(bar: &Bar0) -> Result { } =20 /// Structure holding the resources required to operate the GPU. -#[pin_data] +#[pin_data(PinnedDrop)] pub(crate) struct Gpu { spec: Spec, /// MMIO mapping of PCI BAR 0 bar: Devres, fw: Firmware, + /// System memory page required for flushing all pending GPU-side memo= ry writes done through + /// PCIE into system memory. + /// + /// We use an `Option` so we can take the object during `drop`. It is = not accessed otherwise. + sysmem_flush: Option, +} + +#[pinned_drop] +impl PinnedDrop for Gpu { + fn drop(mut self: Pin<&mut Self>) { + // Unregister the sysmem flush page before we release it. + let _ =3D self + .sysmem_flush + .take() + .map(|sysmem_flush| self.bar.try_access_with(|b| sysmem_flush.= unregister(b))); + } } =20 impl Gpu { @@ -187,10 +204,14 @@ pub(crate) fn new( gfw::wait_gfw_boot_completion(bar) .inspect_err(|_| dev_err!(pdev.as_ref(), "GFW boot did not com= plete"))?; =20 + // System memory page required for sysmembar to properly flush int= o system memory. + let sysmem_flush =3D SysmemFlush::register(pdev.as_ref(), bar, spe= c.chipset)?; + Ok(pin_init!(Self { spec, bar: devres_bar, - fw + fw, + sysmem_flush: Some(sysmem_flush), })) } } diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nov= a_core.rs index 121fe5c11044a192212d0a64353b7acad58c796a..8ac04b8586e7314528e081464ed= 73ee615001e9b 100644 --- a/drivers/gpu/nova-core/nova_core.rs +++ b/drivers/gpu/nova-core/nova_core.rs @@ -4,6 +4,7 @@ =20 mod dma; mod driver; +mod fb; mod firmware; mod gfw; mod gpu; diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index cba442da51181971f209b338249307c11ac481e3..b599e7ddad57ed8defe03240565= 71ba46b926cf6 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -38,6 +38,16 @@ pub(crate) fn chipset(self) -> Result { } } =20 +/* PFB */ + +register!(NV_PFB_NISO_FLUSH_SYSMEM_ADDR @ 0x00100c10 { + 31:0 adr_39_08 as u32; +}); + +register!(NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI @ 0x00100c40 { + 23:0 adr_63_40 as u32; +}); + /* PGC6 */ =20 register!(NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK @ 0x00118128= { --=20 2.49.0 From nobody Fri Dec 19 02:53:47 2025 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2063.outbound.protection.outlook.com [40.107.92.63]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0E6826F445; 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Add the common Falcon code and HAL for Ampere GPUs, and instantiate the GSP and SEC2 Falcons that will be required to perform that dance and boot the GSP. Thanks to Ben Skeggs for pointing out an important bug in the memory scrubbing code that could lead to a race condition and ultimately a failure to boot the GSP! Reviewed-by: Lyude Paul Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/falcon.rs | 551 ++++++++++++++++++++++++++= ++++ drivers/gpu/nova-core/falcon/gsp.rs | 24 ++ drivers/gpu/nova-core/falcon/hal.rs | 54 +++ drivers/gpu/nova-core/falcon/hal/ga102.rs | 119 +++++++ drivers/gpu/nova-core/falcon/sec2.rs | 10 + drivers/gpu/nova-core/gpu.rs | 11 + drivers/gpu/nova-core/nova_core.rs | 1 + drivers/gpu/nova-core/regs.rs | 146 ++++++++ 8 files changed, 916 insertions(+) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs new file mode 100644 index 0000000000000000000000000000000000000000..ba14cb24b80db89901191000a61= 7bee683cbc060 --- /dev/null +++ b/drivers/gpu/nova-core/falcon.rs @@ -0,0 +1,551 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Falcon microprocessor base support + +// To be removed when all code is used. +#![expect(dead_code)] + +use core::ops::Deref; +use core::time::Duration; +use hal::FalconHal; +use kernel::bindings; +use kernel::device; +use kernel::prelude::*; +use kernel::types::ARef; + +use crate::dma::DmaObject; +use crate::driver::Bar0; +use crate::gpu::Chipset; +use crate::regs; +use crate::util; + +pub(crate) mod gsp; +mod hal; +pub(crate) mod sec2; + +/// Revision number of a falcon core, used in the [`crate::regs::NV_PFALCO= N_FALCON_HWCFG1`] +/// register. +#[repr(u8)] +#[derive(Debug, Default, Copy, Clone, PartialEq, Eq, PartialOrd, Ord)] +pub(crate) enum FalconCoreRev { + #[default] + Rev1 =3D 1, + Rev2 =3D 2, + Rev3 =3D 3, + Rev4 =3D 4, + Rev5 =3D 5, + Rev6 =3D 6, + Rev7 =3D 7, +} + +impl TryFrom for FalconCoreRev { + type Error =3D Error; + + fn try_from(value: u8) -> Result { + use FalconCoreRev::*; + + let rev =3D match value { + 1 =3D> Rev1, + 2 =3D> Rev2, + 3 =3D> Rev3, + 4 =3D> Rev4, + 5 =3D> Rev5, + 6 =3D> Rev6, + 7 =3D> Rev7, + _ =3D> return Err(EINVAL), + }; + + Ok(rev) + } +} + +/// Revision subversion number of a falcon core, used in the +/// [`crate::regs::NV_PFALCON_FALCON_HWCFG1`] register. +#[repr(u8)] +#[derive(Debug, Default, Copy, Clone, PartialEq, Eq, PartialOrd, Ord)] +pub(crate) enum FalconCoreRevSubversion { + #[default] + Subversion0 =3D 0, + Subversion1 =3D 1, + Subversion2 =3D 2, + Subversion3 =3D 3, +} + +impl TryFrom for FalconCoreRevSubversion { + type Error =3D Error; + + fn try_from(value: u8) -> Result { + use FalconCoreRevSubversion::*; + + let sub_version =3D match value & 0b11 { + 0 =3D> Subversion0, + 1 =3D> Subversion1, + 2 =3D> Subversion2, + 3 =3D> Subversion3, + _ =3D> return Err(EINVAL), + }; + + Ok(sub_version) + } +} + +/// Security model of a falcon core, used in the [`crate::regs::NV_PFALCON= _FALCON_HWCFG1`] +/// register. +#[repr(u8)] +#[derive(Debug, Default, Copy, Clone)] +pub(crate) enum FalconSecurityModel { + /// Non-Secure: runs unsigned code without privileges. + #[default] + None =3D 0, + /// Low-Secure: runs code with some privileges. Can only be entered fr= om `Heavy` mode, which + /// will typically validate the LS code through some signature. + Light =3D 2, + /// High-Secure: runs signed code with full privileges. Signature is v= alidated by boot ROM. + Heavy =3D 3, +} + +impl TryFrom for FalconSecurityModel { + type Error =3D Error; + + fn try_from(value: u8) -> Result { + use FalconSecurityModel::*; + + let sec_model =3D match value { + 0 =3D> None, + 2 =3D> Light, + 3 =3D> Heavy, + _ =3D> return Err(EINVAL), + }; + + Ok(sec_model) + } +} + +/// Signing algorithm for a given firmware, used in the [`crate::regs::NV_= PFALCON2_FALCON_MOD_SEL`] +/// register. +#[repr(u8)] +#[derive(Debug, Default, Copy, Clone, PartialEq, Eq)] +pub(crate) enum FalconModSelAlgo { + /// RSA3K. + #[default] + Rsa3k =3D 1, +} + +impl TryFrom for FalconModSelAlgo { + type Error =3D Error; + + fn try_from(value: u8) -> Result { + match value { + 1 =3D> Ok(FalconModSelAlgo::Rsa3k), + _ =3D> Err(EINVAL), + } + } +} + +/// Valid values for the `size` field of the [`crate::regs::NV_PFALCON_FAL= CON_DMATRFCMD`] register. +#[repr(u8)] +#[derive(Debug, Default, Copy, Clone, PartialEq, Eq)] +pub(crate) enum DmaTrfCmdSize { + /// 256 bytes transfer. + #[default] + Size256B =3D 0x6, +} + +impl TryFrom for DmaTrfCmdSize { + type Error =3D Error; + + fn try_from(value: u8) -> Result { + match value { + 0x6 =3D> Ok(Self::Size256B), + _ =3D> Err(EINVAL), + } + } +} + +/// Currently active core on a dual falcon/riscv (Peregrine) controller. +#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)] +pub(crate) enum PeregrineCoreSelect { + /// Falcon core is active. + #[default] + Falcon =3D 0, + /// RISC-V core is active. + Riscv =3D 1, +} + +impl From for PeregrineCoreSelect { + fn from(value: bool) -> Self { + match value { + false =3D> PeregrineCoreSelect::Falcon, + true =3D> PeregrineCoreSelect::Riscv, + } + } +} + +/// Different types of memory present in a falcon core. +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub(crate) enum FalconMem { + /// Instruction Memory. + Imem, + /// Data Memory. + Dmem, +} + +/// Target/source of a DMA transfer to/from falcon memory. +#[derive(Debug, Clone, Default)] +pub(crate) enum FalconFbifTarget { + /// VRAM. + #[default] + LocalFb =3D 0, + /// Coherent system memory. + CoherentSysmem =3D 1, + /// Non-coherent system memory. + NoncoherentSysmem =3D 2, +} + +impl TryFrom for FalconFbifTarget { + type Error =3D Error; + + fn try_from(value: u8) -> Result { + let res =3D match value { + 0 =3D> Self::LocalFb, + 1 =3D> Self::CoherentSysmem, + 2 =3D> Self::NoncoherentSysmem, + _ =3D> return Err(EINVAL), + }; + + Ok(res) + } +} + +/// Type of memory addresses to use. +#[derive(Debug, Clone, Default)] +pub(crate) enum FalconFbifMemType { + /// Virtual memory addresses. + #[default] + Virtual =3D 0, + /// Physical memory addresses. + Physical =3D 1, +} + +/// Conversion from a single-bit register field. +impl From for FalconFbifMemType { + fn from(value: bool) -> Self { + match value { + false =3D> Self::Virtual, + true =3D> Self::Physical, + } + } +} + +/// Trait defining the parameters of a given Falcon instance. +pub(crate) trait FalconEngine: Sync { + /// Base I/O address for the falcon, relative from which its registers= are accessed. + const BASE: usize; +} + +/// Represents a portion of the firmware to be loaded into a particular me= mory (e.g. IMEM or DMEM). +#[derive(Debug)] +pub(crate) struct FalconLoadTarget { + /// Offset from the start of the source object to copy from. + pub(crate) src_start: u32, + /// Offset from the start of the destination memory to copy into. + pub(crate) dst_start: u32, + /// Number of bytes to copy. + pub(crate) len: u32, +} + +/// Parameters for the falcon boot ROM. +#[derive(Debug)] +pub(crate) struct FalconBromParams { + /// Offset in `DMEM`` of the firmware's signature. + pub(crate) pkc_data_offset: u32, + /// Mask of engines valid for this firmware. + pub(crate) engine_id_mask: u16, + /// ID of the ucode used to infer a fuse register to validate the sign= ature. + pub(crate) ucode_id: u8, +} + +/// Trait for providing load parameters of falcon firmwares. +pub(crate) trait FalconLoadParams { + /// Returns the load parameters for `IMEM`. + fn imem_load_params(&self) -> FalconLoadTarget; + + /// Returns the load parameters for `DMEM`. + fn dmem_load_params(&self) -> FalconLoadTarget; + + /// Returns the parameters to write into the BROM registers. + fn brom_params(&self) -> FalconBromParams; + + /// Returns the start address of the firmware. + fn boot_addr(&self) -> u32; +} + +/// Trait for a falcon firmware. +/// +/// A falcon firmware can be loaded on a given engine, and is presented in= the form of a DMA +/// object. +pub(crate) trait FalconFirmware: FalconLoadParams + Deref { + /// Engine on which this firmware is to be loaded. + type Target: FalconEngine; +} + +/// Contains the base parameters common to all Falcon instances. +pub(crate) struct Falcon { + hal: KBox>, + dev: ARef, +} + +impl Falcon { + /// Create a new falcon instance. + /// + /// `need_riscv` is set to `true` if the caller expects the falcon to = be a dual falcon/riscv + /// controller. + pub(crate) fn new( + dev: &device::Device, + chipset: Chipset, + bar: &Bar0, + need_riscv: bool, + ) -> Result { + let hwcfg1 =3D regs::NV_PFALCON_FALCON_HWCFG1::read(bar, E::BASE); + // Check that the revision and security model contain valid values. + let _ =3D hwcfg1.core_rev()?; + let _ =3D hwcfg1.security_model()?; + + if need_riscv { + let hwcfg2 =3D regs::NV_PFALCON_FALCON_HWCFG2::read(bar, E::BA= SE); + if !hwcfg2.riscv() { + dev_err!( + dev, + "riscv support requested on a controller that does not= support it\n" + ); + return Err(EINVAL); + } + } + + Ok(Self { + hal: hal::falcon_hal(chipset)?, + dev: dev.into(), + }) + } + + /// Wait for memory scrubbing to complete. + fn reset_wait_mem_scrubbing(&self, bar: &Bar0) -> Result { + // TIMEOUT: memory scrubbing should complete in less than 20ms. + util::wait_on(Duration::from_millis(20), || { + if regs::NV_PFALCON_FALCON_HWCFG2::read(bar, E::BASE).mem_scru= bbing_done() { + Some(()) + } else { + None + } + }) + } + + /// Reset the falcon engine. + fn reset_eng(&self, bar: &Bar0) -> Result { + let _ =3D regs::NV_PFALCON_FALCON_HWCFG2::read(bar, E::BASE); + + // According to OpenRM's `kflcnPreResetWait_GA102` documentation, = HW sometimes does not set + // RESET_READY so a non-failing timeout is used. + let _ =3D util::wait_on(Duration::from_micros(150), || { + let r =3D regs::NV_PFALCON_FALCON_HWCFG2::read(bar, E::BASE); + if r.reset_ready() { + Some(()) + } else { + None + } + }); + + regs::NV_PFALCON_FALCON_ENGINE::alter(bar, E::BASE, |v| v.set_rese= t(true)); + + // TODO: replace with udelay() or equivalent once available. + // TIMEOUT: falcon engine should not take more than 10us to reset. + let _: Result =3D util::wait_on(Duration::from_micros(10), || None= ); + + regs::NV_PFALCON_FALCON_ENGINE::alter(bar, E::BASE, |v| v.set_rese= t(false)); + + self.reset_wait_mem_scrubbing(bar)?; + + Ok(()) + } + + /// Reset the controller, select the falcon core, and wait for memory = scrubbing to complete. + pub(crate) fn reset(&self, bar: &Bar0) -> Result { + self.reset_eng(bar)?; + self.hal.select_core(self, bar)?; + self.reset_wait_mem_scrubbing(bar)?; + + regs::NV_PFALCON_FALCON_RM::default() + .set_value(regs::NV_PMC_BOOT_0::read(bar).into()) + .write(bar, E::BASE); + + Ok(()) + } + + /// Perform a DMA write according to `load_offsets` from `dma_handle` = into the falcon's + /// `target_mem`. + /// + /// `sec` is set if the loaded firmware is expected to run in secure m= ode. + fn dma_wr>( + &self, + bar: &Bar0, + fw: &F, + target_mem: FalconMem, + load_offsets: FalconLoadTarget, + sec: bool, + ) -> Result { + const DMA_LEN: u32 =3D 256; + + // For IMEM, we want to use the start offset as a virtual address = tag for each page, since + // code addresses in the firmware (and the boot vector) are virtua= l. + // + // For DMEM we can fold the start offset into the DMA handle. + let (src_start, dma_start) =3D match target_mem { + FalconMem::Imem =3D> (load_offsets.src_start, fw.dma_handle()), + FalconMem::Dmem =3D> ( + 0, + fw.dma_handle_with_offset(load_offsets.src_start as usize)= ?, + ), + }; + if dma_start % DMA_LEN as bindings::dma_addr_t > 0 { + dev_err!( + self.dev, + "DMA transfer start addresses must be a multiple of {}", + DMA_LEN + ); + return Err(EINVAL); + } + if load_offsets.len % DMA_LEN > 0 { + dev_err!( + self.dev, + "DMA transfer length must be a multiple of {}", + DMA_LEN + ); + return Err(EINVAL); + } + + // Set up the base source DMA address. + + regs::NV_PFALCON_FALCON_DMATRFBASE::default() + .set_base((dma_start >> 8) as u32) + .write(bar, E::BASE); + regs::NV_PFALCON_FALCON_DMATRFBASE1::default() + .set_base((dma_start >> 40) as u16) + .write(bar, E::BASE); + + let cmd =3D regs::NV_PFALCON_FALCON_DMATRFCMD::default() + .set_size(DmaTrfCmdSize::Size256B) + .set_imem(target_mem =3D=3D FalconMem::Imem) + .set_sec(if sec { 1 } else { 0 }); + + for pos in (0..load_offsets.len).step_by(DMA_LEN as usize) { + // Perform a transfer of size `DMA_LEN`. + regs::NV_PFALCON_FALCON_DMATRFMOFFS::default() + .set_offs(load_offsets.dst_start + pos) + .write(bar, E::BASE); + regs::NV_PFALCON_FALCON_DMATRFFBOFFS::default() + .set_offs(src_start + pos) + .write(bar, E::BASE); + cmd.write(bar, E::BASE); + + // Wait for the transfer to complete. + // TIMEOUT: arbitrarily large value, no DMA transfer to the fa= lcon's small memories + // should ever take that long. + util::wait_on(Duration::from_secs(2), || { + let r =3D regs::NV_PFALCON_FALCON_DMATRFCMD::read(bar, E::= BASE); + if r.idle() { + Some(()) + } else { + None + } + })?; + } + + Ok(()) + } + + /// Perform a DMA load into `IMEM` and `DMEM` of `fw`, and prepare the= falcon to run it. + pub(crate) fn dma_load>(&self, bar: &B= ar0, fw: &F) -> Result { + regs::NV_PFALCON_FBIF_CTL::alter(bar, E::BASE, |v| v.set_allow_phy= s_no_ctx(true)); + regs::NV_PFALCON_FALCON_DMACTL::default().write(bar, E::BASE); + regs::NV_PFALCON_FBIF_TRANSCFG::alter(bar, E::BASE, |v| { + v.set_target(FalconFbifTarget::CoherentSysmem) + .set_mem_type(FalconFbifMemType::Physical) + }); + + self.dma_wr(bar, fw, FalconMem::Imem, fw.imem_load_params(), true)= ?; + self.dma_wr(bar, fw, FalconMem::Dmem, fw.dmem_load_params(), true)= ?; + + self.hal.program_brom(self, bar, &fw.brom_params())?; + + // Set `BootVec` to start of non-secure code. + regs::NV_PFALCON_FALCON_BOOTVEC::default() + .set_value(fw.boot_addr()) + .write(bar, E::BASE); + + Ok(()) + } + + /// Runs the loaded firmware and waits for its completion. + /// + /// `mbox0` and `mbox1` are optional parameters to write into the `MBO= X0` and `MBOX1` registers + /// prior to running. + /// + /// Wait up to two seconds for the firmware to complete, and return it= s exit status read from + /// the `MBOX0` and `MBOX1` registers. + pub(crate) fn boot( + &self, + bar: &Bar0, + mbox0: Option, + mbox1: Option, + ) -> Result<(u32, u32)> { + if let Some(mbox0) =3D mbox0 { + regs::NV_PFALCON_FALCON_MAILBOX0::default() + .set_value(mbox0) + .write(bar, E::BASE); + } + + if let Some(mbox1) =3D mbox1 { + regs::NV_PFALCON_FALCON_MAILBOX1::default() + .set_value(mbox1) + .write(bar, E::BASE); + } + + match regs::NV_PFALCON_FALCON_CPUCTL::read(bar, E::BASE).alias_en(= ) { + true =3D> regs::NV_PFALCON_FALCON_CPUCTL_ALIAS::default() + .set_startcpu(true) + .write(bar, E::BASE), + false =3D> regs::NV_PFALCON_FALCON_CPUCTL::default() + .set_startcpu(true) + .write(bar, E::BASE), + } + + // TIMEOUT: arbitrarily large value, firmwares should complete in = less than 2 seconds. + util::wait_on(Duration::from_secs(2), || { + let r =3D regs::NV_PFALCON_FALCON_CPUCTL::read(bar, E::BASE); + if r.halted() { + Some(()) + } else { + None + } + })?; + + let (mbox0, mbox1) =3D ( + regs::NV_PFALCON_FALCON_MAILBOX0::read(bar, E::BASE).value(), + regs::NV_PFALCON_FALCON_MAILBOX1::read(bar, E::BASE).value(), + ); + + Ok((mbox0, mbox1)) + } + + /// Returns the fused version of the signature to use in order to run = a HS firmware on this + /// falcon instance. `engine_id_mask` and `ucode_id` are obtained from= the firmware header. + pub(crate) fn signature_reg_fuse_version( + &self, + bar: &Bar0, + engine_id_mask: u16, + ucode_id: u8, + ) -> Result { + self.hal + .signature_reg_fuse_version(self, bar, engine_id_mask, ucode_i= d) + } +} diff --git a/drivers/gpu/nova-core/falcon/gsp.rs b/drivers/gpu/nova-core/fa= lcon/gsp.rs new file mode 100644 index 0000000000000000000000000000000000000000..d622e9a64470932af0b48032be5= a1d4b518bf4a7 --- /dev/null +++ b/drivers/gpu/nova-core/falcon/gsp.rs @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 + +use crate::{ + driver::Bar0, + falcon::{Falcon, FalconEngine}, + regs, +}; + +/// Type specifying the `Gsp` falcon engine. Cannot be instantiated. +pub(crate) struct Gsp(()); + +impl FalconEngine for Gsp { + const BASE: usize =3D 0x00110000; +} + +impl Falcon { + /// Clears the SWGEN0 bit in the Falcon's IRQ status clear register to + /// allow GSP to signal CPU for processing new messages in message que= ue. + pub(crate) fn clear_swgen0_intr(&self, bar: &Bar0) { + regs::NV_PFALCON_FALCON_IRQSCLR::default() + .set_swgen0(true) + .write(bar, Gsp::BASE); + } +} diff --git a/drivers/gpu/nova-core/falcon/hal.rs b/drivers/gpu/nova-core/fa= lcon/hal.rs new file mode 100644 index 0000000000000000000000000000000000000000..b233bc365882f9add9b6eab33b8= d462d7913df37 --- /dev/null +++ b/drivers/gpu/nova-core/falcon/hal.rs @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 + +use kernel::prelude::*; + +use crate::driver::Bar0; +use crate::falcon::{Falcon, FalconBromParams, FalconEngine}; +use crate::gpu::Chipset; + +mod ga102; + +/// Hardware Abstraction Layer for Falcon cores. +/// +/// Implements chipset-specific low-level operations. The trait is generic= against [`FalconEngine`] +/// so its `BASE` parameter can be used in order to avoid runtime bound ch= ecks when accessing +/// registers. +pub(crate) trait FalconHal: Sync { + /// Activates the Falcon core if the engine is a risvc/falcon dual eng= ine. + fn select_core(&self, _falcon: &Falcon, _bar: &Bar0) -> Result { + Ok(()) + } + + /// Returns the fused version of the signature to use in order to run = a HS firmware on this + /// falcon instance. `engine_id_mask` and `ucode_id` are obtained from= the firmware header. + fn signature_reg_fuse_version( + &self, + falcon: &Falcon, + bar: &Bar0, + engine_id_mask: u16, + ucode_id: u8, + ) -> Result; + + /// Program the boot ROM registers prior to starting a secure firmware. + fn program_brom(&self, falcon: &Falcon, bar: &Bar0, params: &Falcon= BromParams) -> Result; +} + +/// Returns a boxed falcon HAL adequate for `chipset`. +/// +/// We use a heap-allocated trait object instead of a statically defined o= ne because the +/// generic `FalconEngine` argument makes it difficult to define all the c= ombinations +/// statically. +pub(super) fn falcon_hal( + chipset: Chipset, +) -> Result>> { + use Chipset::*; + + let hal =3D match chipset { + GA102 | GA103 | GA104 | GA106 | GA107 =3D> { + KBox::new(ga102::Ga102::::new(), GFP_KERNEL)? as KBox> + } + _ =3D> return Err(ENOTSUPP), + }; + + Ok(hal) +} diff --git a/drivers/gpu/nova-core/falcon/hal/ga102.rs b/drivers/gpu/nova-c= ore/falcon/hal/ga102.rs new file mode 100644 index 0000000000000000000000000000000000000000..0a4e5e7adf8cbcec9f67bb09ba7= 58a9cb2887bae --- /dev/null +++ b/drivers/gpu/nova-core/falcon/hal/ga102.rs @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0 + +use core::marker::PhantomData; +use core::time::Duration; + +use kernel::device; +use kernel::prelude::*; + +use crate::driver::Bar0; +use crate::falcon::{ + Falcon, FalconBromParams, FalconEngine, FalconModSelAlgo, PeregrineCor= eSelect, +}; +use crate::regs; +use crate::util; + +use super::FalconHal; + +fn select_core_ga102(bar: &Bar0) -> Result { + let bcr_ctrl =3D regs::NV_PRISCV_RISCV_BCR_CTRL::read(bar, E::BASE); + if bcr_ctrl.core_select() !=3D PeregrineCoreSelect::Falcon { + regs::NV_PRISCV_RISCV_BCR_CTRL::default() + .set_core_select(PeregrineCoreSelect::Falcon) + .write(bar, E::BASE); + + // TIMEOUT: falcon core should take less than 10ms to report being= enabled. + util::wait_on(Duration::from_millis(10), || { + let r =3D regs::NV_PRISCV_RISCV_BCR_CTRL::read(bar, E::BASE); + if r.valid() { + Some(()) + } else { + None + } + })?; + } + + Ok(()) +} + +fn signature_reg_fuse_version_ga102( + dev: &device::Device, + bar: &Bar0, + engine_id_mask: u16, + ucode_id: u8, +) -> Result { + // TODO: The ucode fuse versions are contained in the FUSE_OPT_FPF__UCODE_VERSION + // registers, which are an array. Our register definition macros do no= t allow us to manage them + // properly, so we need to hardcode their addresses for now. Clean thi= s up once we support + // register arrays. + + // Each engine has 16 ucode version registers numbered from 1 to 16. + if ucode_id =3D=3D 0 || ucode_id > 16 { + dev_err!(dev, "invalid ucode id {:#x}", ucode_id); + return Err(EINVAL); + } + + // Base address of the FUSE registers array corresponding to the engin= e. + let reg_fuse_base =3D if engine_id_mask & 0x0001 !=3D 0 { + regs::NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION::OFFSET + } else if engine_id_mask & 0x0004 !=3D 0 { + regs::NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION::OFFSET + } else if engine_id_mask & 0x0400 !=3D 0 { + regs::NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION::OFFSET + } else { + dev_err!(dev, "unexpected engine_id_mask {:#x}", engine_id_mask); + return Err(EINVAL); + }; + + // Read `reg_fuse_base[ucode_id - 1]`. + let reg_fuse_version =3D + bar.read32(reg_fuse_base + ((ucode_id - 1) as usize * core::mem::s= ize_of::())); + + // TODO: replace with `last_set_bit` once it lands. + Ok(u32::BITS - reg_fuse_version.leading_zeros()) +} + +fn program_brom_ga102(bar: &Bar0, params: &FalconBromPara= ms) -> Result { + regs::NV_PFALCON2_FALCON_BROM_PARAADDR::default() + .set_value(params.pkc_data_offset) + .write(bar, E::BASE); + regs::NV_PFALCON2_FALCON_BROM_ENGIDMASK::default() + .set_value(params.engine_id_mask as u32) + .write(bar, E::BASE); + regs::NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID::default() + .set_ucode_id(params.ucode_id) + .write(bar, E::BASE); + regs::NV_PFALCON2_FALCON_MOD_SEL::default() + .set_algo(FalconModSelAlgo::Rsa3k) + .write(bar, E::BASE); + + Ok(()) +} + +pub(super) struct Ga102(PhantomData); + +impl Ga102 { + pub(super) fn new() -> Self { + Self(PhantomData) + } +} + +impl FalconHal for Ga102 { + fn select_core(&self, _falcon: &Falcon, bar: &Bar0) -> Result { + select_core_ga102::(bar) + } + + fn signature_reg_fuse_version( + &self, + falcon: &Falcon, + bar: &Bar0, + engine_id_mask: u16, + ucode_id: u8, + ) -> Result { + signature_reg_fuse_version_ga102(&falcon.dev, bar, engine_id_mask,= ucode_id) + } + + fn program_brom(&self, _falcon: &Falcon, bar: &Bar0, params: &Falco= nBromParams) -> Result { + program_brom_ga102::(bar, params) + } +} diff --git a/drivers/gpu/nova-core/falcon/sec2.rs b/drivers/gpu/nova-core/f= alcon/sec2.rs new file mode 100644 index 0000000000000000000000000000000000000000..5147d9e2a7fe859210727504688= d84cca4de991b --- /dev/null +++ b/drivers/gpu/nova-core/falcon/sec2.rs @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 + +use crate::falcon::FalconEngine; + +/// Type specifying the `Sec2` falcon engine. Cannot be instantiated. +pub(crate) struct Sec2(()); + +impl FalconEngine for Sec2 { + const BASE: usize =3D 0x00840000; +} diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 768579dfdfc7e9e61c613202030d2c7ee6054e2a..c9f7f604a5de6ea4eb85f061cae= 826302c1902c3 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -3,6 +3,7 @@ use kernel::{device, devres::Devres, error::code::*, pci, prelude::*}; =20 use crate::driver::Bar0; +use crate::falcon::{gsp::Gsp, sec2::Sec2, Falcon}; use crate::fb::SysmemFlush; use crate::firmware::{Firmware, FIRMWARE_VERSION}; use crate::gfw; @@ -207,6 +208,16 @@ pub(crate) fn new( // System memory page required for sysmembar to properly flush int= o system memory. let sysmem_flush =3D SysmemFlush::register(pdev.as_ref(), bar, spe= c.chipset)?; =20 + let gsp_falcon =3D Falcon::::new( + pdev.as_ref(), + spec.chipset, + bar, + spec.chipset > Chipset::GA100, + )?; + gsp_falcon.clear_swgen0_intr(bar); + + let _sec2_falcon =3D Falcon::::new(pdev.as_ref(), spec.chips= et, bar, true)?; + Ok(pin_init!(Self { spec, bar: devres_bar, diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nov= a_core.rs index 8ac04b8586e7314528e081464ed73ee615001e9b..808997bbe36d2fa1dc8b8940c1f= 9373d9bdbfb69 100644 --- a/drivers/gpu/nova-core/nova_core.rs +++ b/drivers/gpu/nova-core/nova_core.rs @@ -4,6 +4,7 @@ =20 mod dma; mod driver; +mod falcon; mod fb; mod firmware; mod gfw; diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index b599e7ddad57ed8defe0324056571ba46b926cf6..a2f449eb08b5691aaa6f2f0e763= 5791838996806 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -7,6 +7,10 @@ #[macro_use] mod macros; =20 +use crate::falcon::{ + DmaTrfCmdSize, FalconCoreRev, FalconCoreRevSubversion, FalconFbifMemTy= pe, FalconFbifTarget, + FalconModSelAlgo, FalconSecurityModel, PeregrineCoreSelect, +}; use crate::gpu::{Architecture, Chipset}; use kernel::prelude::*; =20 @@ -72,3 +76,145 @@ pub(crate) fn completed(self) -> bool { self.progress() =3D=3D 0xff } } + +/* FUSE */ + +register!(NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION @ 0x00824100 { + 15:0 data as u16; +}); + +register!(NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION @ 0x00824140 { + 15:0 data as u16; +}); + +register!(NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION @ 0x008241c0 { + 15:0 data as u16; +}); + +/* PFALCON */ + +register!(NV_PFALCON_FALCON_IRQSCLR @ +0x00000004 { + 4:4 halt as bool; + 6:6 swgen0 as bool; +}); + +register!(NV_PFALCON_FALCON_MAILBOX0 @ +0x00000040 { + 31:0 value as u32; +}); + +register!(NV_PFALCON_FALCON_MAILBOX1 @ +0x00000044 { + 31:0 value as u32; +}); + +register!(NV_PFALCON_FALCON_RM @ +0x00000084 { + 31:0 value as u32; +}); + +register!(NV_PFALCON_FALCON_HWCFG2 @ +0x000000f4 { + 10:10 riscv as bool; + 12:12 mem_scrubbing as bool, "Set to 0 after memory scrubbing is com= pleted"; + 31:31 reset_ready as bool, "Signal indicating that reset is complete= d (GA102+)"; +}); + +impl NV_PFALCON_FALCON_HWCFG2 { + /// Returns `true` if memory scrubbing is completed. + pub(crate) fn mem_scrubbing_done(self) -> bool { + !self.mem_scrubbing() + } +} + +register!(NV_PFALCON_FALCON_CPUCTL @ +0x00000100 { + 1:1 startcpu as bool; + 4:4 halted as bool; + 6:6 alias_en as bool; +}); + +register!(NV_PFALCON_FALCON_BOOTVEC @ +0x00000104 { + 31:0 value as u32; +}); + +register!(NV_PFALCON_FALCON_DMACTL @ +0x0000010c { + 0:0 require_ctx as bool; + 1:1 dmem_scrubbing as bool; + 2:2 imem_scrubbing as bool; + 6:3 dmaq_num as u8; + 7:7 secure_stat as bool; +}); + +register!(NV_PFALCON_FALCON_DMATRFBASE @ +0x00000110 { + 31:0 base as u32; +}); + +register!(NV_PFALCON_FALCON_DMATRFMOFFS @ +0x00000114 { + 23:0 offs as u32; +}); + +register!(NV_PFALCON_FALCON_DMATRFCMD @ +0x00000118 { + 0:0 full as bool; + 1:1 idle as bool; + 3:2 sec as u8; + 4:4 imem as bool; + 5:5 is_write as bool; + 10:8 size as u8 ?=3D> DmaTrfCmdSize; + 14:12 ctxdma as u8; + 16:16 set_dmtag as u8; +}); + +register!(NV_PFALCON_FALCON_DMATRFFBOFFS @ +0x0000011c { + 31:0 offs as u32; +}); + +register!(NV_PFALCON_FALCON_DMATRFBASE1 @ +0x00000128 { + 8:0 base as u16; +}); + +register!(NV_PFALCON_FALCON_HWCFG1 @ +0x0000012c { + 3:0 core_rev as u8 ?=3D> FalconCoreRev, "Core revision"; + 5:4 security_model as u8 ?=3D> FalconSecurityModel, "Security mode= l"; + 7:6 core_rev_subversion as u8 ?=3D> FalconCoreRevSubversion, "Core= revision subversion"; +}); + +register!(NV_PFALCON_FALCON_CPUCTL_ALIAS @ +0x00000130 { + 1:1 startcpu as bool; +}); + +// Actually known as `NV_PSEC_FALCON_ENGINE` and `NV_PGSP_FALCON_ENGINE` d= epending on the falcon +// instance. +register!(NV_PFALCON_FALCON_ENGINE @ +0x000003c0 { + 0:0 reset as bool; +}); + +// TODO: this is an array of registers. +register!(NV_PFALCON_FBIF_TRANSCFG @ +0x00000600 { + 1:0 target as u8 ?=3D> FalconFbifTarget; + 2:2 mem_type as bool =3D> FalconFbifMemType; +}); + +register!(NV_PFALCON_FBIF_CTL @ +0x00000624 { + 7:7 allow_phys_no_ctx as bool; +}); + +register!(NV_PFALCON2_FALCON_MOD_SEL @ +0x00001180 { + 7:0 algo as u8 ?=3D> FalconModSelAlgo; +}); + +register!(NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID @ +0x00001198 { + 7:0 ucode_id as u8; +}); + +register!(NV_PFALCON2_FALCON_BROM_ENGIDMASK @ +0x0000119c { + 31:0 value as u32; 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Introduce the structure that describes it. Reviewed-by: Lyude Paul Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/firmware.rs | 45 +++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 45 insertions(+) diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index 4b8a38358a4f6da2a4d57f8db50ea9e788c3e4b5..2f4f5c7c7902a386a44bc9cf5eb= 6d46375fe0e5a 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -41,6 +41,51 @@ pub(crate) fn new(dev: &device::Device, chipset: Chipset= , ver: &str) -> Result usize { + const HDR_SIZE_SHIFT: u32 =3D 16; + const HDR_SIZE_MASK: u32 =3D 0xffff0000; + + ((self.hdr & HDR_SIZE_MASK) >> HDR_SIZE_SHIFT) as usize + } +} + pub(crate) struct ModInfoBuilder(firmware::ModInfoBuilder<= N>); =20 impl ModInfoBuilder { --=20 2.49.0 From nobody Fri Dec 19 02:53:47 2025 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2063.outbound.protection.outlook.com [40.107.92.63]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 357C72701BA; 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Later patches will build on this. Debug log messages will show the BIOS images: [102141.013287] NovaCore: Found BIOS image at offset 0x0, size: 0xfe00, typ= e: PciAt [102141.080692] NovaCore: Found BIOS image at offset 0xfe00, size: 0x14800,= type: Efi [102141.098443] NovaCore: Found BIOS image at offset 0x24600, size: 0x5600,= type: FwSec [102141.415095] NovaCore: Found BIOS image at offset 0x29c00, size: 0x60800= , type: FwSec [applied feedback from Alex Courbot and Timur Tabi] [applied changes related to code reorg, prints etc from Danilo Krummrich] [acourbot@nvidia.com: fix clippy warnings, read_more() function] Cc: Alexandre Courbot Cc: John Hubbard Cc: Shirish Baskaran Cc: Alistair Popple Cc: Timur Tabi Cc: Ben Skeggs Signed-off-by: Alexandre Courbot Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/firmware.rs | 4 +- drivers/gpu/nova-core/gpu.rs | 4 + drivers/gpu/nova-core/nova_core.rs | 1 + drivers/gpu/nova-core/vbios.rs | 681 +++++++++++++++++++++++++++++++++= ++++ 4 files changed, 688 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index 2f4f5c7c7902a386a44bc9cf5eb6d46375fe0e5a..41f43a729ad3bf2c4acb6108f41= e0905a6fac0df 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -44,6 +44,7 @@ pub(crate) fn new(dev: &device::Device, chipset: Chipset,= ver: &str) -> Result usize { const HDR_SIZE_SHIFT: u32 =3D 16; const HDR_SIZE_MASK: u32 =3D 0xffff0000; diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index c9f7f604a5de6ea4eb85f061cae826302c1902c3..1c577d3eff8b32bbc45d7d2302c= 3e2246bef3b44 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -9,6 +9,7 @@ use crate::gfw; use crate::regs; use crate::util; +use crate::vbios::Vbios; use core::fmt; =20 macro_rules! define_chipset { @@ -218,6 +219,9 @@ pub(crate) fn new( =20 let _sec2_falcon =3D Falcon::::new(pdev.as_ref(), spec.chips= et, bar, true)?; =20 + // Will be used in a later patch when fwsec firmware is needed. + let _bios =3D Vbios::new(pdev, bar)?; + Ok(pin_init!(Self { spec, bar: devres_bar, diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nov= a_core.rs index 808997bbe36d2fa1dc8b8940c1f9373d9bdbfb69..de14f2e926361a4f954b1a8d0b9= 5b0e985e54eec 100644 --- a/drivers/gpu/nova-core/nova_core.rs +++ b/drivers/gpu/nova-core/nova_core.rs @@ -11,6 +11,7 @@ mod gpu; mod regs; mod util; +mod vbios; =20 pub(crate) const MODULE_NAME: &kernel::str::CStr =3D ::NAME; =20 diff --git a/drivers/gpu/nova-core/vbios.rs b/drivers/gpu/nova-core/vbios.rs new file mode 100644 index 0000000000000000000000000000000000000000..b9879590ae3aae6517683a6ed02= f7f639055598e --- /dev/null +++ b/drivers/gpu/nova-core/vbios.rs @@ -0,0 +1,681 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! VBIOS extraction and parsing. + +// To be removed when all code is used. +#![expect(dead_code)] + +use crate::driver::Bar0; +use core::convert::TryFrom; +use kernel::error::Result; +use kernel::pci; +use kernel::prelude::*; + +/// The offset of the VBIOS ROM in the BAR0 space. +const ROM_OFFSET: usize =3D 0x300000; +/// The maximum length of the VBIOS ROM to scan into. +const BIOS_MAX_SCAN_LEN: usize =3D 0x100000; +/// The size to read ahead when parsing initial BIOS image headers. +const BIOS_READ_AHEAD_SIZE: usize =3D 1024; +/// The bit in the last image indicator byte for the PCI Data Structure th= at +/// indicates the last image. Bit 0-6 are reserved, bit 7 is last image bi= t. +const LAST_IMAGE_BIT_MASK: u8 =3D 0x80; + +// PMU lookup table entry types. Used to locate PMU table entries +// in the Fwsec image, corresponding to falcon ucodes. +#[expect(dead_code)] +const FALCON_UCODE_ENTRY_APPID_FIRMWARE_SEC_LIC: u8 =3D 0x05; +#[expect(dead_code)] +const FALCON_UCODE_ENTRY_APPID_FWSEC_DBG: u8 =3D 0x45; +const FALCON_UCODE_ENTRY_APPID_FWSEC_PROD: u8 =3D 0x85; + +/// Vbios Reader for constructing the VBIOS data +struct VbiosIterator<'a> { + pdev: &'a pci::Device, + bar0: &'a Bar0, + // VBIOS data vector: As BIOS images are scanned, they are added to th= is vector + // for reference or copying into other data structures. It is the enti= re + // scanned contents of the VBIOS which progressively extends. It is us= ed + // so that we do not re-read any contents that are already read as we = use + // the cumulative length read so far, and re-read any gaps as we extend + // the length. + data: KVec, + current_offset: usize, // Current offset for iterator + last_found: bool, // Whether the last image has been found +} + +impl<'a> VbiosIterator<'a> { + fn new(pdev: &'a pci::Device, bar0: &'a Bar0) -> Result { + Ok(Self { + pdev, + bar0, + data: KVec::new(), + current_offset: 0, + last_found: false, + }) + } + + /// Read bytes from the ROM at the current end of the data vector + fn read_more(&mut self, len: usize) -> Result { + let current_len =3D self.data.len(); + let start =3D ROM_OFFSET + current_len; + + // Ensure length is a multiple of 4 for 32-bit reads + if len % core::mem::size_of::() !=3D 0 { + dev_err!( + self.pdev.as_ref(), + "VBIOS read length {} is not a multiple of 4\n", + len + ); + return Err(EINVAL); + } + + self.data.reserve(len, GFP_KERNEL)?; + // Read ROM data bytes and push directly to vector + for addr in (start..start + len).step_by(core::mem::size_of::= ()) { + // Read 32-bit word from the VBIOS ROM + let word =3D self.bar0.try_read32(addr)?; + + // Convert the u32 to a 4 byte array and push each byte + word.to_ne_bytes() + .iter() + .try_for_each(|&b| self.data.push(b, GFP_KERNEL))?; + } + + Ok(()) + } + + /// Read bytes at a specific offset, filling any gap + fn read_more_at_offset(&mut self, offset: usize, len: usize) -> Result= { + if offset > BIOS_MAX_SCAN_LEN { + dev_err!(self.pdev.as_ref(), "Error: exceeded BIOS scan limit.= \n"); + return Err(EINVAL); + } + + // If offset is beyond current data size, fill the gap first + let current_len =3D self.data.len(); + let gap_bytes =3D offset.saturating_sub(current_len); + + // Now read the requested bytes at the offset + self.read_more(gap_bytes + len) + } + + /// Read a BIOS image at a specific offset and create a BiosImage from= it. + /// self.data is extended as needed and a new BiosImage is returned. + /// @context is a string describing the operation for error reporting + fn read_bios_image_at_offset( + &mut self, + offset: usize, + len: usize, + context: &str, + ) -> Result { + let data_len =3D self.data.len(); + if offset + len > data_len { + self.read_more_at_offset(offset, len).inspect_err(|e| { + dev_err!( + self.pdev.as_ref(), + "Failed to read more at offset {:#x}: {:?}\n", + offset, + e + ) + })?; + } + + BiosImage::new(self.pdev, &self.data[offset..offset + len]).inspec= t_err(|err| { + dev_err!( + self.pdev.as_ref(), + "Failed to {} at offset {:#x}: {:?}\n", + context, + offset, + err + ) + }) + } +} + +impl<'a> Iterator for VbiosIterator<'a> { + type Item =3D Result; + + /// Iterate over all VBIOS images until the last image is detected or = offset + /// exceeds scan limit. + fn next(&mut self) -> Option { + if self.last_found { + return None; + } + + if self.current_offset > BIOS_MAX_SCAN_LEN { + dev_err!( + self.pdev.as_ref(), + "Error: exceeded BIOS scan limit, stopping scan\n" + ); + return None; + } + + // Parse image headers first to get image size + let image_size =3D match self.read_bios_image_at_offset( + self.current_offset, + BIOS_READ_AHEAD_SIZE, + "parse initial BIOS image headers", + ) { + Ok(image) =3D> image.image_size_bytes(), + Err(e) =3D> return Some(Err(e)), + }; + + // Now create a new BiosImage with the full image data + let full_image =3D match self.read_bios_image_at_offset( + self.current_offset, + image_size, + "parse full BIOS image", + ) { + Ok(image) =3D> image, + Err(e) =3D> return Some(Err(e)), + }; + + self.last_found =3D full_image.is_last(); + + // Advance to next image (aligned to 512 bytes) + self.current_offset +=3D image_size; + // TODO: replace with `align_up` once it lands. + self.current_offset =3D self.current_offset.next_multiple_of(512); + + Some(Ok(full_image)) + } +} + +pub(crate) struct Vbios { + fwsec_image: FwSecBiosImage, +} + +impl Vbios { + /// Probe for VBIOS extraction + /// Once the VBIOS object is built, bar0 is not read for vbios purpose= s anymore. + pub(crate) fn new(pdev: &pci::Device, bar0: &Bar0) -> Result { + // Images to extract from iteration + let mut pci_at_image: Option =3D None; + let mut first_fwsec_image: Option =3D None; + let mut second_fwsec_image: Option =3D None; + + // Parse all VBIOS images in the ROM + for image_result in VbiosIterator::new(pdev, bar0)? { + let full_image =3D image_result?; + + dev_dbg!( + pdev.as_ref(), + "Found BIOS image: size: {:#x}, type: {}, last: {}\n", + full_image.image_size_bytes(), + full_image.image_type_str(), + full_image.is_last() + ); + + // Get references to images we will need after the loop, in or= der to + // setup the falcon data offset. + match full_image { + BiosImage::PciAt(image) =3D> { + pci_at_image =3D Some(image); + } + BiosImage::FwSec(image) =3D> { + if first_fwsec_image.is_none() { + first_fwsec_image =3D Some(image); + } else { + second_fwsec_image =3D Some(image); + } + } + // For now we don't need to handle these + BiosImage::Efi(_image) =3D> {} + BiosImage::Nbsi(_image) =3D> {} + } + } + + // Using all the images, setup the falcon data pointer in Fwsec. + // These are temporarily unused images and will be used in later p= atches. + if let (Some(second), Some(_first), Some(_pci_at)) =3D + (second_fwsec_image, first_fwsec_image, pci_at_image) + { + Ok(Vbios { + fwsec_image: second, + }) + } else { + dev_err!( + pdev.as_ref(), + "Missing required images for falcon data setup, skipping\n" + ); + Err(EINVAL) + } + } +} + +/// PCI Data Structure as defined in PCI Firmware Specification +#[derive(Debug, Clone)] +#[repr(C)] +struct PcirStruct { + /// PCI Data Structure signature ("PCIR" or "NPDS") + signature: [u8; 4], + /// PCI Vendor ID (e.g., 0x10DE for NVIDIA) + vendor_id: u16, + /// PCI Device ID + device_id: u16, + /// Device List Pointer + device_list_ptr: u16, + /// PCI Data Structure Length + pci_data_struct_len: u16, + /// PCI Data Structure Revision + pci_data_struct_rev: u8, + /// Class code (3 bytes, 0x03 for display controller) + class_code: [u8; 3], + /// Size of this image in 512-byte blocks + image_len: u16, + /// Revision Level of the Vendor's ROM + vendor_rom_rev: u16, + /// ROM image type (0x00 =3D PC-AT compatible, 0x03 =3D EFI, 0x70 =3D = NBSI) + code_type: u8, + /// Last image indicator (0x00 =3D Not last image, 0x80 =3D Last image) + last_image: u8, + /// Maximum Run-time Image Length (units of 512 bytes) + max_runtime_image_len: u16, +} + +impl PcirStruct { + fn new(pdev: &pci::Device, data: &[u8]) -> Result { + if data.len() < core::mem::size_of::() { + dev_err!(pdev.as_ref(), "Not enough data for PcirStruct\n"); + return Err(EINVAL); + } + + let mut signature =3D [0u8; 4]; + signature.copy_from_slice(&data[0..4]); + + // Signature should be "PCIR" (0x52494350) or "NPDS" (0x5344504e) + if &signature !=3D b"PCIR" && &signature !=3D b"NPDS" { + dev_err!( + pdev.as_ref(), + "Invalid signature for PcirStruct: {:?}\n", + signature + ); + return Err(EINVAL); + } + + let mut class_code =3D [0u8; 3]; + class_code.copy_from_slice(&data[13..16]); + + let image_len =3D u16::from_le_bytes([data[16], data[17]]); + if image_len =3D=3D 0 { + dev_err!(pdev.as_ref(), "Invalid image length: 0\n"); + return Err(EINVAL); + } + + Ok(PcirStruct { + signature, + vendor_id: u16::from_le_bytes([data[4], data[5]]), + device_id: u16::from_le_bytes([data[6], data[7]]), + device_list_ptr: u16::from_le_bytes([data[8], data[9]]), + pci_data_struct_len: u16::from_le_bytes([data[10], data[11]]), + pci_data_struct_rev: data[12], + class_code, + image_len, + vendor_rom_rev: u16::from_le_bytes([data[18], data[19]]), + code_type: data[20], + last_image: data[21], + max_runtime_image_len: u16::from_le_bytes([data[22], data[23]]= ), + }) + } + + /// Check if this is the last image in the ROM + fn is_last(&self) -> bool { + self.last_image & LAST_IMAGE_BIT_MASK !=3D 0 + } + + /// Calculate image size in bytes from 512-byte blocks + fn image_size_bytes(&self) -> usize { + self.image_len as usize * 512 + } +} + +/// PCI ROM Expansion Header as defined in PCI Firmware Specification. +/// This is header is at the beginning of every image in the set of +/// images in the ROM. It contains a pointer to the PCI Data Structure +/// which describes the image. +/// For "NBSI" images (NoteBook System Information), the ROM +/// header deviates from the standard and contains an offset to the +/// NBSI image however we do not yet parse that in this module and keep +/// it for future reference. +#[derive(Debug, Clone, Copy)] +#[expect(dead_code)] +struct PciRomHeader { + /// 00h: Signature (0xAA55) + signature: u16, + /// 02h: Reserved bytes for processor architecture unique data (20 byt= es) + reserved: [u8; 20], + /// 16h: NBSI Data Offset (NBSI-specific, offset from header to NBSI i= mage) + nbsi_data_offset: Option, + /// 18h: Pointer to PCI Data Structure (offset from start of ROM image) + pci_data_struct_offset: u16, + /// 1Ah: Size of block (this is NBSI-specific) + size_of_block: Option, +} + +impl PciRomHeader { + fn new(pdev: &pci::Device, data: &[u8]) -> Result { + if data.len() < 26 { + // Need at least 26 bytes to read pciDataStrucPtr and sizeOfBl= ock + return Err(EINVAL); + } + + let signature =3D u16::from_le_bytes([data[0], data[1]]); + + // Check for valid ROM signatures + match signature { + 0xAA55 | 0xBB77 | 0x4E56 =3D> {} + _ =3D> { + dev_err!(pdev.as_ref(), "ROM signature unknown {:#x}\n", s= ignature); + return Err(EINVAL); + } + } + + // Read the pointer to the PCI Data Structure at offset 0x18 + let pci_data_struct_ptr =3D u16::from_le_bytes([data[24], data[25]= ]); + + // Try to read optional fields if enough data + let mut size_of_block =3D None; + let mut nbsi_data_offset =3D None; + + if data.len() >=3D 30 { + // Read size_of_block at offset 0x1A + size_of_block =3D Some( + (data[29] as u32) << 24 + | (data[28] as u32) << 16 + | (data[27] as u32) << 8 + | (data[26] as u32), + ); + } + + // For NBSI images, try to read the nbsiDataOffset at offset 0x16 + if data.len() >=3D 24 { + nbsi_data_offset =3D Some(u16::from_le_bytes([data[22], data[2= 3]])); + } + + Ok(PciRomHeader { + signature, + reserved: [0u8; 20], + pci_data_struct_offset: pci_data_struct_ptr, + size_of_block, + nbsi_data_offset, + }) + } +} + +/// NVIDIA PCI Data Extension Structure. This is similar to the +/// PCI Data Structure, but is Nvidia-specific and is placed right after +/// the PCI Data Structure. It contains some fields that are redundant +/// with the PCI Data Structure, but are needed for traversing the +/// BIOS images. It is expected to be present in all BIOS images except +/// for NBSI images. +#[derive(Debug, Clone)] +#[repr(C)] +struct NpdeStruct { + /// 00h: Signature ("NPDE") + signature: [u8; 4], + /// 04h: NVIDIA PCI Data Extension Revision + npci_data_ext_rev: u16, + /// 06h: NVIDIA PCI Data Extension Length + npci_data_ext_len: u16, + /// 08h: Sub-image Length (in 512-byte units) + subimage_len: u16, + /// 0Ah: Last image indicator flag + last_image: u8, +} + +impl NpdeStruct { + fn new(pdev: &pci::Device, data: &[u8]) -> Option { + if data.len() < core::mem::size_of::() { + dev_dbg!(pdev.as_ref(), "Not enough data for NpdeStruct\n"); + return None; + } + + let mut signature =3D [0u8; 4]; + signature.copy_from_slice(&data[0..4]); + + // Signature should be "NPDE" (0x4544504E) + if &signature !=3D b"NPDE" { + dev_dbg!( + pdev.as_ref(), + "Invalid signature for NpdeStruct: {:?}\n", + signature + ); + return None; + } + + let subimage_len =3D u16::from_le_bytes([data[8], data[9]]); + if subimage_len =3D=3D 0 { + dev_dbg!(pdev.as_ref(), "Invalid subimage length: 0\n"); + return None; + } + + Some(NpdeStruct { + signature, + npci_data_ext_rev: u16::from_le_bytes([data[4], data[5]]), + npci_data_ext_len: u16::from_le_bytes([data[6], data[7]]), + subimage_len, + last_image: data[10], + }) + } + + /// Check if this is the last image in the ROM + fn is_last(&self) -> bool { + self.last_image & LAST_IMAGE_BIT_MASK !=3D 0 + } + + /// Calculate image size in bytes from 512-byte blocks + fn image_size_bytes(&self) -> usize { + self.subimage_len as usize * 512 + } + + /// Try to find NPDE in the data, the NPDE is right after the PCIR. + fn find_in_data( + pdev: &pci::Device, + data: &[u8], + rom_header: &PciRomHeader, + pcir: &PcirStruct, + ) -> Option { + // Calculate the offset where NPDE might be located + // NPDE should be right after the PCIR structure, aligned to 16 by= tes + let pcir_offset =3D rom_header.pci_data_struct_offset as usize; + let npde_start =3D (pcir_offset + pcir.pci_data_struct_len as usiz= e + 0x0F) & !0x0F; + + // Check if we have enough data + if npde_start + core::mem::size_of::() > data.len() { + dev_dbg!(pdev.as_ref(), "Not enough data for NPDE\n"); + return None; + } + + // Try to create NPDE from the data + NpdeStruct::new(pdev, &data[npde_start..]) + } +} + +// Use a macro to implement BiosImage enum and methods. This avoids having= to +// repeat each enum type when implementing functions like base() in BiosIm= age. +macro_rules! bios_image { + ( + $($variant:ident: $class:ident),* $(,)? + ) =3D> { + // BiosImage enum with variants for each image type + enum BiosImage { + $($variant($class)),* + } + + impl BiosImage { + /// Get a reference to the common BIOS image data regardless o= f type + fn base(&self) -> &BiosImageBase { + match self { + $(Self::$variant(img) =3D> &img.base),* + } + } + + /// Returns a string representing the type of BIOS image + fn image_type_str(&self) -> &'static str { + match self { + $(Self::$variant(_) =3D> stringify!($variant)),* + } + } + } + } +} + +impl BiosImage { + /// Check if this is the last image + fn is_last(&self) -> bool { + let base =3D self.base(); + + // For NBSI images (type =3D=3D 0x70), return true as they're + // considered the last image + if matches!(self, Self::Nbsi(_)) { + return true; + } + + // For other image types, check the NPDE first if available + if let Some(ref npde) =3D base.npde { + return npde.is_last(); + } + + // Otherwise, fall back to checking the PCIR last_image flag + base.pcir.is_last() + } + + /// Get the image size in bytes + fn image_size_bytes(&self) -> usize { + let base =3D self.base(); + + // Prefer NPDE image size if available + if let Some(ref npde) =3D base.npde { + return npde.image_size_bytes(); + } + + // Otherwise, fall back to the PCIR image size + base.pcir.image_size_bytes() + } + + /// Create a BiosImageBase from a byte slice and convert it to a BiosI= mage + /// which triggers the constructor of the specific BiosImage enum vari= ant. + fn new(pdev: &pci::Device, data: &[u8]) -> Result { + let base =3D BiosImageBase::new(pdev, data)?; + let image =3D base.into_image().inspect_err(|e| { + dev_err!(pdev.as_ref(), "Failed to create BiosImage: {:?}\n", = e); + })?; + + Ok(image) + } +} + +bios_image! { + PciAt: PciAtBiosImage, // PCI-AT compatible BIOS image + Efi: EfiBiosImage, // EFI (Extensible Firmware Interface) + Nbsi: NbsiBiosImage, // NBSI (Nvidia Bios System Interface) + FwSec: FwSecBiosImage, // FWSEC (Firmware Security) +} + +struct PciAtBiosImage { + base: BiosImageBase, + // PCI-AT-specific fields can be added here in the future. +} + +struct EfiBiosImage { + base: BiosImageBase, + // EFI-specific fields can be added here in the future. +} + +struct NbsiBiosImage { + base: BiosImageBase, + // NBSI-specific fields can be added here in the future. +} + +struct FwSecBiosImage { + base: BiosImageBase, + // FWSEC-specific fields can be added here in the future. +} + +// Convert from BiosImageBase to BiosImage +impl TryFrom for BiosImage { + type Error =3D Error; + + fn try_from(base: BiosImageBase) -> Result { + match base.pcir.code_type { + 0x00 =3D> Ok(BiosImage::PciAt(PciAtBiosImage { base })), + 0x03 =3D> Ok(BiosImage::Efi(EfiBiosImage { base })), + 0x70 =3D> Ok(BiosImage::Nbsi(NbsiBiosImage { base })), + 0xE0 =3D> Ok(BiosImage::FwSec(FwSecBiosImage { base })), + _ =3D> Err(EINVAL), + } + } +} + +/// BIOS Image structure containing various headers and references +/// fields base to all BIOS images. Each BiosImage type has a +/// BiosImageBase type along with other image-specific fields. +/// Note that Rust favors composition of types over inheritance. +#[derive(Debug)] +#[expect(dead_code)] +struct BiosImageBase { + /// PCI ROM Expansion Header + rom_header: PciRomHeader, + /// PCI Data Structure + pcir: PcirStruct, + /// NVIDIA PCI Data Extension (optional) + npde: Option, + /// Image data (includes ROM header and PCIR) + data: KVec, +} + +impl BiosImageBase { + fn into_image(self) -> Result { + BiosImage::try_from(self) + } + + /// Creates a new BiosImageBase from raw byte data. + fn new(pdev: &pci::Device, data: &[u8]) -> Result { + // Ensure we have enough data for the ROM header + if data.len() < 26 { + dev_err!(pdev.as_ref(), "Not enough data for ROM header\n"); + return Err(EINVAL); + } + + // Parse the ROM header + let rom_header =3D PciRomHeader::new(pdev, &data[0..26]) + .inspect_err(|e| dev_err!(pdev.as_ref(), "Failed to create Pci= RomHeader: {:?}\n", e))?; + + // Get the PCI Data Structure using the pointer from the ROM header + let pcir_offset =3D rom_header.pci_data_struct_offset as usize; + let pcir_data =3D data + .get(pcir_offset..pcir_offset + core::mem::size_of::()) + .ok_or(EINVAL) + .inspect_err(|_| { + dev_err!( + pdev.as_ref(), + "PCIR offset {:#x} out of bounds (data length: {})\n", + pcir_offset, + data.len() + ); + dev_err!( + pdev.as_ref(), + "Consider reading more data for construction of BiosIm= age\n" + ); + })?; + + let pcir =3D PcirStruct::new(pdev, pcir_data) + .inspect_err(|e| dev_err!(pdev.as_ref(), "Failed to create Pci= rStruct: {:?}\n", e))?; + + // Look for NPDE structure if this is not an NBSI image (type !=3D= 0x70) + let npde =3D NpdeStruct::find_in_data(pdev, data, &rom_header, &pc= ir); + + // Create a copy of the data + let mut data_copy =3D KVec::new(); + data_copy.extend_with(data.len(), 0, GFP_KERNEL)?; + data_copy.copy_from_slice(data); + + Ok(BiosImageBase { + rom_header, + pcir, + npde, + data: data_copy, + }) + } +} --=20 2.49.0 From nobody Fri Dec 19 02:53:47 2025 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2063.outbound.protection.outlook.com [40.107.92.63]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0990D26FD8F; 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Add support for the same. Signed-off-by: Joel Fernandes Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/vbios.rs | 179 +++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 177 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nova-core/vbios.rs b/drivers/gpu/nova-core/vbios.rs index b9879590ae3aae6517683a6ed02f7f639055598e..445b7ee5893c9d16a82254e70d9= 37a902b1d0fae 100644 --- a/drivers/gpu/nova-core/vbios.rs +++ b/drivers/gpu/nova-core/vbios.rs @@ -330,6 +330,111 @@ fn image_size_bytes(&self) -> usize { } } =20 +/// BIOS Information Table (BIT) Header +/// This is the head of the BIT table, that is used to locate the Falcon d= ata. +/// The BIT table (with its header) is in the PciAtBiosImage and the falco= n data +/// it is pointing to is in the FwSecBiosImage. +#[derive(Debug, Clone, Copy)] +#[expect(dead_code)] +struct BitHeader { + /// 0h: BIT Header Identifier (BMP=3D0x7FFF/BIT=3D0xB8FF) + id: u16, + /// 2h: BIT Header Signature ("BIT\0") + signature: [u8; 4], + /// 6h: Binary Coded Decimal Version, ex: 0x0100 is 1.00. + bcd_version: u16, + /// 8h: Size of BIT Header (in bytes) + header_size: u8, + /// 9h: Size of BIT Tokens (in bytes) + token_size: u8, + /// 10h: Number of token entries that follow + token_entries: u8, + /// 11h: BIT Header Checksum + checksum: u8, +} + +impl BitHeader { + fn new(data: &[u8]) -> Result { + if data.len() < 12 { + return Err(EINVAL); + } + + let mut signature =3D [0u8; 4]; + signature.copy_from_slice(&data[2..6]); + + // Check header ID and signature + let id =3D u16::from_le_bytes([data[0], data[1]]); + if id !=3D 0xB8FF || &signature !=3D b"BIT\0" { + return Err(EINVAL); + } + + Ok(BitHeader { + id, + signature, + bcd_version: u16::from_le_bytes([data[6], data[7]]), + header_size: data[8], + token_size: data[9], + token_entries: data[10], + checksum: data[11], + }) + } +} + +/// BIT Token Entry: Records in the BIT table followed by the BIT header +#[derive(Debug, Clone, Copy)] +#[expect(dead_code)] +struct BitToken { + /// 00h: Token identifier + id: u8, + /// 01h: Version of the token data + data_version: u8, + /// 02h: Size of token data in bytes + data_size: u16, + /// 04h: Offset to the token data + data_offset: u16, +} + +// Define the token ID for the Falcon data +const BIT_TOKEN_ID_FALCON_DATA: u8 =3D 0x70; + +impl BitToken { + /// Find a BIT token entry by BIT ID in a PciAtBiosImage + fn from_id(image: &PciAtBiosImage, token_id: u8) -> Result { + let header =3D &image.bit_header; + + // Offset to the first token entry + let tokens_start =3D image.bit_offset + header.header_size as usiz= e; + + for i in 0..header.token_entries as usize { + let entry_offset =3D tokens_start + (i * header.token_size as = usize); + + // Make sure we don't go out of bounds + if entry_offset + header.token_size as usize > image.base.data= .len() { + return Err(EINVAL); + } + + // Check if this token has the requested ID + if image.base.data[entry_offset] =3D=3D token_id { + return Ok(BitToken { + id: image.base.data[entry_offset], + data_version: image.base.data[entry_offset + 1], + data_size: u16::from_le_bytes([ + image.base.data[entry_offset + 2], + image.base.data[entry_offset + 3], + ]), + data_offset: u16::from_le_bytes([ + image.base.data[entry_offset + 4], + image.base.data[entry_offset + 5], + ]), + }); + } + } + + // Token not found + Err(ENOENT) + } +} + /// PCI ROM Expansion Header as defined in PCI Firmware Specification. /// This is header is at the beginning of every image in the set of /// images in the ROM. It contains a pointer to the PCI Data Structure @@ -575,7 +680,8 @@ fn new(pdev: &pci::Device, data: &[u8]) -> Result= { =20 struct PciAtBiosImage { base: BiosImageBase, - // PCI-AT-specific fields can be added here in the future. + bit_header: BitHeader, + bit_offset: usize, } =20 struct EfiBiosImage { @@ -599,7 +705,7 @@ impl TryFrom for BiosImage { =20 fn try_from(base: BiosImageBase) -> Result { match base.pcir.code_type { - 0x00 =3D> Ok(BiosImage::PciAt(PciAtBiosImage { base })), + 0x00 =3D> Ok(BiosImage::PciAt(base.try_into()?)), 0x03 =3D> Ok(BiosImage::Efi(EfiBiosImage { base })), 0x70 =3D> Ok(BiosImage::Nbsi(NbsiBiosImage { base })), 0xE0 =3D> Ok(BiosImage::FwSec(FwSecBiosImage { base })), @@ -679,3 +785,72 @@ fn new(pdev: &pci::Device, data: &[u8]) -> Result { }) } } + +/// The PciAt BIOS image is typically the first BIOS image type found in t= he +/// BIOS image chain. It contains the BIT header and the BIT tokens. +impl PciAtBiosImage { + /// Find a byte pattern in a slice + fn find_byte_pattern(haystack: &[u8], needle: &[u8]) -> Result { + haystack + .windows(needle.len()) + .position(|window| window =3D=3D needle) + .ok_or(EINVAL) + } + + /// Find the BIT header in the PciAtBiosImage + fn find_bit_header(data: &[u8]) -> Result<(BitHeader, usize)> { + let bit_pattern =3D [0xff, 0xb8, b'B', b'I', b'T', 0x00]; + let bit_offset =3D Self::find_byte_pattern(data, &bit_pattern)?; + let bit_header =3D BitHeader::new(&data[bit_offset..])?; + + Ok((bit_header, bit_offset)) + } + + /// Get a BIT token entry from the BIT table in the PciAtBiosImage + fn get_bit_token(&self, token_id: u8) -> Result { + BitToken::from_id(self, token_id) + } + + /// Find the Falcon data pointer structure in the PciAtBiosImage + /// This is just a 4 byte structure that contains a pointer to the + /// Falcon data in the FWSEC image. + fn falcon_data_ptr(&self, pdev: &pci::Device) -> Result { + let token =3D self.get_bit_token(BIT_TOKEN_ID_FALCON_DATA)?; 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Received: from CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) by DM6PR12MB4353.namprd12.prod.outlook.com (2603:10b6:5:2a6::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8857.21; Thu, 19 Jun 2025 13:25:31 +0000 Received: from CH2PR12MB3990.namprd12.prod.outlook.com ([fe80::6e37:569f:82ee:3f99]) by CH2PR12MB3990.namprd12.prod.outlook.com ([fe80::6e37:569f:82ee:3f99%4]) with mapi id 15.20.8857.019; Thu, 19 Jun 2025 13:25:31 +0000 From: Alexandre Courbot Date: Thu, 19 Jun 2025 22:24:03 +0900 Subject: [PATCH v6 19/24] gpu: nova-core: vbios: Add support for FWSEC ucode extraction Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250619-nova-frts-v6-19-ecf41ef99252@nvidia.com> References: <20250619-nova-frts-v6-0-ecf41ef99252@nvidia.com> In-Reply-To: <20250619-nova-frts-v6-0-ecf41ef99252@nvidia.com> To: Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Benno Lossin Cc: John Hubbard , Ben Skeggs , Joel Fernandes , Timur Tabi , Alistair Popple , linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Alexandre Courbot , Shirish Baskaran X-Mailer: b4 0.14.2 X-ClientProxiedBy: TYCP286CA0219.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:3c5::15) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|DM6PR12MB4353:EE_ X-MS-Office365-Filtering-Correlation-Id: ea7f2c51-b8e5-49e5-dc70-08ddaf34c3c6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|10070799003|376014|366016|1800799024|921020; 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The main data extracted from the vBIOS is the FWSEC-FRTS firmware which runs on the GSP processor. This firmware runs in high secure mode, and sets up the WPR2 (Write protected region) before the Booter runs on the SEC2 processor. Tested on my Ampere GA102 and boot is successful. [applied changes by Alex Courbot for fwsec signatures] [acourbot@nvidia.com: remove now-unneeded Devres acquisition] Cc: Alexandre Courbot Cc: John Hubbard Cc: Shirish Baskaran Cc: Alistair Popple Cc: Timur Tabi Cc: Ben Skeggs Signed-off-by: Alexandre Courbot Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/firmware.rs | 2 - drivers/gpu/nova-core/vbios.rs | 307 ++++++++++++++++++++++++++++++++++= ++-- 2 files changed, 298 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index 41f43a729ad3bf2c4acb6108f41e0905a6fac0df..e5583925cb3b4353b521c68175f= 8cf0c2d6ce830 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -44,7 +44,6 @@ pub(crate) fn new(dev: &device::Device, chipset: Chipset,= ver: &str) -> Result usize { const HDR_SIZE_SHIFT: u32 =3D 16; const HDR_SIZE_MASK: u32 =3D 0xffff0000; diff --git a/drivers/gpu/nova-core/vbios.rs b/drivers/gpu/nova-core/vbios.rs index 445b7ee5893c9d16a82254e70d937a902b1d0fae..0149621dca1aaea5b342ff32e47= 01de49e988839 100644 --- a/drivers/gpu/nova-core/vbios.rs +++ b/drivers/gpu/nova-core/vbios.rs @@ -6,7 +6,9 @@ #![expect(dead_code)] =20 use crate::driver::Bar0; +use crate::firmware::FalconUCodeDescV3; use core::convert::TryFrom; +use kernel::device; use kernel::error::Result; use kernel::pci; use kernel::prelude::*; @@ -192,8 +194,8 @@ impl Vbios { pub(crate) fn new(pdev: &pci::Device, bar0: &Bar0) -> Result { // Images to extract from iteration let mut pci_at_image: Option =3D None; - let mut first_fwsec_image: Option =3D None; - let mut second_fwsec_image: Option =3D None; + let mut first_fwsec_image: Option =3D None; + let mut second_fwsec_image: Option =3D None; =20 // Parse all VBIOS images in the ROM for image_result in VbiosIterator::new(pdev, bar0)? { @@ -227,12 +229,14 @@ pub(crate) fn new(pdev: &pci::Device, bar0: &Bar0) ->= Result { } =20 // Using all the images, setup the falcon data pointer in Fwsec. - // These are temporarily unused images and will be used in later p= atches. - if let (Some(second), Some(_first), Some(_pci_at)) =3D + if let (Some(mut second), Some(first), Some(pci_at)) =3D (second_fwsec_image, first_fwsec_image, pci_at_image) { + second + .setup_falcon_data(pdev, &pci_at, &first) + .inspect_err(|e| dev_err!(pdev.as_ref(), "Falcon data setu= p failed: {:?}\n", e))?; Ok(Vbios { - fwsec_image: second, + fwsec_image: second.build(pdev)?, }) } else { dev_err!( @@ -242,6 +246,10 @@ pub(crate) fn new(pdev: &pci::Device, bar0: &Bar0) -> = Result { Err(EINVAL) } } + + pub(crate) fn fwsec_image(&self) -> &FwSecBiosImage { + &self.fwsec_image + } } =20 /// PCI Data Structure as defined in PCI Firmware Specification @@ -675,7 +683,7 @@ fn new(pdev: &pci::Device, data: &[u8]) -> Result= { PciAt: PciAtBiosImage, // PCI-AT compatible BIOS image Efi: EfiBiosImage, // EFI (Extensible Firmware Interface) Nbsi: NbsiBiosImage, // NBSI (Nvidia Bios System Interface) - FwSec: FwSecBiosImage, // FWSEC (Firmware Security) + FwSec: FwSecBiosBuilder, // FWSEC (Firmware Security) } =20 struct PciAtBiosImage { @@ -694,9 +702,24 @@ struct NbsiBiosImage { // NBSI-specific fields can be added here in the future. } =20 -struct FwSecBiosImage { +struct FwSecBiosBuilder { base: BiosImageBase, - // FWSEC-specific fields can be added here in the future. + /// These are temporary fields that are used during the construction of + /// the FwSecBiosBuilder. Once FwSecBiosBuilder is constructed, the + /// falcon_ucode_offset will be copied into a new FwSecBiosImage. + /// + /// The offset of the Falcon data from the start of Fwsec image + falcon_data_offset: Option, + /// The PmuLookupTable starts at the offset of the falcon data pointer + pmu_lookup_table: Option, + /// The offset of the Falcon ucode + falcon_ucode_offset: Option, +} + +pub(crate) struct FwSecBiosImage { + base: BiosImageBase, + /// The offset of the Falcon ucode + falcon_ucode_offset: usize, } =20 // Convert from BiosImageBase to BiosImage @@ -708,7 +731,12 @@ fn try_from(base: BiosImageBase) -> Result { 0x00 =3D> Ok(BiosImage::PciAt(base.try_into()?)), 0x03 =3D> Ok(BiosImage::Efi(EfiBiosImage { base })), 0x70 =3D> Ok(BiosImage::Nbsi(NbsiBiosImage { base })), - 0xE0 =3D> Ok(BiosImage::FwSec(FwSecBiosImage { base })), + 0xE0 =3D> Ok(BiosImage::FwSec(FwSecBiosBuilder { + base, + falcon_data_offset: None, + pmu_lookup_table: None, + falcon_ucode_offset: None, + })), _ =3D> Err(EINVAL), } } @@ -854,3 +882,264 @@ fn try_from(base: BiosImageBase) -> Result { }) } } + +/// The PmuLookupTableEntry structure is a single entry in the PmuLookupTa= ble. +/// See the PmuLookupTable description for more information. +#[expect(dead_code)] +struct PmuLookupTableEntry { + application_id: u8, + target_id: u8, + data: u32, +} + +impl PmuLookupTableEntry { + fn new(data: &[u8]) -> Result { + if data.len() < 5 { + return Err(EINVAL); + } + + Ok(PmuLookupTableEntry { + application_id: data[0], + target_id: data[1], + data: u32::from_le_bytes(data[2..6].try_into().map_err(|_| EIN= VAL)?), + }) + } +} + +/// The PmuLookupTableEntry structure is used to find the PmuLookupTableEn= try +/// for a given application ID. The table of entries is pointed to by the = falcon +/// data pointer in the BIT table, and is used to locate the Falcon Ucode. +#[expect(dead_code)] +struct PmuLookupTable { + version: u8, + header_len: u8, + entry_len: u8, + entry_count: u8, + table_data: KVec, +} + +impl PmuLookupTable { + fn new(pdev: &pci::Device, data: &[u8]) -> Result { + if data.len() < 4 { + return Err(EINVAL); + } + + let header_len =3D data[1] as usize; + let entry_len =3D data[2] as usize; + let entry_count =3D data[3] as usize; + + let required_bytes =3D header_len + (entry_count * entry_len); + + if data.len() < required_bytes { + dev_err!( + pdev.as_ref(), + "PmuLookupTable data length less than required\n" + ); + return Err(EINVAL); + } + + // Create a copy of only the table data + let table_data =3D { + let mut ret =3D KVec::new(); + ret.extend_from_slice(&data[header_len..required_bytes], GFP_K= ERNEL)?; + ret + }; + + // Debug logging of entries (dumps the table data to dmesg) + for i in (header_len..required_bytes).step_by(entry_len) { + dev_dbg!( + pdev.as_ref(), + "PMU entry: {:02x?}\n", + &data[i..][..entry_len] + ); + } + + Ok(PmuLookupTable { + version: data[0], + header_len: header_len as u8, + entry_len: entry_len as u8, + entry_count: entry_count as u8, + table_data, + }) + } + + fn lookup_index(&self, idx: u8) -> Result { + if idx >=3D self.entry_count { + return Err(EINVAL); + } + + let index =3D (idx as usize) * self.entry_len as usize; + PmuLookupTableEntry::new(&self.table_data[index..]) + } + + // find entry by type value + fn find_entry_by_type(&self, entry_type: u8) -> Result { + for i in 0..self.entry_count { + let entry =3D self.lookup_index(i)?; + if entry.application_id =3D=3D entry_type { + return Ok(entry); + } + } + + Err(EINVAL) + } +} + +/// The FwSecBiosImage structure contains the PMU table and the Falcon Uco= de. +/// The PMU table contains voltage/frequency tables as well as a pointer t= o the +/// Falcon Ucode. +impl FwSecBiosBuilder { + fn setup_falcon_data( + &mut self, + pdev: &pci::Device, + pci_at_image: &PciAtBiosImage, + first_fwsec: &FwSecBiosBuilder, + ) -> Result { + let mut offset =3D pci_at_image.falcon_data_ptr(pdev)? as usize; + let mut pmu_in_first_fwsec =3D false; + + // The falcon data pointer assumes that the PciAt and FWSEC images + // are contiguous in memory. However, testing shows the EFI image = sits in + // between them. So calculate the offset from the end of the PciAt= image + // rather than the start of it. Compensate. + offset -=3D pci_at_image.base.data.len(); + + // The offset is now from the start of the first Fwsec image, howe= ver + // the offset points to a location in the second Fwsec image. Since + // the fwsec images are contiguous, subtract the length of the fir= st Fwsec + // image from the offset to get the offset to the start of the sec= ond + // Fwsec image. + if offset < first_fwsec.base.data.len() { + pmu_in_first_fwsec =3D true; + } else { + offset -=3D first_fwsec.base.data.len(); + } + + self.falcon_data_offset =3D Some(offset); + + if pmu_in_first_fwsec { + self.pmu_lookup_table =3D + Some(PmuLookupTable::new(pdev, &first_fwsec.base.data[offs= et..])?); + } else { + self.pmu_lookup_table =3D Some(PmuLookupTable::new(pdev, &self= .base.data[offset..])?); + } + + match self + .pmu_lookup_table + .as_ref() + .ok_or(EINVAL)? + .find_entry_by_type(FALCON_UCODE_ENTRY_APPID_FWSEC_PROD) + { + Ok(entry) =3D> { + let mut ucode_offset =3D entry.data as usize; + ucode_offset -=3D pci_at_image.base.data.len(); + if ucode_offset < first_fwsec.base.data.len() { + dev_err!(pdev.as_ref(), "Falcon Ucode offset not in se= cond Fwsec.\n"); + return Err(EINVAL); + } + ucode_offset -=3D first_fwsec.base.data.len(); + self.falcon_ucode_offset =3D Some(ucode_offset); + } + Err(e) =3D> { + dev_err!( + pdev.as_ref(), + "PmuLookupTableEntry not found, error: {:?}\n", + e + ); + return Err(EINVAL); + } + } + Ok(()) + } + + /// Build the final FwSecBiosImage from this builder + fn build(self, pdev: &pci::Device) -> Result { + let ret =3D FwSecBiosImage { + base: self.base, + falcon_ucode_offset: self.falcon_ucode_offset.ok_or(EINVAL)?, + }; + + if cfg!(debug_assertions) { + // Print the desc header for debugging + let desc =3D ret.header(pdev.as_ref())?; + dev_dbg!(pdev.as_ref(), "PmuLookupTableEntry desc: {:#?}\n", d= esc); + } + + Ok(ret) + } +} + +impl FwSecBiosImage { + /// Get the FwSec header (FalconUCodeDescV3) + pub(crate) fn header(&self, dev: &device::Device) -> Result<&FalconUCo= deDescV3> { + // Get the falcon ucode offset that was found in setup_falcon_data + let falcon_ucode_offset =3D self.falcon_ucode_offset; + + // Make sure the offset is within the data bounds + if falcon_ucode_offset + core::mem::size_of::()= > self.base.data.len() { + dev_err!(dev, "fwsec-frts header not contained within BIOS bou= nds\n"); + return Err(ERANGE); + } + + // Read the first 4 bytes to get the version + let hdr_bytes: [u8; 4] =3D self.base.data[falcon_ucode_offset..fal= con_ucode_offset + 4] + .try_into() + .map_err(|_| EINVAL)?; + let hdr =3D u32::from_le_bytes(hdr_bytes); + let ver =3D (hdr & 0xff00) >> 8; + + if ver !=3D 3 { + dev_err!(dev, "invalid fwsec firmware version: {:?}\n", ver); + return Err(EINVAL); + } + + // Return a reference to the FalconUCodeDescV3 structure. + // SAFETY: we have checked that `falcon_ucode_offset + size_of::` + // is within the bounds of `data`. Also, this data vector is from = ROM, and 'data' field + // in BiosImageBase is immutable after construction. + Ok(unsafe { + &*(self + .base + .data + .as_ptr() + .add(falcon_ucode_offset) + .cast::()) + }) + } + + /// Get the ucode data as a byte slice + pub(crate) fn ucode(&self, dev: &device::Device, desc: &FalconUCodeDes= cV3) -> Result<&[u8]> { + let falcon_ucode_offset =3D self.falcon_ucode_offset; + + // The ucode data follows the descriptor + let ucode_data_offset =3D falcon_ucode_offset + desc.size(); + let size =3D (desc.imem_load_size + desc.dmem_load_size) as usize; + + // Get the data slice, checking bounds in a single operation + self.base + .data + .get(ucode_data_offset..ucode_data_offset + size) + .ok_or(ERANGE) + .inspect_err(|_| dev_err!(dev, "fwsec ucode data not contained= within BIOS bounds\n")) + } + + /// Get the signatures as a byte slice + pub(crate) fn sigs(&self, dev: &device::Device, desc: &FalconUCodeDesc= V3) -> Result<&[u8]> { + const SIG_SIZE: usize =3D 96 * 4; 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Do this in a `FbLayout` structure, that will be later extended to describe more memory regions used to boot the GSP. Reviewed-by: Lyude Paul Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/fb.rs | 70 ++++++++++++++++++++++++++++++++ drivers/gpu/nova-core/fb/hal.rs | 12 +++++- drivers/gpu/nova-core/fb/hal/ga100.rs | 12 ++++++ drivers/gpu/nova-core/fb/hal/ga102.rs | 36 +++++++++++++++++ drivers/gpu/nova-core/fb/hal/tu102.rs | 16 ++++++++ drivers/gpu/nova-core/gpu.rs | 4 ++ drivers/gpu/nova-core/regs.rs | 76 +++++++++++++++++++++++++++++++= ++++ 7 files changed, 224 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs index 308cd76edfee5a2e8a4cd979c20da2ce51cb16a5..dc009a3ed44c2de7ffeb8cc0be0= 6a72cf2ca5309 100644 --- a/drivers/gpu/nova-core/fb.rs +++ b/drivers/gpu/nova-core/fb.rs @@ -1,12 +1,16 @@ // SPDX-License-Identifier: GPL-2.0 =20 +use core::ops::Range; + use kernel::prelude::*; +use kernel::sizes::*; use kernel::types::ARef; use kernel::{dev_warn, device}; =20 use crate::dma::DmaObject; use crate::driver::Bar0; use crate::gpu::Chipset; +use crate::regs; =20 mod hal; =20 @@ -64,3 +68,69 @@ pub(crate) fn unregister(self, bar: &Bar0) { } } } + +/// Layout of the GPU framebuffer memory. +/// +/// Contains ranges of GPU memory reserved for a given purpose during the = GSP bootup process. +#[derive(Debug)] +#[expect(dead_code)] +pub(crate) struct FbLayout { + pub(crate) fb: Range, + pub(crate) vga_workspace: Range, + pub(crate) frts: Range, +} + +impl FbLayout { + /// Computes the FB layout. + pub(crate) fn new(chipset: Chipset, bar: &Bar0) -> Result { + let hal =3D hal::fb_hal(chipset); + + let fb =3D { + let fb_size =3D hal.vidmem_size(bar); + + 0..fb_size + }; + + let vga_workspace =3D { + let vga_base =3D { + const NV_PRAMIN_SIZE: u64 =3D SZ_1M as u64; + let base =3D fb.end - NV_PRAMIN_SIZE; + + if hal.supports_display(bar) { + match regs::NV_PDISP_VGA_WORKSPACE_BASE::read(bar).vga= _workspace_addr() { + Some(addr) =3D> { + if addr < base { + const VBIOS_WORKSPACE_SIZE: u64 =3D SZ_128= K as u64; + + // Point workspace address to end of frame= buffer. + fb.end - VBIOS_WORKSPACE_SIZE + } else { + addr + } + } + None =3D> base, + } + } else { + base + } + }; + + vga_base..fb.end + }; + + let frts =3D { + const FRTS_DOWN_ALIGN: u64 =3D SZ_128K as u64; + const FRTS_SIZE: u64 =3D SZ_1M as u64; + // TODO: replace with `align_down` once it lands. + let frts_base =3D (vga_workspace.start & !(FRTS_DOWN_ALIGN - 1= )) - FRTS_SIZE; + + frts_base..frts_base + FRTS_SIZE + }; + + Ok(Self { + fb, + vga_workspace, + frts, + }) + } +} diff --git a/drivers/gpu/nova-core/fb/hal.rs b/drivers/gpu/nova-core/fb/hal= .rs index 23eab57eec9f524e066d3324eb7f5f2bf78481d2..2f914948bb9a9842fd00a4c6381= 420b74de81c3f 100644 --- a/drivers/gpu/nova-core/fb/hal.rs +++ b/drivers/gpu/nova-core/fb/hal.rs @@ -6,6 +6,7 @@ use crate::gpu::Chipset; =20 mod ga100; +mod ga102; mod tu102; =20 pub(crate) trait FbHal { @@ -16,6 +17,12 @@ pub(crate) trait FbHal { /// /// This might fail if the address is too large for the receiving regi= ster. fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result; + + /// Returns `true` is display is supported. + fn supports_display(&self, bar: &Bar0) -> bool; + + /// Returns the VRAM size, in bytes. + fn vidmem_size(&self, bar: &Bar0) -> u64; } =20 /// Returns the HAL corresponding to `chipset`. @@ -24,8 +31,9 @@ pub(super) fn fb_hal(chipset: Chipset) -> &'static dyn Fb= Hal { =20 match chipset { TU102 | TU104 | TU106 | TU117 | TU116 =3D> tu102::TU102_HAL, - GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD= 104 | AD106 | AD107 =3D> { - ga100::GA100_HAL + GA100 =3D> ga100::GA100_HAL, + GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD= 106 | AD107 =3D> { + ga102::GA102_HAL } } } diff --git a/drivers/gpu/nova-core/fb/hal/ga100.rs b/drivers/gpu/nova-core/= fb/hal/ga100.rs index 7c10436c1c590d9b767c399b69370697fdf8d239..4827721c9860649601b274c3986= 470096e1fe9bc 100644 --- a/drivers/gpu/nova-core/fb/hal/ga100.rs +++ b/drivers/gpu/nova-core/fb/hal/ga100.rs @@ -25,6 +25,10 @@ pub(super) fn write_sysmem_flush_page_ga100(bar: &Bar0, = addr: u64) { .write(bar); } =20 +pub(super) fn display_enabled_ga100(bar: &Bar0) -> bool { + !regs::ga100::NV_FUSE_STATUS_OPT_DISPLAY::read(bar).display_disabled() +} + /// Shift applied to the sysmem address before it is written into /// `NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI`, const FLUSH_SYSMEM_ADDR_SHIFT_HI: u32 =3D 40; @@ -39,6 +43,14 @@ fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64)= -> Result { =20 Ok(()) } + + fn supports_display(&self, bar: &Bar0) -> bool { + display_enabled_ga100(bar) + } + + fn vidmem_size(&self, bar: &Bar0) -> u64 { + super::tu102::vidmem_size_gp102(bar) + } } =20 const GA100: Ga100 =3D Ga100; diff --git a/drivers/gpu/nova-core/fb/hal/ga102.rs b/drivers/gpu/nova-core/= fb/hal/ga102.rs new file mode 100644 index 0000000000000000000000000000000000000000..a73b77e3971513d088211a97ad8= e50b00a9131f7 --- /dev/null +++ b/drivers/gpu/nova-core/fb/hal/ga102.rs @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0 + +use kernel::prelude::*; + +use crate::driver::Bar0; +use crate::fb::hal::FbHal; +use crate::regs; + +fn vidmem_size_ga102(bar: &Bar0) -> u64 { + regs::NV_USABLE_FB_SIZE_IN_MB::read(bar).usable_fb_size() +} + +struct Ga102; + +impl FbHal for Ga102 { + fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { + super::ga100::read_sysmem_flush_page_ga100(bar) + } + + fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { + super::ga100::write_sysmem_flush_page_ga100(bar, addr); + + Ok(()) + } + + fn supports_display(&self, bar: &Bar0) -> bool { + super::ga100::display_enabled_ga100(bar) + } + + fn vidmem_size(&self, bar: &Bar0) -> u64 { + vidmem_size_ga102(bar) + } +} + +const GA102: Ga102 =3D Ga102; +pub(super) const GA102_HAL: &dyn FbHal =3D &GA102; diff --git a/drivers/gpu/nova-core/fb/hal/tu102.rs b/drivers/gpu/nova-core/= fb/hal/tu102.rs index 048859f9fd9d6cfb630da0a8c3513becf3ab62d6..6f8ae58e9481017f1a81fb8e75f= b24782e50a781 100644 --- a/drivers/gpu/nova-core/fb/hal/tu102.rs +++ b/drivers/gpu/nova-core/fb/hal/tu102.rs @@ -26,6 +26,14 @@ pub(super) fn write_sysmem_flush_page_gm107(bar: &Bar0, = addr: u64) -> Result { } } =20 +pub(super) fn display_enabled_gm107(bar: &Bar0) -> bool { + !regs::gm107::NV_FUSE_STATUS_OPT_DISPLAY::read(bar).display_disabled() +} + +pub(super) fn vidmem_size_gp102(bar: &Bar0) -> u64 { + regs::NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE::read(bar).usable_fb_size() +} + struct Tu102; =20 impl FbHal for Tu102 { @@ -36,6 +44,14 @@ fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { write_sysmem_flush_page_gm107(bar, addr) } + + fn supports_display(&self, bar: &Bar0) -> bool { + display_enabled_gm107(bar) + } + + fn vidmem_size(&self, bar: &Bar0) -> u64 { + vidmem_size_gp102(bar) + } } =20 const TU102: Tu102 =3D Tu102; diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 1c577d3eff8b32bbc45d7d2302c3e2246bef3b44..413f1ab85b37926cdfd9a9c7616= 7816b21d89adc 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -4,6 +4,7 @@ =20 use crate::driver::Bar0; use crate::falcon::{gsp::Gsp, sec2::Sec2, Falcon}; +use crate::fb::FbLayout; use crate::fb::SysmemFlush; use crate::firmware::{Firmware, FIRMWARE_VERSION}; use crate::gfw; @@ -219,6 +220,9 @@ pub(crate) fn new( =20 let _sec2_falcon =3D Falcon::::new(pdev.as_ref(), spec.chips= et, bar, true)?; =20 + let fb_layout =3D FbLayout::new(spec.chipset, bar)?; + dev_dbg!(pdev.as_ref(), "{:#x?}\n", fb_layout); + // Will be used in a later patch when fwsec firmware is needed. let _bios =3D Vbios::new(pdev, bar)?; =20 diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index a2f449eb08b5691aaa6f2f0e7635791838996806..8ca7bcb5a93f4b60ee9ee488f26= 469af48e2f1d8 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -52,6 +52,27 @@ pub(crate) fn chipset(self) -> Result { 23:0 adr_63_40 as u32; }); =20 +register!(NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE @ 0x00100ce0 { + 3:0 lower_scale as u8; + 9:4 lower_mag as u8; + 30:30 ecc_mode_enabled as bool; +}); + +impl NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE { + /// Returns the usable framebuffer size, in bytes. + pub(crate) fn usable_fb_size(self) -> u64 { + let size =3D ((self.lower_mag() as u64) << (self.lower_scale() as = u64)) + * kernel::sizes::SZ_1M as u64; + + if self.ecc_mode_enabled() { + // Remove the amount of memory reserved for ECC (one per 16 un= its). + size / 16 * 15 + } else { + size + } + } +} + /* PGC6 */ =20 register!(NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK @ 0x00118128= { @@ -77,6 +98,42 @@ pub(crate) fn completed(self) -> bool { } } =20 +register!(NV_PGC6_AON_SECURE_SCRATCH_GROUP_42 @ 0x001183a4 { + 31:0 value as u32; +}); + +register!( + NV_USABLE_FB_SIZE_IN_MB =3D> NV_PGC6_AON_SECURE_SCRATCH_GROUP_42, + "Scratch group 42 register used as framebuffer size" { + 31:0 value as u32, "Usable framebuffer size, in megabytes"; + } +); + +impl NV_USABLE_FB_SIZE_IN_MB { + /// Returns the usable framebuffer size, in bytes. + pub(crate) fn usable_fb_size(self) -> u64 { + u64::from(self.value()) * kernel::sizes::SZ_1M as u64 + } +} + +/* PDISP */ + +register!(NV_PDISP_VGA_WORKSPACE_BASE @ 0x00625f04 { + 3:3 status_valid as bool, "Set if the `addr` field is valid"; + 31:8 addr as u32, "VGA workspace base address divided by 0x10000"; +}); + +impl NV_PDISP_VGA_WORKSPACE_BASE { + /// Returns the base address of the VGA workspace, or `None` if none e= xists. + pub(crate) fn vga_workspace_addr(self) -> Option { + if self.status_valid() { + Some((self.addr() as u64) << 16) + } else { + None + } + } +} + /* FUSE */ =20 register!(NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION @ 0x00824100 { @@ -218,3 +275,22 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { 4:4 core_select as bool =3D> PeregrineCoreSelect; 8:8 br_fetch as bool; }); + +// The modules below provide registers that are not identical on all suppo= rted chips. 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Add a couple of types and traits that sub-modules can use to implement this behavior, while ensuring that the correct kind of signature is applied to the firmware. Reviewed-by: Lyude Paul Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/firmware.rs | 64 +++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 64 insertions(+) diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index e5583925cb3b4353b521c68175f8cf0c2d6ce830..32553b5142d6623bdaaa9d480fb= ff11069198606 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -3,11 +3,15 @@ //! Contains structures and functions dedicated to the parsing, building a= nd patching of firmwares //! to be loaded into a given execution unit. =20 +use core::marker::PhantomData; + use kernel::device; use kernel::firmware; use kernel::prelude::*; use kernel::str::CString; =20 +use crate::dma::DmaObject; +use crate::falcon::FalconFirmware; use crate::gpu; use crate::gpu::Chipset; =20 @@ -84,6 +88,66 @@ pub(crate) fn size(&self) -> usize { } } =20 +/// Trait implemented by types defining the signed state of a firmware. +trait SignedState {} + +/// Type indicating that the firmware must be signed before it can be used. +struct Unsigned; +impl SignedState for Unsigned {} + +/// Type indicating that the firmware is signed and ready to be loaded. +struct Signed; +impl SignedState for Signed {} + +/// A [`DmaObject`] containing a specific microcode ready to be loaded int= o a falcon. +/// +/// This is module-local and meant for sub-modules to use internally. +/// +/// After construction, a firmware is [`Unsigned`], and must generally be = patched with a signature +/// before it can be loaded (with an exception for development hardware). = The +/// [`Self::patch_signature`] and [`Self::no_patch_signature`] methods are= used to transition the +/// firmware to its [`Signed`] state. +struct FirmwareDmaObject(DmaObject, Pha= ntomData<(F, S)>); + +/// Trait for signatures to be patched directly into a given firmware. +/// +/// This is module-local and meant for sub-modules to use internally. +trait FirmwareSignature: AsRef<[u8]> {} + +#[expect(unused)] +impl FirmwareDmaObject { + /// Patches the firmware at offset `sig_base_img` with `signature`. + fn patch_signature>( + mut self, + signature: &S, + sig_base_img: usize, + ) -> Result> { + let signature_bytes =3D signature.as_ref(); + if sig_base_img + signature_bytes.len() > self.0.size() { + return Err(EINVAL); + } + + // SAFETY: we are the only user of this object, so there cannot be= any race. + let dst =3D unsafe { self.0.start_ptr_mut().add(sig_base_img) }; + + // SAFETY: `signature` and `dst` are valid, properly aligned, and = do not overlap. + unsafe { + core::ptr::copy_nonoverlapping(signature_bytes.as_ptr(), dst, = signature_bytes.len()) + }; + + Ok(FirmwareDmaObject(self.0, PhantomData)) + } + + /// Mark the firmware as signed without patching it. + /// + /// This method is used to explicitly confirm that we do not need to s= ign the firmware, while + /// allowing us to continue as if it was. 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Do this so we are ready to load and run this firmware into the GSP falcon and create the FRTS region. [joelagnelf@nvidia.com: give better names to FalconAppifHdrV1's fields] Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/dma.rs | 3 - drivers/gpu/nova-core/firmware.rs | 3 +- drivers/gpu/nova-core/firmware/fwsec.rs | 398 ++++++++++++++++++++++++++++= ++++ drivers/gpu/nova-core/gpu.rs | 15 +- drivers/gpu/nova-core/vbios.rs | 30 ++- 5 files changed, 434 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/nova-core/dma.rs b/drivers/gpu/nova-core/dma.rs index 4b063aaef65ec4e2f476fc5ce9dc25341b6660ca..1f1f8c378d8e2cf51edc772e7af= e392e9c9c8831 100644 --- a/drivers/gpu/nova-core/dma.rs +++ b/drivers/gpu/nova-core/dma.rs @@ -2,9 +2,6 @@ =20 //! Simple DMA object wrapper. =20 -// To be removed when all code is used. -#![expect(dead_code)] - use core::ops::{Deref, DerefMut}; =20 use kernel::device; diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index 32553b5142d6623bdaaa9d480fbff11069198606..ae449a98dffb51e400db058c736= 8f0632b62f147 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -15,6 +15,8 @@ use crate::gpu; use crate::gpu::Chipset; =20 +pub(crate) mod fwsec; + pub(crate) const FIRMWARE_VERSION: &str =3D "535.113.01"; =20 /// Structure encapsulating the firmware blobs required for the GPU to ope= rate. @@ -114,7 +116,6 @@ impl SignedState for Signed {} /// This is module-local and meant for sub-modules to use internally. trait FirmwareSignature: AsRef<[u8]> {} =20 -#[expect(unused)] impl FirmwareDmaObject { /// Patches the firmware at offset `sig_base_img` with `signature`. fn patch_signature>( diff --git a/drivers/gpu/nova-core/firmware/fwsec.rs b/drivers/gpu/nova-cor= e/firmware/fwsec.rs new file mode 100644 index 0000000000000000000000000000000000000000..de179c2011396fa789e868ec564= b09eb48aa07ff --- /dev/null +++ b/drivers/gpu/nova-core/firmware/fwsec.rs @@ -0,0 +1,398 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! FWSEC is a High Secure firmware that is extracted from the BIOS and pe= rforms the first step of +//! the GSP startup by creating the WPR2 memory region and copying critica= l areas of the VBIOS into +//! it after authenticating them, ensuring they haven't been tampered with= . It runs on the GSP +//! falcon. +//! +//! Before being run, it needs to be patched in two areas: +//! +//! - The command to be run, as this firmware can perform several tasks ; +//! - The ucode signature, so the GSP falcon can run FWSEC in HS mode. + +use core::marker::PhantomData; +use core::mem::{align_of, size_of}; +use core::ops::Deref; + +use kernel::device::{self, Device}; +use kernel::prelude::*; +use kernel::transmute::FromBytes; + +use crate::dma::DmaObject; +use crate::driver::Bar0; +use crate::falcon::gsp::Gsp; +use crate::falcon::{Falcon, FalconBromParams, FalconFirmware, FalconLoadPa= rams, FalconLoadTarget}; +use crate::firmware::{FalconUCodeDescV3, FirmwareDmaObject, FirmwareSignat= ure, Signed, Unsigned}; +use crate::vbios::Vbios; + +const NVFW_FALCON_APPIF_ID_DMEMMAPPER: u32 =3D 0x4; + +#[repr(C)] +#[derive(Debug)] +struct FalconAppifHdrV1 { + version: u8, + header_size: u8, + entry_size: u8, + entry_count: u8, +} +// SAFETY: any byte sequence is valid for this struct. +unsafe impl FromBytes for FalconAppifHdrV1 {} + +#[repr(C, packed)] +#[derive(Debug)] +struct FalconAppifV1 { + id: u32, + dmem_base: u32, +} +// SAFETY: any byte sequence is valid for this struct. +unsafe impl FromBytes for FalconAppifV1 {} + +#[derive(Debug)] +#[repr(C, packed)] +struct FalconAppifDmemmapperV3 { + signature: u32, + version: u16, + size: u16, + cmd_in_buffer_offset: u32, + cmd_in_buffer_size: u32, + cmd_out_buffer_offset: u32, + cmd_out_buffer_size: u32, + nvf_img_data_buffer_offset: u32, + nvf_img_data_buffer_size: u32, + printf_buffer_hdr: u32, + ucode_build_time_stamp: u32, + ucode_signature: u32, + init_cmd: u32, + ucode_feature: u32, + ucode_cmd_mask0: u32, + ucode_cmd_mask1: u32, + multi_tgt_tbl: u32, +} +// SAFETY: any byte sequence is valid for this struct. +unsafe impl FromBytes for FalconAppifDmemmapperV3 {} + +#[derive(Debug)] +#[repr(C, packed)] +struct ReadVbios { + ver: u32, + hdr: u32, + addr: u64, + size: u32, + flags: u32, +} +// SAFETY: any byte sequence is valid for this struct. +unsafe impl FromBytes for ReadVbios {} + +#[derive(Debug)] +#[repr(C, packed)] +struct FrtsRegion { + ver: u32, + hdr: u32, + addr: u32, + size: u32, + ftype: u32, +} +// SAFETY: any byte sequence is valid for this struct. +unsafe impl FromBytes for FrtsRegion {} + +const NVFW_FRTS_CMD_REGION_TYPE_FB: u32 =3D 2; + +#[repr(C, packed)] +struct FrtsCmd { + read_vbios: ReadVbios, + frts_region: FrtsRegion, +} +// SAFETY: any byte sequence is valid for this struct. +unsafe impl FromBytes for FrtsCmd {} + +const NVFW_FALCON_APPIF_DMEMMAPPER_CMD_FRTS: u32 =3D 0x15; +const NVFW_FALCON_APPIF_DMEMMAPPER_CMD_SB: u32 =3D 0x19; + +/// Command for the [`FwsecFirmware`] to execute. +pub(crate) enum FwsecCommand { + /// Asks [`FwsecFirmware`] to carve out the WPR2 area and place a veri= fied copy of the VBIOS + /// image into it. + Frts { frts_addr: u64, frts_size: u64 }, + /// Asks [`FwsecFirmware`] to load pre-OS apps on the PMU. + #[expect(dead_code)] + Sb, +} + +/// Size of the signatures used in FWSEC. +const BCRT30_RSA3K_SIG_SIZE: usize =3D 384; + +/// A single signature that can be patched into a FWSEC image. +#[repr(transparent)] +pub(crate) struct Bcrt30Rsa3kSignature([u8; BCRT30_RSA3K_SIG_SIZE]); + +/// SAFETY: A signature is just an array of bytes. +unsafe impl FromBytes for Bcrt30Rsa3kSignature {} + +impl From<[u8; BCRT30_RSA3K_SIG_SIZE]> for Bcrt30Rsa3kSignature { + fn from(sig: [u8; BCRT30_RSA3K_SIG_SIZE]) -> Self { + Self(sig) + } +} + +impl AsRef<[u8]> for Bcrt30Rsa3kSignature { + fn as_ref(&self) -> &[u8] { + &self.0 + } +} + +impl FirmwareSignature for Bcrt30Rsa3kSignature {} + +/// Reinterpret the area starting from `offset` in `fw` as an instance of = `T` (which must implement +/// [`FromBytes`]) and return a reference to it. +/// +/// # Safety +/// +/// Callers must ensure that the region of memory returned is not written = for as long as the +/// returned reference is alive. +/// +/// TODO: Remove this and `transmute_mut` once `CoherentAllocation::as_sli= ce` is available and we +/// have a way to transmute objects implementing FromBytes, e.g.: +/// https://lore.kernel.org/lkml/20250330234039.29814-1-christiansantoslim= a21@gmail.com/ +unsafe fn transmute<'a, 'b, T: Sized + FromBytes>( + fw: &'a DmaObject, + offset: usize, +) -> Result<&'b T> { + if offset + size_of::() > fw.size() { + return Err(EINVAL); + } + if (fw.start_ptr() as usize + offset) % align_of::() !=3D 0 { + return Err(EINVAL); + } + + // SAFETY: we have checked that the pointer is properly aligned that i= ts pointed memory is + // large enough the contains an instance of `T`, which implements `Fro= mBytes`. + Ok(unsafe { &*(fw.start_ptr().add(offset).cast::()) }) +} + +/// Reinterpret the area starting from `offset` in `fw` as a mutable insta= nce of `T` (which must +/// implement [`FromBytes`]) and return a reference to it. +/// +/// # Safety +/// +/// Callers must ensure that the region of memory returned is not read or = written for as long as +/// the returned reference is alive. +unsafe fn transmute_mut<'a, 'b, T: Sized + FromBytes>( + fw: &'a mut DmaObject, + offset: usize, +) -> Result<&'b mut T> { + if offset + size_of::() > fw.size() { + return Err(EINVAL); + } + if (fw.start_ptr_mut() as usize + offset) % align_of::() !=3D 0 { + return Err(EINVAL); + } + + // SAFETY: we have checked that the pointer is properly aligned that i= ts pointed memory is + // large enough the contains an instance of `T`, which implements `Fro= mBytes`. + Ok(unsafe { &mut *(fw.start_ptr_mut().add(offset).cast::()) }) +} + +/// The FWSEC microcode, extracted from the BIOS and to be run on the GSP = falcon. +/// +/// It is responsible for e.g. carving out the WPR2 region as the first st= ep of the GSP bootflow. +pub(crate) struct FwsecFirmware { + /// Descriptor of the firmware. + desc: FalconUCodeDescV3, + /// GPU-accessible DMA object containing the firmware. + ucode: FirmwareDmaObject, +} + +// We need to load full DMEM pages. +const DMEM_LOAD_SIZE_ALIGN: u32 =3D 256; + +impl FalconLoadParams for FwsecFirmware { + fn imem_load_params(&self) -> FalconLoadTarget { + FalconLoadTarget { + src_start: 0, + dst_start: self.desc.imem_phys_base, + len: self.desc.imem_load_size, + } + } + + fn dmem_load_params(&self) -> FalconLoadTarget { + FalconLoadTarget { + src_start: self.desc.imem_load_size, + dst_start: self.desc.dmem_phys_base, + // TODO: replace with `align_up` once it lands. + len: self + .desc + .dmem_load_size + .next_multiple_of(DMEM_LOAD_SIZE_ALIGN), + } + } + + fn brom_params(&self) -> FalconBromParams { + FalconBromParams { + pkc_data_offset: self.desc.pkc_data_offset, + engine_id_mask: self.desc.engine_id_mask, + ucode_id: self.desc.ucode_id, + } + } + + fn boot_addr(&self) -> u32 { + 0 + } +} + +impl Deref for FwsecFirmware { + type Target =3D DmaObject; + + fn deref(&self) -> &Self::Target { + &self.ucode.0 + } +} + +impl FalconFirmware for FwsecFirmware { + type Target =3D Gsp; +} + +impl FirmwareDmaObject { + fn new_fwsec(dev: &Device, bios: &Vbios, cmd: FwsecComm= and) -> Result { + let desc =3D bios.fwsec_image().header(dev)?; + let ucode =3D bios.fwsec_image().ucode(dev, desc)?; + let mut dma_object =3D DmaObject::from_data(dev, ucode)?; + + let hdr_offset =3D (desc.imem_load_size + desc.interface_offset) a= s usize; + // SAFETY: we have exclusive access to `dma_object`. + let hdr: &FalconAppifHdrV1 =3D unsafe { transmute(&dma_object, hdr= _offset) }?; + + if hdr.version !=3D 1 { + return Err(EINVAL); + } + + // Find the DMEM mapper section in the firmware. + for i in 0..hdr.entry_count as usize { + let app: &FalconAppifV1 =3D + // SAFETY: we have exclusive access to `dma_object`. + unsafe { + transmute( + &dma_object, + hdr_offset + hdr.header_size as usize + i * hdr.entry_= size as usize + ) + }?; + + if app.id !=3D NVFW_FALCON_APPIF_ID_DMEMMAPPER { + continue; + } + + // SAFETY: we have exclusive access to `dma_object`. + let dmem_mapper: &mut FalconAppifDmemmapperV3 =3D unsafe { + transmute_mut( + &mut dma_object, + (desc.imem_load_size + app.dmem_base) as usize, + ) + }?; + + // SAFETY: we have exclusive access to `dma_object`. + let frts_cmd: &mut FrtsCmd =3D unsafe { + transmute_mut( + &mut dma_object, + (desc.imem_load_size + dmem_mapper.cmd_in_buffer_offse= t) as usize, + ) + }?; + + frts_cmd.read_vbios =3D ReadVbios { + ver: 1, + hdr: size_of::() as u32, + addr: 0, + size: 0, + flags: 2, + }; + + dmem_mapper.init_cmd =3D match cmd { + FwsecCommand::Frts { + frts_addr, + frts_size, + } =3D> { + frts_cmd.frts_region =3D FrtsRegion { + ver: 1, + hdr: size_of::() as u32, + addr: (frts_addr >> 12) as u32, + size: (frts_size >> 12) as u32, + ftype: NVFW_FRTS_CMD_REGION_TYPE_FB, + }; + + NVFW_FALCON_APPIF_DMEMMAPPER_CMD_FRTS + } + FwsecCommand::Sb =3D> NVFW_FALCON_APPIF_DMEMMAPPER_CMD_SB, + }; + + // Return early as we found and patched the DMEMMAPPER region. + return Ok(Self(dma_object, PhantomData)); + } + + Err(ENOTSUPP) + } +} + +impl FwsecFirmware { + /// Extract the Fwsec firmware from `bios` and patch it to run on `fal= con` with the `cmd` + /// command. + pub(crate) fn new( + dev: &Device, + falcon: &Falcon, + bar: &Bar0, + bios: &Vbios, + cmd: FwsecCommand, + ) -> Result { + let ucode_dma =3D FirmwareDmaObject::::new_fwsec(dev, bio= s, cmd)?; + + // Patch signature if needed. + let desc =3D bios.fwsec_image().header(dev)?; + let ucode_signed =3D if desc.signature_count !=3D 0 { + let sig_base_img =3D (desc.imem_load_size + desc.pkc_data_offs= et) as usize; + let desc_sig_versions =3D desc.signature_versions as u32; + let reg_fuse_version =3D + falcon.signature_reg_fuse_version(bar, desc.engine_id_mask= , desc.ucode_id)?; + dev_dbg!( + dev, + "desc_sig_versions: {:#x}, reg_fuse_version: {}\n", + desc_sig_versions, + reg_fuse_version + ); + let signature_idx =3D { + let reg_fuse_version_bit =3D 1 << reg_fuse_version; + + // Check if the fuse version is supported by the firmware. + if desc_sig_versions & reg_fuse_version_bit =3D=3D 0 { + dev_err!( + dev, + "no matching signature: {:#x} {:#x}\n", + reg_fuse_version_bit, + desc_sig_versions, + ); + return Err(EINVAL); + } + + // `desc_sig_versions` has one bit set per included signat= ure. Thus, the index of + // the signature to patch is the number of bits in `desc_s= ig_versions` set to `1` + // before `reg_fuse_version_bit`. + + // Mask of the bits of `desc_sig_versions` to preserve. + let reg_fuse_version_mask =3D reg_fuse_version_bit.wrappin= g_sub(1); + + (desc_sig_versions & reg_fuse_version_mask).count_ones() a= s usize + }; + + dev_dbg!(dev, "patching signature with index {}\n", signature_= idx); + let signature =3D bios + .fwsec_image() + .sigs(dev, desc) + .and_then(|sigs| sigs.get(signature_idx).ok_or(EINVAL))?; + + ucode_dma.patch_signature(signature, sig_base_img)? + } else { + ucode_dma.no_patch_signature() + }; + + Ok(FwsecFirmware { + desc: desc.clone(), + ucode: ucode_signed, + }) + } +} diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 413f1ab85b37926cdfd9a9c76167816b21d89adc..ba926162c1a016f7e1c88da5030= 8fb0a8686924a 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -6,6 +6,7 @@ use crate::falcon::{gsp::Gsp, sec2::Sec2, Falcon}; use crate::fb::FbLayout; use crate::fb::SysmemFlush; +use crate::firmware::fwsec::{FwsecCommand, FwsecFirmware}; use crate::firmware::{Firmware, FIRMWARE_VERSION}; use crate::gfw; use crate::regs; @@ -223,8 +224,18 @@ pub(crate) fn new( let fb_layout =3D FbLayout::new(spec.chipset, bar)?; dev_dbg!(pdev.as_ref(), "{:#x?}\n", fb_layout); =20 - // Will be used in a later patch when fwsec firmware is needed. - let _bios =3D Vbios::new(pdev, bar)?; + let bios =3D Vbios::new(pdev, bar)?; + + let _fwsec_frts =3D FwsecFirmware::new( + pdev.as_ref(), + &gsp_falcon, + bar, + &bios, + FwsecCommand::Frts { + frts_addr: fb_layout.frts.start, + frts_size: fb_layout.frts.end - fb_layout.frts.start, + }, + )?; =20 Ok(pin_init!(Self { spec, diff --git a/drivers/gpu/nova-core/vbios.rs b/drivers/gpu/nova-core/vbios.rs index 0149621dca1aaea5b342ff32e4701de49e988839..c029c600b9b3081ad1e1dd4112a= cd4ed914e9d8d 100644 --- a/drivers/gpu/nova-core/vbios.rs +++ b/drivers/gpu/nova-core/vbios.rs @@ -2,10 +2,8 @@ =20 //! VBIOS extraction and parsing. =20 -// To be removed when all code is used. -#![expect(dead_code)] - use crate::driver::Bar0; +use crate::firmware::fwsec::Bcrt30Rsa3kSignature; use crate::firmware::FalconUCodeDescV3; use core::convert::TryFrom; use kernel::device; @@ -1124,15 +1122,18 @@ pub(crate) fn ucode(&self, dev: &device::Device, de= sc: &FalconUCodeDescV3) -> Re } =20 /// Get the signatures as a byte slice - pub(crate) fn sigs(&self, dev: &device::Device, desc: &FalconUCodeDesc= V3) -> Result<&[u8]> { - const SIG_SIZE: usize =3D 96 * 4; - + pub(crate) fn sigs( + &self, + dev: &device::Device, + desc: &FalconUCodeDescV3, + ) -> Result<&[Bcrt30Rsa3kSignature]> { // The signatures data follows the descriptor let sigs_data_offset =3D self.falcon_ucode_offset + core::mem::siz= e_of::(); - let size =3D desc.signature_count as usize * SIG_SIZE; + let sigs_size =3D + desc.signature_count as usize * core::mem::size_of::(); =20 // Make sure the data is within bounds - if sigs_data_offset + size > self.base.data.len() { + if sigs_data_offset + sigs_size > self.base.data.len() { dev_err!( dev, "fwsec signatures data not contained within BIOS bounds\n" @@ -1140,6 +1141,17 @@ pub(crate) fn sigs(&self, dev: &device::Device, desc= : &FalconUCodeDescV3) -> Res return Err(ERANGE); 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Reviewed-by: Lyude Paul Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/falcon.rs | 3 -- drivers/gpu/nova-core/firmware/fwsec.rs | 25 +++++++++ drivers/gpu/nova-core/gpu.rs | 90 +++++++++++++++++++++++++++++= ---- drivers/gpu/nova-core/regs.rs | 31 ++++++++++++ 4 files changed, 136 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon= .rs index ba14cb24b80db89901191000a617bee683cbc060..fe4d3d458a6b105bfdd6257111d= 3eed8ed8aba7c 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -2,9 +2,6 @@ =20 //! Falcon microprocessor base support =20 -// To be removed when all code is used. -#![expect(dead_code)] - use core::ops::Deref; use core::time::Duration; use hal::FalconHal; diff --git a/drivers/gpu/nova-core/firmware/fwsec.rs b/drivers/gpu/nova-cor= e/firmware/fwsec.rs index de179c2011396fa789e868ec564b09eb48aa07ff..6058598ce76e25484cc4ebebd1b= e80b9dd1b469c 100644 --- a/drivers/gpu/nova-core/firmware/fwsec.rs +++ b/drivers/gpu/nova-core/firmware/fwsec.rs @@ -395,4 +395,29 @@ pub(crate) fn new( ucode: ucode_signed, }) } + + /// Loads the FWSEC firmware into `falcon` and execute it. + pub(crate) fn run( + &self, + dev: &Device, + falcon: &Falcon, + bar: &Bar0, + ) -> Result<()> { + // Reset falcon, load the firmware, and run it. + falcon + .reset(bar) + .inspect_err(|e| dev_err!(dev, "Failed to reset GSP falcon: {:= ?}\n", e))?; + falcon + .dma_load(bar, self) + .inspect_err(|e| dev_err!(dev, "Failed to load FWSEC firmware:= {:?}\n", e))?; + let (mbox0, _) =3D falcon + .boot(bar, Some(0), None) + .inspect_err(|e| dev_err!(dev, "Failed to boot FWSEC firmware:= {:?}\n", e))?; + if mbox0 !=3D 0 { + dev_err!(dev, "FWSEC firmware returned error {}\n", mbox0); + Err(EIO) + } else { + Ok(()) + } + } } diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index ba926162c1a016f7e1c88da50308fb0a8686924a..ae454c0e2fb4d485e99fbf9cd80= c2ebb89884887 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -188,6 +188,85 @@ fn drop(mut self: Pin<&mut Self>) { } =20 impl Gpu { + /// Helper function to load and run the FWSEC-FRTS firmware and confir= m that it has properly + /// created the WPR2 region. + /// + /// TODO: this needs to be moved into a larger type responsible for bo= oting the whole GSP + /// (`GspBooter`?). + fn run_fwsec_frts( + dev: &device::Device, + falcon: &Falcon, + bar: &Bar0, + bios: &Vbios, + fb_layout: &FbLayout, + ) -> Result<()> { + // Check that the WPR2 region does not already exists - if it does= , we cannot run + // FWSEC-FRTS until the GPU is reset. + if regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI::read(bar).higher_bound() != =3D 0 { + dev_err!( + dev, + "WPR2 region already exists - GPU needs to be reset to pro= ceed\n" + ); + return Err(EBUSY); + } + + let fwsec_frts =3D FwsecFirmware::new( + dev, + falcon, + bar, + bios, + FwsecCommand::Frts { + frts_addr: fb_layout.frts.start, + frts_size: fb_layout.frts.end - fb_layout.frts.start, + }, + )?; + + // Run FWSEC-FRTS to create the WPR2 region. + fwsec_frts.run(dev, falcon, bar)?; + + // SCRATCH_E contains the error code for FWSEC-FRTS. + let frts_status =3D regs::NV_PBUS_SW_SCRATCH_0E::read(bar).frts_er= r_code(); + if frts_status !=3D 0 { + dev_err!( + dev, + "FWSEC-FRTS returned with error code {:#x}", + frts_status + ); + + return Err(EIO); + } + + // Check that the WPR2 region has been created as we requested. + let (wpr2_lo, wpr2_hi) =3D ( + regs::NV_PFB_PRI_MMU_WPR2_ADDR_LO::read(bar).lower_bound(), + regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI::read(bar).higher_bound(), + ); + + match (wpr2_lo, wpr2_hi) { + (_, 0) =3D> { + dev_err!(dev, "WPR2 region not created after running FWSEC= -FRTS\n"); + + Err(EIO) + } + (wpr2_lo, _) if wpr2_lo !=3D fb_layout.frts.start =3D> { + dev_err!( + dev, + "WPR2 region created at unexpected address {:#x}; expe= cted {:#x}\n", + wpr2_lo, + fb_layout.frts.start, + ); + + Err(EIO) + } + (wpr2_lo, wpr2_hi) =3D> { + dev_dbg!(dev, "WPR2: {:#x}-{:#x}\n", wpr2_lo, wpr2_hi); + dev_dbg!(dev, "GPU instance built\n"); + + Ok(()) + } + } + } + pub(crate) fn new( pdev: &pci::Device, devres_bar: Devres, @@ -226,16 +305,7 @@ pub(crate) fn new( =20 let bios =3D Vbios::new(pdev, bar)?; =20 - let _fwsec_frts =3D FwsecFirmware::new( - pdev.as_ref(), - &gsp_falcon, - bar, - &bios, - FwsecCommand::Frts { - frts_addr: fb_layout.frts.start, - frts_size: fb_layout.frts.end - fb_layout.frts.start, - }, - )?; + Self::run_fwsec_frts(pdev.as_ref(), &gsp_falcon, bar, &bios, &fb_l= ayout)?; =20 Ok(pin_init!(Self { spec, diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 8ca7bcb5a93f4b60ee9ee488f26469af48e2f1d8..ccfaeed55cff90e66ac0acf37dc= bd0eb344994c5 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -42,6 +42,13 @@ pub(crate) fn chipset(self) -> Result { } } =20 +/* PBUS */ + +// TODO: this is an array of registers. +register!(NV_PBUS_SW_SCRATCH_0E@0x00001438 { + 31:16 frts_err_code as u16; +}); + /* PFB */ =20 register!(NV_PFB_NISO_FLUSH_SYSMEM_ADDR @ 0x00100c10 { @@ -73,6 +80,30 @@ pub(crate) fn usable_fb_size(self) -> u64 { } } =20 +register!(NV_PFB_PRI_MMU_WPR2_ADDR_LO@0x001fa824 { + 31:4 lo_val as u32, "Bits 12..40 of the lower (inclusive) bound of = the WPR2 region"; +}); + +impl NV_PFB_PRI_MMU_WPR2_ADDR_LO { + /// Returns the lower (inclusive) bound of the WPR2 region. + pub(crate) fn lower_bound(self) -> u64 { + (self.lo_val() as u64) << 12 + } +} + +register!(NV_PFB_PRI_MMU_WPR2_ADDR_HI@0x001fa828 { + 31:4 hi_val as u32, "Bits 12..40 of the higher (exclusive) bound of= the WPR2 region"; +}); + +impl NV_PFB_PRI_MMU_WPR2_ADDR_HI { + /// Returns the higher (exclusive) bound of the WPR2 region. + /// + /// A value of zero means the WPR2 region is not set. + pub(crate) fn higher_bound(self) -> u64 { + (self.hi_val() as u64) << 12 + } +} + /* PGC6 */ =20 register!(NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK @ 0x00118128= { --=20 2.49.0 From nobody Fri Dec 19 02:53:47 2025 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2063.outbound.protection.outlook.com [40.107.92.63]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9B86273D7E; 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Some items have also become obsolete: - The auxiliary bus abstractions have been implemented and are in use, - The ELF utilities are not considered for being part of the core kernel bindings anymore. - VBIOS, falcon and GPU timer have been completed. We now have quite a few TODO entries in the code, so annotate them with a 4 letter code representing the corresponding task in `todo.rst`. This allows to easily find which part of the code corresponds to a given entry (and conversely). Signed-off-by: Alexandre Courbot --- Documentation/gpu/nova/core/todo.rst | 107 ++++++++++++++++----------= ---- drivers/gpu/nova-core/dma.rs | 2 +- drivers/gpu/nova-core/driver.rs | 2 +- drivers/gpu/nova-core/falcon.rs | 8 ++- drivers/gpu/nova-core/falcon/hal/ga102.rs | 10 +-- drivers/gpu/nova-core/fb.rs | 2 +- drivers/gpu/nova-core/firmware/fwsec.rs | 6 +- drivers/gpu/nova-core/gfw.rs | 2 +- drivers/gpu/nova-core/gpu.rs | 2 +- drivers/gpu/nova-core/regs.rs | 8 +-- drivers/gpu/nova-core/regs/macros.rs | 2 +- drivers/gpu/nova-core/util.rs | 2 +- drivers/gpu/nova-core/vbios.rs | 2 +- 13 files changed, 84 insertions(+), 71 deletions(-) diff --git a/Documentation/gpu/nova/core/todo.rst b/Documentation/gpu/nova/= core/todo.rst index 8a459fc088121f770bfcda5dfb4ef51c712793ce..894a1e9c3741a43ad4eb76d24a9= 486862999874e 100644 --- a/Documentation/gpu/nova/core/todo.rst +++ b/Documentation/gpu/nova/core/todo.rst @@ -14,14 +14,17 @@ Tasks may have the following fields: - ``Contact``: The person that can be contacted for further information ab= out the task. =20 +A task might have `[ABCD]` code after its name. This code can be used to g= rep +into the code for `TODO` entries related to it. + Enablement (Rust) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 Tasks that are not directly related to nova-core, but are preconditions in= terms of required APIs. =20 -FromPrimitive API ------------------ +FromPrimitive API [FPRI] +------------------------ =20 Sometimes the need arises to convert a number to a value of an enum or a structure. @@ -41,8 +44,27 @@ automatically generates the corresponding mappings betwe= en a value and a number. | Complexity: Beginner | Link: https://docs.rs/num/latest/num/trait.FromPrimitive.html =20 -Generic register abstraction ----------------------------- +Conversion from byte slices for types implementing FromBytes [TRSM] +------------------------------------------------------------------- + +We retrieve several structures from byte streams coming from the BIOS or l= oaded +firmware. At the moment converting the bytes slice into the proper type re= quire +an inelegant `unsafe` operation; this will go away once `FromBytes` implem= ents +a proper `from_bytes` method. + +| Complexity: Beginner + +CoherentAllocation improvements [COHA] +-------------------------------------- + +`CoherentAllocation` needs a safe way to write into the allocation, and to +obtain slices within the allocation. + +| Complexity: Beginner +| Contact: Abdiel Janulgue + +Generic register abstraction [REGA] +----------------------------------- =20 Work out how register constants and structures can be automatically genera= ted through generalized macros. @@ -102,16 +124,40 @@ Usage: let boot0 =3D Boot0::read(&bar); pr_info!("Revision: {}\n", boot0.revision()); =20 -Note: a work-in-progress implementation currently resides in +A work-in-progress implementation currently resides in `drivers/gpu/nova-core/regs/macros.rs` and is used in nova-core. It would = be nice to improve it (possibly using proc macros) and move it to the `kernel` crate so it can be used by other components as well. =20 +Features desired before this happens: + +* Relative register with build-time base address validation, +* Arrays of registers with build-time index validation, +* Make I/O optional I/O (for field values that are not registers), +* Support other sizes than `u32`, +* Allow visibility control for registers and individual fields, +* Use Rust slice syntax to express fields ranges. + | Complexity: Advanced | Contact: Alexandre Courbot =20 -Delay / Sleep abstractions --------------------------- +Numerical operations [NUMM] +--------------------------- + +Nova uses integer operations that are not part of the standard library (or= not +implemented in an optimized way for the kernel). These include: + +- Aligning up and down to a power of two, +- The "Find Last Set Bit" (`fls` function of the C part of the kernel) + operation. + +A `num` core kernel module is being designed to provide these operations. + +| Complexity: Intermediate +| Contact: Alexandre Courbot + +Delay / Sleep abstractions [DLAY] +--------------------------------- =20 Rust abstractions for the kernel's delay() and sleep() functions. =20 @@ -159,18 +205,6 @@ mailing list yet. | Complexity: Intermediate | Contact: Abdiel Janulgue =20 -ELF utils ---------- - -Rust implementation of ELF header representation to retrieve section header -tables, names, and data from an ELF-formatted images. - -There is preceding work from Abdiel Janulgue, which hasn't made it to the -mailing list yet. - -| Complexity: Beginner -| Contact: Abdiel Janulgue - PCI MISC APIs ------------- =20 @@ -179,12 +213,11 @@ capability, MSI API abstractions. =20 | Complexity: Beginner =20 -Auxiliary bus abstractions --------------------------- +XArray bindings [XARR] +---------------------- =20 -Rust abstraction for the auxiliary bus APIs. - -This is needed to connect nova-core to the nova-drm driver. +We need bindings for `xa_alloc`/`xa_alloc_cyclic` in order to generate the +auxiliary device IDs. =20 | Complexity: Intermediate =20 @@ -216,15 +249,6 @@ Build the radix3 page table to map the firmware. | Complexity: Intermediate | Contact: Abdiel Janulgue =20 -vBIOS support -------------- - -Parse the vBIOS and probe the structures required for driver initializatio= n. - -| Contact: Dave Airlie -| Reference: Vec extensions -| Complexity: Intermediate - Initial Devinit support ----------------------- =20 @@ -234,23 +258,6 @@ configuration. | Contact: Dave Airlie | Complexity: Beginner =20 -Boot Falcon controller ----------------------- - -Infrastructure to load and execute falcon (sec2) firmware images; handle t= he -GSP falcon processor and fwsec loading. - -| Complexity: Advanced -| Contact: Dave Airlie - -GPU Timer support ------------------ - -Support for the GPU's internal timer peripheral. - -| Complexity: Beginner -| Contact: Dave Airlie - MMU / PT management ------------------- =20 diff --git a/drivers/gpu/nova-core/dma.rs b/drivers/gpu/nova-core/dma.rs index 1f1f8c378d8e2cf51edc772e7afe392e9c9c8831..94f44bcfd748d18ea42c520e36a= 618bde9635e55 100644 --- a/drivers/gpu/nova-core/dma.rs +++ b/drivers/gpu/nova-core/dma.rs @@ -26,7 +26,7 @@ pub(crate) fn new(dev: &device::Device, le= n: usize) -> Result, data: &[u= 8]) -> Result { Self::new(dev, data.len()).map(|mut dma_obj| { - // TODO: replace with `CoherentAllocation::write()` once avail= able. + // TODO[COHA]: replace with `CoherentAllocation::write()` once= available. // SAFETY: // - `dma_obj`'s size is at least `data.len()`. // - We have just created this object and there is no other us= er at this stage. diff --git a/drivers/gpu/nova-core/driver.rs b/drivers/gpu/nova-core/driver= .rs index ffe25c7a2fdad289549460f7fd87d6e09299a35c..518ef8739550fd0b63b5a4aa98c= d1fd814770725 100644 --- a/drivers/gpu/nova-core/driver.rs +++ b/drivers/gpu/nova-core/driver.rs @@ -42,7 +42,7 @@ fn probe(pdev: &pci::Device, _info: &Self::IdInfo) = -> Result for FalconCoreRev { type Error =3D Error; =20 @@ -68,6 +69,7 @@ pub(crate) enum FalconCoreRevSubversion { Subversion3 =3D 3, } =20 +// TODO[FPRI]: replace with `FromPrimitive`. impl TryFrom for FalconCoreRevSubversion { type Error =3D Error; =20 @@ -101,6 +103,7 @@ pub(crate) enum FalconSecurityModel { Heavy =3D 3, } =20 +// TODO[FPRI]: replace with `FromPrimitive`. impl TryFrom for FalconSecurityModel { type Error =3D Error; =20 @@ -128,6 +131,7 @@ pub(crate) enum FalconModSelAlgo { Rsa3k =3D 1, } =20 +// TODO[FPRI]: replace with `FromPrimitive`. impl TryFrom for FalconModSelAlgo { type Error =3D Error; =20 @@ -148,6 +152,7 @@ pub(crate) enum DmaTrfCmdSize { Size256B =3D 0x6, } =20 +// TODO[FPRI]: replace with `FromPrimitive`. impl TryFrom for DmaTrfCmdSize { type Error =3D Error; =20 @@ -199,6 +204,7 @@ pub(crate) enum FalconFbifTarget { NoncoherentSysmem =3D 2, } =20 +// TODO[FPRI]: replace with `FromPrimitive`. impl TryFrom for FalconFbifTarget { type Error =3D Error; =20 @@ -354,7 +360,7 @@ fn reset_eng(&self, bar: &Bar0) -> Result { =20 regs::NV_PFALCON_FALCON_ENGINE::alter(bar, E::BASE, |v| v.set_rese= t(true)); =20 - // TODO: replace with udelay() or equivalent once available. + // TODO[DLAY]: replace with udelay() or equivalent once available. // TIMEOUT: falcon engine should not take more than 10us to reset. let _: Result =3D util::wait_on(Duration::from_micros(10), || None= ); =20 diff --git a/drivers/gpu/nova-core/falcon/hal/ga102.rs b/drivers/gpu/nova-c= ore/falcon/hal/ga102.rs index 0a4e5e7adf8cbcec9f67bb09ba758a9cb2887bae..664327f75cf4199cca37d22ca18= b2b9abac781f8 100644 --- a/drivers/gpu/nova-core/falcon/hal/ga102.rs +++ b/drivers/gpu/nova-core/falcon/hal/ga102.rs @@ -42,10 +42,10 @@ fn signature_reg_fuse_version_ga102( engine_id_mask: u16, ucode_id: u8, ) -> Result { - // TODO: The ucode fuse versions are contained in the FUSE_OPT_FPF__UCODE_VERSION - // registers, which are an array. Our register definition macros do no= t allow us to manage them - // properly, so we need to hardcode their addresses for now. Clean thi= s up once we support - // register arrays. + // TODO[REGA]: The ucode fuse versions are contained in the + // FUSE_OPT_FPF__UCODE_VERSION registers, which are an arra= y. Our register + // definition macros do not allow us to manage them properly, so we ne= ed to hardcode their + // addresses for now. Clean this up once we support register arrays. =20 // Each engine has 16 ucode version registers numbered from 1 to 16. if ucode_id =3D=3D 0 || ucode_id > 16 { @@ -69,7 +69,7 @@ fn signature_reg_fuse_version_ga102( let reg_fuse_version =3D bar.read32(reg_fuse_base + ((ucode_id - 1) as usize * core::mem::s= ize_of::())); =20 - // TODO: replace with `last_set_bit` once it lands. + // TODO[NUMM]: replace with `last_set_bit` once it lands. Ok(u32::BITS - reg_fuse_version.leading_zeros()) } =20 diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs index dc009a3ed44c2de7ffeb8cc0be06a72cf2ca5309..48003527a2472a4a8b784af0d48= 1a441c8d2426e 100644 --- a/drivers/gpu/nova-core/fb.rs +++ b/drivers/gpu/nova-core/fb.rs @@ -121,7 +121,7 @@ pub(crate) fn new(chipset: Chipset, bar: &Bar0) -> Resu= lt { let frts =3D { const FRTS_DOWN_ALIGN: u64 =3D SZ_128K as u64; const FRTS_SIZE: u64 =3D SZ_1M as u64; - // TODO: replace with `align_down` once it lands. + // TODO[NUMM]: replace with `align_down` once it lands. let frts_base =3D (vga_workspace.start & !(FRTS_DOWN_ALIGN - 1= )) - FRTS_SIZE; =20 frts_base..frts_base + FRTS_SIZE diff --git a/drivers/gpu/nova-core/firmware/fwsec.rs b/drivers/gpu/nova-cor= e/firmware/fwsec.rs index 6058598ce76e25484cc4ebebd1be80b9dd1b469c..047aab76470ecb0a0486f6917f6= fda69b5381391 100644 --- a/drivers/gpu/nova-core/firmware/fwsec.rs +++ b/drivers/gpu/nova-core/firmware/fwsec.rs @@ -150,8 +150,8 @@ impl FirmwareSignature for Bcrt30Rsa3kSi= gnature {} /// Callers must ensure that the region of memory returned is not written = for as long as the /// returned reference is alive. /// -/// TODO: Remove this and `transmute_mut` once `CoherentAllocation::as_sli= ce` is available and we -/// have a way to transmute objects implementing FromBytes, e.g.: +/// TODO[TRSM][COHA]: Remove this and `transmute_mut` once `CoherentAlloca= tion::as_slice` is +/// available and we have a way to transmute objects implementing FromByte= s, e.g.: /// https://lore.kernel.org/lkml/20250330234039.29814-1-christiansantoslim= a21@gmail.com/ unsafe fn transmute<'a, 'b, T: Sized + FromBytes>( fw: &'a DmaObject, @@ -218,7 +218,7 @@ fn dmem_load_params(&self) -> FalconLoadTarget { FalconLoadTarget { src_start: self.desc.imem_load_size, dst_start: self.desc.dmem_phys_base, - // TODO: replace with `align_up` once it lands. + // TODO[NUMM]: replace with `align_up` once it lands. len: self .desc .dmem_load_size diff --git a/drivers/gpu/nova-core/gfw.rs b/drivers/gpu/nova-core/gfw.rs index fa3f642bc814c7eea1ce1f2c2e24e684d1ae5fda..97fdd311a1f842c1c4e5c28d10b= b26066a7aa586 100644 --- a/drivers/gpu/nova-core/gfw.rs +++ b/drivers/gpu/nova-core/gfw.rs @@ -31,7 +31,7 @@ pub(crate) fn wait_gfw_boot_completion(bar: &Bar0) -> Res= ult { } else { // Avoid busy-looping. // SAFETY: msleep should be safe to call with any parameter. - // TODO: replace with [1] once it merges. + // TODO[DLAY]: replace with [1] once it merges. // [1] https://lore.kernel.org/rust-for-linux/20250423192857.1= 99712-6-fujita.tomonori@gmail.com/ unsafe { bindings::msleep(1) }; =20 diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index ae454c0e2fb4d485e99fbf9cd80c2ebb89884887..7a6ff6d89cb2a5e3176489e5455= 2d04633861ad6 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -37,7 +37,7 @@ impl Chipset { ]; } =20 - // TODO replace with something like derive(FromPrimitive) + // TODO[FPRI]: replace with something like derive(FromPrimitive) impl TryFrom for Chipset { type Error =3D kernel::error::Error; =20 diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index ccfaeed55cff90e66ac0acf37dcbd0eb344994c5..707f87d6828df54c959af87fd13= bbdd3a25aa020 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -44,7 +44,7 @@ pub(crate) fn chipset(self) -> Result { =20 /* PBUS */ =20 -// TODO: this is an array of registers. +// TODO[REGA]: this is an array of registers. register!(NV_PBUS_SW_SCRATCH_0E@0x00001438 { 31:16 frts_err_code as u16; }); @@ -110,7 +110,7 @@ pub(crate) fn higher_bound(self) -> u64 { 0:0 read_protection_level0 as bool, "Set after FWSEC lowers its pr= otection level"; }); =20 -// TODO: This is an array of registers. +// TODO[REGA]: This is an array of registers. register!(NV_PGC6_AON_SECURE_SCRATCH_GROUP_05 @ 0x00118234 { 31:0 value as u32; }); @@ -272,7 +272,7 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { 0:0 reset as bool; }); =20 -// TODO: this is an array of registers. +// TODO[REGA]: this is an array of registers. register!(NV_PFALCON_FBIF_TRANSCFG @ +0x00000600 { 1:0 target as u8 ?=3D> FalconFbifTarget; 2:2 mem_type as bool =3D> FalconFbifMemType; @@ -294,7 +294,7 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { 31:0 value as u32; }); =20 -// TODO: this is an array of registers. +// TODO[REGA]: this is an array of registers. register!(NV_PFALCON2_FALCON_BROM_PARAADDR @ +0x00001210 { 31:0 value as u32; }); diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/r= egs/macros.rs index e0e6fef3796f9dd2ce4e0223444a05bcc53075a6..cdf668073480ed703c89ffa8628= f5c9de6494687 100644 --- a/drivers/gpu/nova-core/regs/macros.rs +++ b/drivers/gpu/nova-core/regs/macros.rs @@ -147,7 +147,7 @@ impl $name { pub(crate) const OFFSET: usize =3D $offset; } =20 - // TODO: display the raw hex value, then the value of all the fiel= ds. This requires + // TODO[REGA]: display the raw hex value, then the value of all th= e fields. This requires // matching the fields, which will complexify the syntax considera= bly... impl ::core::fmt::Debug for $name { fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::f= mt::Result { diff --git a/drivers/gpu/nova-core/util.rs b/drivers/gpu/nova-core/util.rs index 69f29238b25ed949b00def1b748df3ff7567d83c..5cafe0797cd6f9567afb7e1e9af= 23b961a8a87f6 100644 --- a/drivers/gpu/nova-core/util.rs +++ b/drivers/gpu/nova-core/util.rs @@ -32,7 +32,7 @@ pub(crate) const fn const_bytes_to_str(bytes: &[u8]) -> &= str { /// `Err(ETIMEDOUT)` is returned if `timeout` has been reached without `co= nd` evaluating to /// `Some`. /// -/// TODO: replace with `read_poll_timeout` once it is available. +/// TODO[DLAY]: replace with `read_poll_timeout` once it is available. /// (https://lore.kernel.org/lkml/20250220070611.214262-8-fujita.tomonori@= gmail.com/) pub(crate) fn wait_on Option>(timeout: Duration, cond: F)= -> Result { let start_time =3D Instant::now(); diff --git a/drivers/gpu/nova-core/vbios.rs b/drivers/gpu/nova-core/vbios.rs index c029c600b9b3081ad1e1dd4112acd4ed914e9d8d..a5889eb149a16beabc0ddbdc876= 66520114c8aec 100644 --- a/drivers/gpu/nova-core/vbios.rs +++ b/drivers/gpu/nova-core/vbios.rs @@ -175,7 +175,7 @@ fn next(&mut self) -> Option { =20 // Advance to next image (aligned to 512 bytes) self.current_offset +=3D image_size; - // TODO: replace with `align_up` once it lands. + // TODO[NUMM]: replace with `align_up` once it lands. self.current_offset =3D self.current_offset.next_multiple_of(512); =20 Some(Ok(full_image)) --=20 2.49.0