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Thu, 19 Jun 2025 04:18:22 -0700 (PDT) From: Peter Griffin Date: Thu, 19 Jun 2025 12:18:15 +0100 Subject: [PATCH 1/2] pinctrl: samsung: rename exynosautov920_retention_data to no_retention_data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250619-gs101-eint-mask-v1-1-89438cfd7499@linaro.org> References: <20250619-gs101-eint-mask-v1-0-89438cfd7499@linaro.org> In-Reply-To: <20250619-gs101-eint-mask-v1-0-89438cfd7499@linaro.org> To: Krzysztof Kozlowski , Sylwester Nawrocki , Alim Akhtar , Linus Walleij , =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, kernel-team@android.com, William Mcvicker , Peter Griffin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2297; i=peter.griffin@linaro.org; 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The purpose of this for exynosautov920 and gs101 is to obtain the PMU syscon for writing the calculated WAKEUP_MASK register(s). Signed-off-by: Peter Griffin --- drivers/pinctrl/samsung/pinctrl-exynos-arm64.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinct= rl/samsung/pinctrl-exynos-arm64.c index 9fd894729a7b87c3e144ff90921a1cadbde93d3d..5fe7c4b9f7bd424f396082f1b1b= 16bfb65f26cdf 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -1405,7 +1405,7 @@ static const struct samsung_pin_bank_data exynosautov= 920_pin_banks7[] =3D { EXYNOSV920_PIN_BANK_EINTG(8, 0x8000, "gpg1", 0x18, 0x24, 0x28), }; =20 -static const struct samsung_retention_data exynosautov920_retention_data _= _initconst =3D { +static const struct samsung_retention_data no_retention_data __initconst = =3D { .regs =3D NULL, .nr_regs =3D 0, .value =3D 0, @@ -1421,7 +1421,7 @@ static const struct samsung_pin_ctrl exynosautov920_p= in_ctrl[] =3D { .eint_wkup_init =3D exynos_eint_wkup_init, .suspend =3D exynosautov920_pinctrl_suspend, .resume =3D exynosautov920_pinctrl_resume, - .retention_data =3D &exynosautov920_retention_data, + .retention_data =3D &no_retention_data, }, { /* pin-controller instance 1 AUD data */ .pin_banks =3D exynosautov920_pin_banks1, @@ -1764,6 +1764,7 @@ static const struct samsung_pin_ctrl gs101_pin_ctrl[]= __initconst =3D { .eint_wkup_init =3D exynos_eint_wkup_init, .suspend =3D gs101_pinctrl_suspend, .resume =3D gs101_pinctrl_resume, + .retention_data =3D &no_retention_data, }, { /* pin banks of gs101 pin-controller (FAR_ALIVE) */ .pin_banks =3D gs101_pin_far_alive, @@ -1771,6 +1772,7 @@ static const struct samsung_pin_ctrl gs101_pin_ctrl[]= __initconst =3D { .eint_wkup_init =3D exynos_eint_wkup_init, .suspend =3D gs101_pinctrl_suspend, .resume =3D gs101_pinctrl_resume, + .retention_data =3D &no_retention_data, }, { /* pin banks of gs101 pin-controller (GSACORE) */ .pin_banks =3D gs101_pin_gsacore, --=20 2.50.0.rc2.701.gf1e915cc24-goog From nobody Wed Dec 17 10:21:30 2025 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CB8B22655E for ; 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Thu, 19 Jun 2025 04:18:24 -0700 (PDT) Received: from gpeter-l.roam.corp.google.com ([145.224.65.219]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4535eac8c41sm25674375e9.26.2025.06.19.04.18.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jun 2025 04:18:23 -0700 (PDT) From: Peter Griffin Date: Thu, 19 Jun 2025 12:18:16 +0100 Subject: [PATCH 2/2] pinctrl: samsung: add support for gs101 wakeup mask programming Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250619-gs101-eint-mask-v1-2-89438cfd7499@linaro.org> References: <20250619-gs101-eint-mask-v1-0-89438cfd7499@linaro.org> In-Reply-To: <20250619-gs101-eint-mask-v1-0-89438cfd7499@linaro.org> To: Krzysztof Kozlowski , Sylwester Nawrocki , Alim Akhtar , Linus Walleij , =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, kernel-team@android.com, William Mcvicker , Peter Griffin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA gs101 differs to other currently supported SoCs in that it has 3 wakeup mask registers for the 67 external wakeup interrupt pins in alive and far_alive. EINT_WAKEUP_MASK 0x3A80 EINT[31:0] EINT_WAKEUP_MASK2 0x3A84 EINT[63:32] EINT_WAKEUP_MASK3 0x3A88 EINT[66:64] Add gs101 specific callbacks and a dedicated gs101_wkup_irq_chip struct to handle these differences. The current wakeup mask with upstream is programmed as WAKEUP_MASK0[0x3A80] value[0xFFFFFFFF] WAKEUP_MASK1[0x3A84] value[0xF2FFEFFF] WAKEUP_MASK2[0x3A88] value[0xFFFFFFFF] Which corresponds to the following wakeup sources: gpa7-3 vol down gpa8-1 vol up gpa10-1 power gpa8-2 typec-int Signed-off-by: Peter Griffin --- drivers/pinctrl/samsung/pinctrl-exynos.c | 100 ++++++++++++++++++++++++= ---- drivers/pinctrl/samsung/pinctrl-samsung.h | 4 ++ include/linux/soc/samsung/exynos-regs-pmu.h | 1 + 3 files changed, 91 insertions(+), 14 deletions(-) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/sam= sung/pinctrl-exynos.c index f3e1c11abe55032ee4ed7eb4db861dbb1e60c2bf..5554768d465fe0d8bf6e423b2e8= 35965cde5d8f5 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -32,18 +32,24 @@ #include "pinctrl-samsung.h" #include "pinctrl-exynos.h" =20 +#define MAX_WAKEUP_REG 3 + struct exynos_irq_chip { struct irq_chip chip; =20 u32 eint_con; u32 eint_mask; u32 eint_pend; - u32 *eint_wake_mask_value; + u32 eint_num_wakeup_reg; u32 eint_wake_mask_reg; void (*set_eint_wakeup_mask)(struct samsung_pinctrl_drv_data *drvdata, struct exynos_irq_chip *irq_chip); }; =20 +static u32 eint_wake_mask_values[MAX_WAKEUP_REG] =3D { EXYNOS_EINT_WAKEUP_= MASK_DISABLED, + EXYNOS_EINT_WAKEUP_MASK_DISABLED, + EXYNOS_EINT_WAKEUP_MASK_DISABLED}; + static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *= chip) { return container_of(chip, struct exynos_irq_chip, chip); @@ -307,7 +313,7 @@ static const struct exynos_irq_chip exynos_gpio_irq_chi= p __initconst =3D { .eint_con =3D EXYNOS_GPIO_ECON_OFFSET, .eint_mask =3D EXYNOS_GPIO_EMASK_OFFSET, .eint_pend =3D EXYNOS_GPIO_EPEND_OFFSET, - /* eint_wake_mask_value not used */ + /* eint_wake_mask_values not used */ }; =20 static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq, @@ -467,10 +473,55 @@ __init int exynos_eint_gpio_init(struct samsung_pinct= rl_drv_data *d) return ret; } =20 +#define BITS_PER_U32 32 +static int gs101_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on) +{ + struct samsung_pin_bank *bank =3D irq_data_get_irq_chip_data(irqd); + struct samsung_pinctrl_drv_data *d =3D bank->drvdata; + u32 bit, wakeup_reg, shift; + + bit =3D bank->eint_num + irqd->hwirq; + wakeup_reg =3D bit / BITS_PER_U32; + shift =3D bit - (wakeup_reg * BITS_PER_U32); + + if (!on) + eint_wake_mask_values[wakeup_reg] |=3D BIT_U32(shift); + else + eint_wake_mask_values[wakeup_reg] &=3D ~BIT_U32(shift); + + dev_info(d->dev, "wake %s for irq %d\n", str_enabled_disabled(on), + irqd->irq); + + return 0; +} + +static void +gs101_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data *drvdat= a, + struct exynos_irq_chip *irq_chip) +{ + struct regmap *pmu_regs; + + if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) { + dev_warn(drvdata->dev, + "No PMU syscon available. Wake-up mask will not be set.\n"); + return; + } + + pmu_regs =3D drvdata->retention_ctrl->priv; + + dev_dbg(drvdata->dev, "Setting external wakeup interrupt mask:\n"); + + for (int i =3D 0; i < irq_chip->eint_num_wakeup_reg; i++) { + dev_dbg(drvdata->dev, "\tWAKEUP_MASK%d[0x%X] value[0x%X]\n", + i, irq_chip->eint_wake_mask_reg + i * 4, + eint_wake_mask_values[i]); + regmap_write(pmu_regs, irq_chip->eint_wake_mask_reg + i * 4, + eint_wake_mask_values[i]); + } +} + static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on) { - struct irq_chip *chip =3D irq_data_get_irq_chip(irqd); - struct exynos_irq_chip *our_chip =3D to_exynos_irq_chip(chip); struct samsung_pin_bank *bank =3D irq_data_get_irq_chip_data(irqd); unsigned long bit =3D 1UL << (2 * bank->eint_offset + irqd->hwirq); =20 @@ -478,9 +529,9 @@ static int exynos_wkup_irq_set_wake(struct irq_data *ir= qd, unsigned int on) irqd->irq, bank->name, irqd->hwirq); =20 if (!on) - *our_chip->eint_wake_mask_value |=3D bit; + eint_wake_mask_values[0] |=3D bit; else - *our_chip->eint_wake_mask_value &=3D ~bit; + eint_wake_mask_values[0] &=3D ~bit; =20 return 0; } @@ -500,10 +551,10 @@ exynos_pinctrl_set_eint_wakeup_mask(struct samsung_pi= nctrl_drv_data *drvdata, pmu_regs =3D drvdata->retention_ctrl->priv; dev_info(drvdata->dev, "Setting external wakeup interrupt mask: 0x%x\n", - *irq_chip->eint_wake_mask_value); + eint_wake_mask_values[0]); =20 regmap_write(pmu_regs, irq_chip->eint_wake_mask_reg, - *irq_chip->eint_wake_mask_value); + eint_wake_mask_values[0]); } =20 static void @@ -522,11 +573,10 @@ s5pv210_pinctrl_set_eint_wakeup_mask(struct samsung_p= inctrl_drv_data *drvdata, =20 clk_base =3D (void __iomem *) drvdata->retention_ctrl->priv; =20 - __raw_writel(*irq_chip->eint_wake_mask_value, + __raw_writel(eint_wake_mask_values[0], clk_base + irq_chip->eint_wake_mask_reg); } =20 -static u32 eint_wake_mask_value =3D EXYNOS_EINT_WAKEUP_MASK_DISABLED; /* * irq_chip for wakeup interrupts */ @@ -544,7 +594,7 @@ static const struct exynos_irq_chip s5pv210_wkup_irq_ch= ip __initconst =3D { .eint_con =3D EXYNOS_WKUP_ECON_OFFSET, .eint_mask =3D EXYNOS_WKUP_EMASK_OFFSET, .eint_pend =3D EXYNOS_WKUP_EPEND_OFFSET, - .eint_wake_mask_value =3D &eint_wake_mask_value, + .eint_num_wakeup_reg =3D 1, /* Only differences with exynos4210_wkup_irq_chip: */ .eint_wake_mask_reg =3D S5PV210_EINT_WAKEUP_MASK, .set_eint_wakeup_mask =3D s5pv210_pinctrl_set_eint_wakeup_mask, @@ -564,7 +614,7 @@ static const struct exynos_irq_chip exynos4210_wkup_irq= _chip __initconst =3D { .eint_con =3D EXYNOS_WKUP_ECON_OFFSET, .eint_mask =3D EXYNOS_WKUP_EMASK_OFFSET, .eint_pend =3D EXYNOS_WKUP_EPEND_OFFSET, - .eint_wake_mask_value =3D &eint_wake_mask_value, + .eint_num_wakeup_reg =3D 1, .eint_wake_mask_reg =3D EXYNOS_EINT_WAKEUP_MASK, .set_eint_wakeup_mask =3D exynos_pinctrl_set_eint_wakeup_mask, }; @@ -583,7 +633,7 @@ static const struct exynos_irq_chip exynos7_wkup_irq_ch= ip __initconst =3D { .eint_con =3D EXYNOS7_WKUP_ECON_OFFSET, .eint_mask =3D EXYNOS7_WKUP_EMASK_OFFSET, .eint_pend =3D EXYNOS7_WKUP_EPEND_OFFSET, - .eint_wake_mask_value =3D &eint_wake_mask_value, + .eint_num_wakeup_reg =3D 1, .eint_wake_mask_reg =3D EXYNOS5433_EINT_WAKEUP_MASK, .set_eint_wakeup_mask =3D exynos_pinctrl_set_eint_wakeup_mask, }; @@ -599,13 +649,31 @@ static const struct exynos_irq_chip exynosautov920_wk= up_irq_chip __initconst =3D { .irq_request_resources =3D exynos_irq_request_resources, .irq_release_resources =3D exynos_irq_release_resources, }, - .eint_wake_mask_value =3D &eint_wake_mask_value, + .eint_num_wakeup_reg =3D 1, .eint_wake_mask_reg =3D EXYNOS5433_EINT_WAKEUP_MASK, .set_eint_wakeup_mask =3D exynos_pinctrl_set_eint_wakeup_mask, }; =20 +static const struct exynos_irq_chip gs101_wkup_irq_chip __initconst =3D { + .chip =3D { + .name =3D "gs101_wkup_irq_chip", + .irq_unmask =3D exynos_irq_unmask, + .irq_mask =3D exynos_irq_mask, + .irq_ack =3D exynos_irq_ack, + .irq_set_type =3D exynos_irq_set_type, + .irq_set_wake =3D gs101_wkup_irq_set_wake, + .irq_request_resources =3D exynos_irq_request_resources, + .irq_release_resources =3D exynos_irq_release_resources, + }, + .eint_num_wakeup_reg =3D 3, + .eint_wake_mask_reg =3D GS101_EINT_WAKEUP_MASK, + .set_eint_wakeup_mask =3D gs101_pinctrl_set_eint_wakeup_mask, +}; + /* list of external wakeup controllers supported */ static const struct of_device_id exynos_wkup_irq_ids[] =3D { + { .compatible =3D "google,gs101-wakeup-eint", + .data =3D &gs101_wkup_irq_chip }, { .compatible =3D "samsung,s5pv210-wakeup-eint", .data =3D &s5pv210_wkup_irq_chip }, { .compatible =3D "samsung,exynos4210-wakeup-eint", @@ -688,6 +756,7 @@ static void exynos_irq_demux_eint16_31(struct irq_desc = *desc) chained_irq_exit(chip, desc); } =20 +static int eint_num; /* * exynos_eint_wkup_init() - setup handling of external wakeup interrupts. * @d: driver data of samsung pinctrl driver. @@ -736,6 +805,9 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl= _drv_data *d) return -ENXIO; } =20 + bank->eint_num =3D eint_num; + eint_num =3D eint_num + bank->nr_pins; + if (!fwnode_property_present(bank->fwnode, "interrupts")) { bank->eint_type =3D EINT_TYPE_WKUP_MUX; ++muxed_banks; diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/sa= msung/pinctrl-samsung.h index fcc57c244d167db1de8c7aceffa6a9e7484bf348..1cabcbe1401a614ea33803132db= 776e97c1d56ee 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -141,6 +141,7 @@ struct samsung_pin_bank_type { * @eint_type: type of the external interrupt supported by the bank. * @eint_mask: bit mask of pins which support EINT function. * @eint_offset: SoC-specific EINT register or interrupt offset of bank. + * @eint_num: total number of eint pins. * @eint_con_offset: ExynosAuto SoC-specific EINT control register offset = of bank. * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of= bank. * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of= bank. @@ -156,6 +157,7 @@ struct samsung_pin_bank_data { enum eint_type eint_type; u32 eint_mask; u32 eint_offset; + u32 eint_num; u32 eint_con_offset; u32 eint_mask_offset; u32 eint_pend_offset; @@ -174,6 +176,7 @@ struct samsung_pin_bank_data { * @eint_type: type of the external interrupt supported by the bank. * @eint_mask: bit mask of pins which support EINT function. * @eint_offset: SoC-specific EINT register or interrupt offset of bank. + * @eint_num: total number of eint pins. * @eint_con_offset: ExynosAuto SoC-specific EINT register or interrupt of= fset of bank. * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of= bank. * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of= bank. @@ -201,6 +204,7 @@ struct samsung_pin_bank { enum eint_type eint_type; u32 eint_mask; u32 eint_offset; + u32 eint_num; u32 eint_con_offset; u32 eint_mask_offset; u32 eint_pend_offset; diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/so= c/samsung/exynos-regs-pmu.h index 1a2c0e0838f99821151661878f022f2129a0c19b..938c6db235fb00b1245ab2aa44a= 094f163b6b84b 100644 --- a/include/linux/soc/samsung/exynos-regs-pmu.h +++ b/include/linux/soc/samsung/exynos-regs-pmu.h @@ -669,6 +669,7 @@ #define GS101_CPU_INFORM(cpu) \ (GS101_CPU0_INFORM + (cpu*4)) #define GS101_SYSTEM_CONFIGURATION (0x3A00) +#define GS101_EINT_WAKEUP_MASK (0x3A80) #define GS101_PHY_CTRL_USB20 (0x3EB0) #define GS101_PHY_CTRL_USBDP (0x3EB4) =20 --=20 2.50.0.rc2.701.gf1e915cc24-goog