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AJvYcCXcinELfTpPcpsqIjE0/ESzPhmSPG2MzOREjnKD8BGuJqsfr4+6H1iIuNKI+DN8EZ5x9Pn+ySaVjeGHptE=@vger.kernel.org X-Gm-Message-State: AOJu0YywVekfN59yt3PVhIsii/SyJGNEJMYTUte5gPyNfLnWxtpr3hRs bi6nhAdTX4NgaDvajjQxmQaWZZXhXSfq/NXFBZ7VwFnOF+tgDykiRHuq48MX7HRKppoj5h8jecX XJCvsmLqFNNgfvGMvqeFHKp29wGa0xw== X-Google-Smtp-Source: AGHT+IHnN4KQrdCKJ7jBLwoS1jPThBVW4hDHqpvXB6q54bqABdZTJVdZXZ6NaNfXR5nGBhyVR/ay/ByQfgGq2xiOFrA= X-Received: from pjbpb15.prod.google.com ([2002:a17:90b:3c0f:b0:2ef:d283:5089]) (user=willmcvicker job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90a:dfc6:b0:311:b413:f5e1 with SMTP id 98e67ed59e1d1-313f1e22ec0mr22222585a91.32.1750280943259; Wed, 18 Jun 2025 14:09:03 -0700 (PDT) Date: Wed, 18 Jun 2025 14:08:39 -0700 In-Reply-To: <20250618210851.661527-1-willmcvicker@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250618210851.661527-1-willmcvicker@google.com> X-Mailer: git-send-email 2.50.0.rc2.761.g2dc52ea45b-goog Message-ID: <20250618210851.661527-3-willmcvicker@google.com> Subject: [PATCH 2/6] clocksource/drivers/exynos_mct: Don't register as a sched_clock on arm64 From: Will McVicker To: Catalin Marinas , Will Deacon , Daniel Lezcano , Thomas Gleixner , Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Saravana Kannan Cc: Will McVicker , Donghoon Yu , Hosung Kim , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, John Stultz , Youngmin Nam , Peter Griffin , Tudor Ambarus , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Conor Dooley , linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MCT register is unfortunately very slow to access, but importantly does not halt in the c2 idle state. So for ARM64, we can improve performance by not registering the MCT for sched_clock, allowing the system to use the faster ARM architected timer for sched_clock instead. The MCT is still registered as a clocksource, and a clockevent in order to be a wakeup source for the arch_timer to exit the "c2" idle state. Since ARM32 SoCs don't have an architected timer, the MCT must continue to be used for sched_clock. Detailed discussion on this topic can be found at [1]. [1] https://lore.kernel.org/linux-samsung-soc/1400188079-21832-1-git-send-e= mail-chirantan@chromium.org/ [Original commit from https://android.googlesource.com/kernel/gs/+/630817f7= 080e92c5e0216095ff52f6eb8dd00727 Signed-off-by: Donghoon Yu Signed-off-by: Youngmin Nam Reviewed-by: Youngmin Nam Acked-by: John Stultz Tested-by: Youngmin Nam Signed-off-by: Will McVicker --- drivers/clocksource/exynos_mct.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_= mct.c index da09f467a6bb..96361d5dc57d 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -219,12 +219,18 @@ static struct clocksource mct_frc =3D { .resume =3D exynos4_frc_resume, }; =20 +/* + * Since ARM devices do not have an architected timer, they need to contin= ue + * using the MCT as the main clocksource for timekeeping, sched_clock, and= the + * delay timer. For AARCH64 SoCs, the architected timer is the preferred + * clocksource due to it's superior performance. + */ +#if defined(CONFIG_ARM) static u64 notrace exynos4_read_sched_clock(void) { return exynos4_read_count_32(); } =20 -#if defined(CONFIG_ARM) static struct delay_timer exynos4_delay_timer; =20 static cycles_t exynos4_read_current_timer(void) @@ -250,12 +256,13 @@ static int __init exynos4_clocksource_init(bool frc_s= hared) exynos4_delay_timer.read_current_timer =3D &exynos4_read_current_timer; exynos4_delay_timer.freq =3D clk_rate; register_current_timer_delay(&exynos4_delay_timer); + + sched_clock_register(exynos4_read_sched_clock, 32, clk_rate); #endif =20 if (clocksource_register_hz(&mct_frc, clk_rate)) panic("%s: can't register clocksource\n", mct_frc.name); =20 - sched_clock_register(exynos4_read_sched_clock, 32, clk_rate); =20 return 0; } --=20 2.50.0.rc2.761.g2dc52ea45b-goog