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charset="utf-8" Need to export `of_irq_count` in preparation for modularizing the Exynos MCT driver which uses this API for setting up the timer IRQs. Acked-by: Rob Herring (Arm) Acked-by: Arnd Bergmann Reviewed-by: Linus Walleij Reviewed-by: Youngmin Nam Tested-by: Youngmin Nam Signed-off-by: Will McVicker --- drivers/of/irq.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/of/irq.c b/drivers/of/irq.c index f8ad79b9b1c9..5adda1dac3cf 100644 --- a/drivers/of/irq.c +++ b/drivers/of/irq.c @@ -519,6 +519,7 @@ int of_irq_count(struct device_node *dev) =20 return nr; } +EXPORT_SYMBOL_GPL(of_irq_count); =20 /** * of_irq_to_resource_table - Fill in resource table with node's IRQ info --=20 2.50.0.rc2.761.g2dc52ea45b-goog From nobody Thu Oct 9 08:16:05 2025 Received: from mail-pg1-f201.google.com (mail-pg1-f201.google.com [209.85.215.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E583926157D for ; Wed, 18 Jun 2025 21:09:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.201 ARC-Seal: i=1; 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Wed, 18 Jun 2025 14:09:03 -0700 (PDT) Date: Wed, 18 Jun 2025 14:08:39 -0700 In-Reply-To: <20250618210851.661527-1-willmcvicker@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250618210851.661527-1-willmcvicker@google.com> X-Mailer: git-send-email 2.50.0.rc2.761.g2dc52ea45b-goog Message-ID: <20250618210851.661527-3-willmcvicker@google.com> Subject: [PATCH 2/6] clocksource/drivers/exynos_mct: Don't register as a sched_clock on arm64 From: Will McVicker To: Catalin Marinas , Will Deacon , Daniel Lezcano , Thomas Gleixner , Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Saravana Kannan Cc: Will McVicker , Donghoon Yu , Hosung Kim , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, John Stultz , Youngmin Nam , Peter Griffin , Tudor Ambarus , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Conor Dooley , linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MCT register is unfortunately very slow to access, but importantly does not halt in the c2 idle state. So for ARM64, we can improve performance by not registering the MCT for sched_clock, allowing the system to use the faster ARM architected timer for sched_clock instead. The MCT is still registered as a clocksource, and a clockevent in order to be a wakeup source for the arch_timer to exit the "c2" idle state. Since ARM32 SoCs don't have an architected timer, the MCT must continue to be used for sched_clock. Detailed discussion on this topic can be found at [1]. [1] https://lore.kernel.org/linux-samsung-soc/1400188079-21832-1-git-send-e= mail-chirantan@chromium.org/ [Original commit from https://android.googlesource.com/kernel/gs/+/630817f7= 080e92c5e0216095ff52f6eb8dd00727 Signed-off-by: Donghoon Yu Signed-off-by: Youngmin Nam Reviewed-by: Youngmin Nam Acked-by: John Stultz Tested-by: Youngmin Nam Signed-off-by: Will McVicker --- drivers/clocksource/exynos_mct.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_= mct.c index da09f467a6bb..96361d5dc57d 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -219,12 +219,18 @@ static struct clocksource mct_frc =3D { .resume =3D exynos4_frc_resume, }; =20 +/* + * Since ARM devices do not have an architected timer, they need to contin= ue + * using the MCT as the main clocksource for timekeeping, sched_clock, and= the + * delay timer. For AARCH64 SoCs, the architected timer is the preferred + * clocksource due to it's superior performance. + */ +#if defined(CONFIG_ARM) static u64 notrace exynos4_read_sched_clock(void) { return exynos4_read_count_32(); } =20 -#if defined(CONFIG_ARM) static struct delay_timer exynos4_delay_timer; =20 static cycles_t exynos4_read_current_timer(void) @@ -250,12 +256,13 @@ static int __init exynos4_clocksource_init(bool frc_s= hared) exynos4_delay_timer.read_current_timer =3D &exynos4_read_current_timer; exynos4_delay_timer.freq =3D clk_rate; register_current_timer_delay(&exynos4_delay_timer); + + sched_clock_register(exynos4_read_sched_clock, 32, clk_rate); #endif =20 if (clocksource_register_hz(&mct_frc, clk_rate)) panic("%s: can't register clocksource\n", mct_frc.name); =20 - sched_clock_register(exynos4_read_sched_clock, 32, clk_rate); =20 return 0; } --=20 2.50.0.rc2.761.g2dc52ea45b-goog From nobody Thu Oct 9 08:16:05 2025 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41E18262FF9 for ; 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charset="utf-8" From: Hosung Kim To allow the CPU to handle it's own clock events, we need to set the IRQF_PERCPU flag. This prevents the local timer interrupts from migrating to other CPUs. Signed-off-by: Hosung Kim [Original commit from https://android.googlesource.com/kernel/gs/+/03267fad= 19f093bac979ca78309483e9eb3a8d16] Reviewed-by: Peter Griffin Reviewed-by: Youngmin Nam Tested-by: Youngmin Nam Signed-off-by: Will McVicker --- drivers/clocksource/exynos_mct.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_= mct.c index 96361d5dc57d..a5ef7d64b1c2 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -596,7 +596,8 @@ static int __init exynos4_timer_interrupts(struct devic= e_node *np, irq_set_status_flags(mct_irq, IRQ_NOAUTOEN); if (request_irq(mct_irq, exynos4_mct_tick_isr, - IRQF_TIMER | IRQF_NOBALANCING, + IRQF_TIMER | IRQF_NOBALANCING | + IRQF_PERCPU, pcpu_mevt->name, pcpu_mevt)) { pr_err("exynos-mct: cannot register IRQ (cpu%d)\n", cpu); --=20 2.50.0.rc2.761.g2dc52ea45b-goog From nobody Thu Oct 9 08:16:05 2025 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51FDB265CD4 for ; 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Wed, 18 Jun 2025 14:09:11 -0700 (PDT) Date: Wed, 18 Jun 2025 14:08:41 -0700 In-Reply-To: <20250618210851.661527-1-willmcvicker@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250618210851.661527-1-willmcvicker@google.com> X-Mailer: git-send-email 2.50.0.rc2.761.g2dc52ea45b-goog Message-ID: <20250618210851.661527-5-willmcvicker@google.com> Subject: [PATCH 4/6] clocksource/drivers/exynos_mct: Fix uninitialized irq name warning From: Will McVicker To: Catalin Marinas , Will Deacon , Daniel Lezcano , Thomas Gleixner , Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Saravana Kannan Cc: Will McVicker , Donghoon Yu , Hosung Kim , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, John Stultz , Youngmin Nam , Peter Griffin , Tudor Ambarus , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Conor Dooley , linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Exynos MCT driver doesn't set the clocksource name until the CPU hotplug state is setup which happens after the IRQs are requested. This results in an empty IRQ name which leads to the below warning at proc_create() time. When this happens, the userdata partition fails to mount and the device gets stuck in an endless loop printing the error: root '/dev/disk/by-partlabel/userdata' doesn't exist or does not contain = a /dev. To fix this, we just need to initialize the name before requesting the IRQs. Warning from Pixel 6 kernel log: [ T430] name len 0 [ T430] WARNING: CPU: 6 PID: 430 at fs/proc/generic.c:407 __proc_create+0x= 258/0x2b4 [ T430] Modules linked in: dwc3_exynos(E+) [ T430] ufs_exynos(E+) phy_exynos_ufs(E) [ T430] phy_exynos5_usbdrd(E) exynos_usi(E+) exynos_mct(E+) s3c2410_wdt(E) [ T430] arm_dsu_pmu(E) simplefb(E) [ T430] CPU: 6 UID: 0 PID: 430 Comm: (udev-worker) Tainted: ... 6.14.0-next-20250331-4k-00008-g59adf909e40e #1 ... [ T430] Tainted: [W]=3DWARN, [E]=3DUNSIGNED_MODULE [ T430] Hardware name: Raven (DT) [...] [ T430] Call trace: [ T430] __proc_create+0x258/0x2b4 (P) [ T430] proc_mkdir+0x40/0xa0 [ T430] register_handler_proc+0x118/0x140 [ T430] __setup_irq+0x460/0x6d0 [ T430] request_threaded_irq+0xcc/0x1b0 [ T430] mct_init_dt+0x244/0x604 [exynos_mct ...] [ T430] mct_init_spi+0x18/0x34 [exynos_mct ...] [ T430] exynos4_mct_probe+0x30/0x4c [exynos_mct ...] [ T430] platform_probe+0x6c/0xe4 [ T430] really_probe+0xf4/0x38c [...] [ T430] driver_register+0x6c/0x140 [ T430] __platform_driver_register+0x28/0x38 [ T430] exynos4_mct_driver_init+0x24/0xfe8 [exynos_mct ...] [ T430] do_one_initcall+0x84/0x3c0 [ T430] do_init_module+0x58/0x208 [ T430] load_module+0x1de0/0x2500 [ T430] init_module_from_file+0x8c/0xdc Reviewed-by: Peter Griffin Reviewed-by: Youngmin Nam Tested-by: Youngmin Nam Signed-off-by: Will McVicker --- drivers/clocksource/exynos_mct.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_= mct.c index a5ef7d64b1c2..62febeb4e1de 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -465,8 +465,6 @@ static int exynos4_mct_starting_cpu(unsigned int cpu) per_cpu_ptr(&percpu_mct_tick, cpu); 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Wed, 18 Jun 2025 14:09:15 -0700 (PDT) Date: Wed, 18 Jun 2025 14:08:42 -0700 In-Reply-To: <20250618210851.661527-1-willmcvicker@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250618210851.661527-1-willmcvicker@google.com> X-Mailer: git-send-email 2.50.0.rc2.761.g2dc52ea45b-goog Message-ID: <20250618210851.661527-6-willmcvicker@google.com> Subject: [PATCH 5/6] clocksource/drivers/exynos_mct: Add module support From: Will McVicker To: Catalin Marinas , Will Deacon , Daniel Lezcano , Thomas Gleixner , Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Saravana Kannan Cc: Will McVicker , Donghoon Yu , Hosung Kim , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, John Stultz , Youngmin Nam , Peter Griffin , Tudor Ambarus , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Conor Dooley , linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Donghoon Yu On Arm64 platforms the Exynos MCT driver can be built as a module. On boot (and even after boot) the arch_timer is used as the clocksource and tick timer. Once the MCT driver is loaded, it can be used as the wakeup source for the arch_timer. Signed-off-by: Donghoon Yu Signed-off-by: Youngmin Nam [original commit from https://android.googlesource.com/kernel/gs/+/8a52a828= 8ec7d88ff78f0b37480dbb0e9c65bbfd] Reviewed-by: Youngmin Nam Tested-by: Youngmin Nam Signed-off-by: Will McVicker --- drivers/clocksource/Kconfig | 3 +- drivers/clocksource/exynos_mct.c | 51 ++++++++++++++++++++++++++------ 2 files changed, 44 insertions(+), 10 deletions(-) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 645f517a1ac2..d657c8ddc96b 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -451,7 +451,8 @@ config ATMEL_TCB_CLKSRC Support for Timer Counter Blocks on Atmel SoCs. =20 config CLKSRC_EXYNOS_MCT - bool "Exynos multi core timer driver" if COMPILE_TEST + tristate "Exynos multi core timer driver" if ARM64 + default y if ARCH_EXYNOS || COMPILE_TEST depends on ARM || ARM64 depends on ARCH_ARTPEC || ARCH_EXYNOS || COMPILE_TEST help diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_= mct.c index 62febeb4e1de..5075ebe052a7 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -15,9 +15,11 @@ #include #include #include +#include #include #include #include +#include #include #include =20 @@ -217,6 +219,7 @@ static struct clocksource mct_frc =3D { .mask =3D CLOCKSOURCE_MASK(32), .flags =3D CLOCK_SOURCE_IS_CONTINUOUS, .resume =3D exynos4_frc_resume, + .owner =3D THIS_MODULE, }; =20 /* @@ -241,7 +244,7 @@ static cycles_t exynos4_read_current_timer(void) } #endif =20 -static int __init exynos4_clocksource_init(bool frc_shared) +static int exynos4_clocksource_init(bool frc_shared) { /* * When the frc is shared, the main processor should have already @@ -336,6 +339,7 @@ static struct clock_event_device mct_comp_device =3D { .set_state_oneshot =3D mct_set_state_shutdown, .set_state_oneshot_stopped =3D mct_set_state_shutdown, .tick_resume =3D mct_set_state_shutdown, + .owner =3D THIS_MODULE, }; =20 static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id) @@ -476,6 +480,7 @@ static int exynos4_mct_starting_cpu(unsigned int cpu) evt->features =3D CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERCPU; evt->rating =3D MCT_CLKEVENTS_RATING; + evt->owner =3D THIS_MODULE; =20 exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET); =20 @@ -511,7 +516,7 @@ static int exynos4_mct_dying_cpu(unsigned int cpu) return 0; } =20 -static int __init exynos4_timer_resources(struct device_node *np) +static int exynos4_timer_resources(struct device_node *np) { struct clk *mct_clk, *tick_clk; =20 @@ -539,7 +544,7 @@ static int __init exynos4_timer_resources(struct device= _node *np) * @local_idx: array mapping CPU numbers to local timer indices * @nr_local: size of @local_idx array */ -static int __init exynos4_timer_interrupts(struct device_node *np, +static int exynos4_timer_interrupts(struct device_node *np, unsigned int int_type, const u32 *local_idx, size_t nr_local) @@ -652,7 +657,7 @@ static int __init exynos4_timer_interrupts(struct devic= e_node *np, return err; } =20 -static int __init mct_init_dt(struct device_node *np, unsigned int int_typ= e) +static int mct_init_dt(struct device_node *np, unsigned int int_type) { bool frc_shared =3D of_property_read_bool(np, "samsung,frc-shared"); u32 local_idx[MCT_NR_LOCAL] =3D {0}; @@ -700,15 +705,43 @@ static int __init mct_init_dt(struct device_node *np,= unsigned int int_type) return exynos4_clockevent_init(); } =20 - -static int __init mct_init_spi(struct device_node *np) +static int mct_init_spi(struct device_node *np) { return mct_init_dt(np, MCT_INT_SPI); } =20 -static int __init mct_init_ppi(struct device_node *np) +static int mct_init_ppi(struct device_node *np) { return mct_init_dt(np, MCT_INT_PPI); } -TIMER_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi); -TIMER_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi); + +static int exynos4_mct_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + int (*mct_init)(struct device_node *np); + + mct_init =3D of_device_get_match_data(dev); + if (!mct_init) + return -EINVAL; + + return mct_init(dev->of_node); +} + +static const struct of_device_id exynos4_mct_match_table[] =3D { + { .compatible =3D "samsung,exynos4210-mct", .data =3D &mct_init_spi, }, + { .compatible =3D "samsung,exynos4412-mct", .data =3D &mct_init_ppi, }, + {} +}; +MODULE_DEVICE_TABLE(of, exynos4_mct_match_table); + +static struct platform_driver exynos4_mct_driver =3D { + .probe =3D exynos4_mct_probe, + .driver =3D { + .name =3D "exynos-mct", + .of_match_table =3D exynos4_mct_match_table, + }, +}; +module_platform_driver(exynos4_mct_driver); + +MODULE_DESCRIPTION("Exynos Multi Core Timer Driver"); +MODULE_LICENSE("GPL"); --=20 2.50.0.rc2.761.g2dc52ea45b-goog From nobody Thu Oct 9 08:16:05 2025 Received: from mail-pg1-f201.google.com (mail-pg1-f201.google.com [209.85.215.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F1C9267AF1 for ; Wed, 18 Jun 2025 21:09:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750280961; cv=none; b=k//C6CAPRVgjiaVT5CHGjIiTg/2LcTdRLZ5q4vriHS7+p6/9YU6v6MNC5Ja/05wJ66oLXHjIffPe3ELCKF1pGOHMec/F+MFzUnis4DqQRetDm3QmsObgwxntmK9SA2BEWIxTcQ+7cZ5oOww9LTZCfP6yP7X6pYoX5uIH6/9kXY0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750280961; c=relaxed/simple; bh=FXb5Ooh1SoKLFB+GF1YDuF7hepy8ALKLUWQZf6h1mvk=; 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charset="utf-8" Since the Exynos MCT driver can be built as a module for some Arm64 SoCs like gs101, drop force-selecting it as a built-in driver by ARCH_EXYNOS and instead depend on `default y if ARCH_EXYNOS` to select it automatically. This allows platforms like Android to build the driver as a module if desired. Reviewed-by: Youngmin Nam Tested-by: Youngmin Nam Signed-off-by: Will McVicker --- arch/arm64/Kconfig.platforms | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index a541bb029aa4..46825b02d099 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -109,7 +109,6 @@ config ARCH_BLAIZE config ARCH_EXYNOS bool "Samsung Exynos SoC family" select COMMON_CLK_SAMSUNG - select CLKSRC_EXYNOS_MCT select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS select EXYNOS_PMU select PINCTRL --=20 2.50.0.rc2.761.g2dc52ea45b-goog