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X-CSE-ConnectionGUID: g2/BdWoMTJ2aqM4Upa5Zzw== X-CSE-MsgGUID: LmjFdBPZSySIf0Mc7si3bA== X-IronPort-AV: E=McAfee;i="6800,10657,11468"; a="52210197" X-IronPort-AV: E=Sophos;i="6.16,246,1744095600"; d="scan'208";a="52210197" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2025 11:56:43 -0700 X-CSE-ConnectionGUID: QzqCr6nsR0ydzltTF4UPwA== X-CSE-MsgGUID: iAgK3UiAT+C9zJxbw+OVhw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,246,1744095600"; d="scan'208";a="153951699" Received: from unknown (HELO bnilawar-desk2.iind.intel.com) ([10.190.239.41]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2025 11:56:40 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com, jgg@nvidia.com Subject: [PATCH v3 04/10] drm/xe/xe_late_bind_fw: Initialize late binding firmware Date: Thu, 19 Jun 2025 00:30:01 +0530 Message-Id: <20250618190007.2932322-5-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618190007.2932322-1-badal.nilawar@intel.com> References: <20250618190007.2932322-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Search for late binding firmware binaries and populate the meta data of firmware structures. v2 (Daniele): - drm_err if firmware size is more than max pay load size - s/request_firmware/firmware_request_nowarn/ as firmware will not be available for all possible cards v3 (Daniele): - init firmware from within xe_late_bind_init, propagate error - switch late_bind_fw to array to handle multiple firmware types Signed-off-by: Badal Nilawar --- drivers/gpu/drm/xe/xe_late_bind_fw.c | 97 +++++++++++++++++++++- drivers/gpu/drm/xe/xe_late_bind_fw_types.h | 32 +++++++ drivers/misc/mei/late_bind/mei_late_bind.c | 1 - 3 files changed, 128 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.c b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.c index 52cb295b7df6..d416d6cc1fa2 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw.c +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.c @@ -5,6 +5,7 @@ =20 #include #include +#include =20 #include #include @@ -13,6 +14,16 @@ =20 #include "xe_device.h" #include "xe_late_bind_fw.h" +#include "xe_pcode.h" +#include "xe_pcode_api.h" + +static const u32 fw_id_to_type[] =3D { + [FAN_CONTROL_FW_ID] =3D CSC_LATE_BINDING_TYPE_FAN_CONTROL, + }; + +static const char * const fw_id_to_name[] =3D { + [FAN_CONTROL_FW_ID] =3D "fan_control", + }; =20 static struct xe_device * late_bind_to_xe(struct xe_late_bind *late_bind) @@ -20,6 +31,86 @@ late_bind_to_xe(struct xe_late_bind *late_bind) return container_of(late_bind, struct xe_device, late_bind); } =20 +static int xe_late_bind_fw_num_fans(struct xe_late_bind *late_bind) +{ + struct xe_device *xe =3D late_bind_to_xe(late_bind); + struct xe_tile *root_tile =3D xe_device_get_root_tile(xe); + u32 uval; + + if (!xe_pcode_read(root_tile, + PCODE_MBOX(FAN_SPEED_CONTROL, FSC_READ_NUM_FANS, 0), &uval, NULL)) + return uval; + else + return 0; +} + +static int __xe_late_bind_fw_init(struct xe_late_bind *late_bind, u32 fw_i= d) +{ + struct xe_device *xe =3D late_bind_to_xe(late_bind); + struct pci_dev *pdev =3D to_pci_dev(xe->drm.dev); + struct xe_late_bind_fw *lb_fw; + const struct firmware *fw; + u32 num_fans; + int ret; + + if (fw_id >=3D MAX_FW_ID) + return -EINVAL; + + lb_fw =3D &late_bind->late_bind_fw[fw_id]; + + lb_fw->valid =3D false; + lb_fw->id =3D fw_id; + lb_fw->type =3D fw_id_to_type[lb_fw->id]; + lb_fw->flags &=3D ~CSC_LATE_BINDING_FLAGS_IS_PERSISTENT; + + if (lb_fw->type =3D=3D CSC_LATE_BINDING_TYPE_FAN_CONTROL) { + num_fans =3D xe_late_bind_fw_num_fans(late_bind); + drm_dbg(&xe->drm, "Number of Fans: %d\n", num_fans); + if (!num_fans) + return 0; + } + + snprintf(lb_fw->blob_path, sizeof(lb_fw->blob_path), "xe/%s_8086_%04x_%04= x_%04x.bin", + fw_id_to_name[lb_fw->id], pdev->device, + pdev->subsystem_vendor, pdev->subsystem_device); + + drm_dbg(&xe->drm, "Request late binding firmware %s\n", lb_fw->blob_path); + ret =3D firmware_request_nowarn(&fw, lb_fw->blob_path, xe->drm.dev); + if (ret) { + drm_dbg(&xe->drm, "%s late binding fw not available for current device", + fw_id_to_name[lb_fw->id]); + return 0; + } + + if (fw->size > MAX_PAYLOAD_SIZE) { + drm_err(&xe->drm, "Firmware %s size %zu is larger than max pay load size= %u\n", + lb_fw->blob_path, fw->size, MAX_PAYLOAD_SIZE); + release_firmware(fw); + return -ENODATA; + } + + lb_fw->payload_size =3D fw->size; + + memcpy(lb_fw->payload, fw->data, lb_fw->payload_size); + release_firmware(fw); + lb_fw->valid =3D true; + + return 0; +} + +static int xe_late_bind_fw_init(struct xe_late_bind *late_bind) +{ + int ret; + int fw_id; + + for (fw_id =3D 0; fw_id < MAX_FW_ID; fw_id++) { + ret =3D __xe_late_bind_fw_init(late_bind, fw_id); + if (ret) + return ret; + } + return ret; +} + static int xe_late_bind_component_bind(struct device *xe_kdev, struct device *mei_kdev, void *data) { @@ -89,5 +180,9 @@ int xe_late_bind_init(struct xe_late_bind *late_bind) =20 late_bind->component_added =3D true; =20 - return devm_add_action_or_reset(xe->drm.dev, xe_late_bind_remove, late_bi= nd); + err =3D devm_add_action_or_reset(xe->drm.dev, xe_late_bind_remove, late_b= ind); + if (err) + return err; + + return xe_late_bind_fw_init(late_bind); } diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h b/drivers/gpu/drm/x= e/xe_late_bind_fw_types.h index ef0a9723bee4..c6fd33fd5484 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h +++ b/drivers/gpu/drm/xe/xe_late_bind_fw_types.h @@ -10,6 +10,36 @@ #include #include =20 +#define MAX_PAYLOAD_SIZE (1024 * 4) + +/** + * xe_late_bind_fw_id - enum to determine late binding fw index + */ +enum xe_late_bind_fw_id { + FAN_CONTROL_FW_ID =3D 0, + MAX_FW_ID +}; + +/** + * struct xe_late_bind_fw + */ +struct xe_late_bind_fw { + /** @late_bind_fw.valid: to check if fw is valid */ + bool valid; + /** @late_bind_fw.id: firmware index */ + u32 id; + /** @late_bind_fw.blob_path: firmware binary path */ + char blob_path[PATH_MAX]; + /** @late_bind_fw.type: firmware type */ + u32 type; + /** @late_bind_fw.flags: firmware flags */ + u32 flags; + /** @late_bind_fw.payload: to store the late binding blob */ + u8 payload[MAX_PAYLOAD_SIZE]; + /** @late_bind_fw.payload_size: late binding blob payload_size */ + size_t payload_size; +}; + /** * struct xe_late_bind_component - Late Binding services component * @mei_dev: device that provide Late Binding service. @@ -34,6 +64,8 @@ struct xe_late_bind { bool component_added; /** @late_bind.mutex: protects the component binding and usage */ struct mutex mutex; + /** @late_bind.late_bind_fw: late binding firmware array */ + struct xe_late_bind_fw late_bind_fw[MAX_FW_ID]; }; =20 #endif diff --git a/drivers/misc/mei/late_bind/mei_late_bind.c b/drivers/misc/mei/= late_bind/mei_late_bind.c index cb985f32309e..6ea64c44bb94 100644 --- a/drivers/misc/mei/late_bind/mei_late_bind.c +++ b/drivers/misc/mei/late_bind/mei_late_bind.c @@ -2,7 +2,6 @@ /* * Copyright (C) 2025 Intel Corporation */ -#include #include #include #include --=20 2.34.1