From nobody Thu Oct 9 10:37:25 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3EE62F547D for ; Wed, 18 Jun 2025 18:56:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750273002; cv=none; b=XUSzgKNZ/eWcaHXBZ1DASYPZ2l1UYaY3v6iNzLqlwVy6XXwwXgOUMQ9vlN5/GdHaO2Vd06u1B0fgLuRPervRbsadokp/VEIBWtvHyEh10zRPDqXZ+Pe+KJtoHvtZDBOKlsPC1RLX/O6duhsXCG0Cejc2y3zXfARfHTCtS9Bup0A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750273002; c=relaxed/simple; bh=62EbXVS38zPLKorkESqoDi598ulaMaVHnADbRkJTn9U=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=IQTMVApJPiOKyzf1YlsGPLwfEoPbg3WMIQqlIwUmqg4BQFLJk6vTV+RMfeAV8cVdW2vGKW6S8mXguaXktg5QzelWIzSTDDeEeJcVck2UpwokuROV3g9Gwo7snzQMqikKf9Mbfoc6aoebuw2obgZfACs3PmKPsPZIJg7y/oOKkSU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Y6PO0uRf; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Y6PO0uRf" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750273001; x=1781809001; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=62EbXVS38zPLKorkESqoDi598ulaMaVHnADbRkJTn9U=; b=Y6PO0uRfyD4EyoV6ONq1bKBbl09PQsilaPZnd0V/k+f2IEOGzhJhxas8 8D6cWmUC44C0ZoTK5DFj/QIRZURYkBwYWXaT4gfb1WJLV4P57fwRA/wmI JUcB7uOjpHO4GMpZqXk1LLExxCQxAxzKhLfLuw51ZFC3QsNqq7GdP1kVQ qcLhyOxNUWqQrdENdaXzNFH8x3gXT7CAbqlbbUETZ6+Gg48pMjg4pEDlE dSMC9c9IkL4r6DcpVGBLhHBOz4Jb3R51ADmI7/0w8GXJA6tUnqCMjDqVM 2ZdVGFkSwCMUzmdOiAL5FguU84Ijd3ybRzR6Ed8cwUMqO1e2n8ozEK+hY w==; X-CSE-ConnectionGUID: I6C8mltTQnCIlNUtald+Rg== X-CSE-MsgGUID: WkheF6MrTECp3kufODqKNQ== X-IronPort-AV: E=McAfee;i="6800,10657,11468"; a="52210190" X-IronPort-AV: E=Sophos;i="6.16,246,1744095600"; d="scan'208";a="52210190" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2025 11:56:40 -0700 X-CSE-ConnectionGUID: APcRPjIAT1qOtugCp9WE8A== X-CSE-MsgGUID: PwQXHnqMRBq44Mmzoo4hdQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,246,1744095600"; d="scan'208";a="153951622" Received: from unknown (HELO bnilawar-desk2.iind.intel.com) ([10.190.239.41]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2025 11:56:37 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com, jgg@nvidia.com Subject: [PATCH v3 03/10] drm/xe/xe_late_bind_fw: Introducing xe_late_bind_fw Date: Thu, 19 Jun 2025 00:30:00 +0530 Message-Id: <20250618190007.2932322-4-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618190007.2932322-1-badal.nilawar@intel.com> References: <20250618190007.2932322-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Introducing xe_late_bind_fw to enable firmware loading for the devices, such as the fan controller, during the driver probe. Typically, firmware for such devices are part of IFWI flash image but can be replaced at probe after OEM tuning. This patch binds mei late binding component to enable firmware loading. v2: - Add devm_add_action_or_reset to remove the component (Daniele) - Add INTEL_MEI_GSC check in xe_late_bind_init() (Daniele) v3: - Fail driver probe if late bind initialization fails, add has_late_bind flag (Daniele) Signed-off-by: Badal Nilawar Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/xe/Makefile | 1 + drivers/gpu/drm/xe/xe_device.c | 5 ++ drivers/gpu/drm/xe/xe_device_types.h | 6 ++ drivers/gpu/drm/xe/xe_late_bind_fw.c | 93 ++++++++++++++++++++++ drivers/gpu/drm/xe/xe_late_bind_fw.h | 15 ++++ drivers/gpu/drm/xe/xe_late_bind_fw_types.h | 39 +++++++++ drivers/gpu/drm/xe/xe_pci.c | 3 + 7 files changed, 162 insertions(+) create mode 100644 drivers/gpu/drm/xe/xe_late_bind_fw.c create mode 100644 drivers/gpu/drm/xe/xe_late_bind_fw.h create mode 100644 drivers/gpu/drm/xe/xe_late_bind_fw_types.h diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index f5f5775acdc0..001384ca7357 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -76,6 +76,7 @@ xe-y +=3D xe_bb.o \ xe_hw_fence.o \ xe_irq.o \ xe_lrc.o \ + xe_late_bind_fw.o \ xe_migrate.o \ xe_mmio.o \ xe_mocs.o \ diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c index 7d9a31868ea9..13cf5f90d09e 100644 --- a/drivers/gpu/drm/xe/xe_device.c +++ b/drivers/gpu/drm/xe/xe_device.c @@ -43,6 +43,7 @@ #include "xe_hw_engine_group.h" #include "xe_hwmon.h" #include "xe_irq.h" +#include "xe_late_bind_fw.h" #include "xe_memirq.h" #include "xe_mmio.h" #include "xe_module.h" @@ -889,6 +890,10 @@ int xe_device_probe(struct xe_device *xe) if (err) return err; =20 + err =3D xe_late_bind_init(&xe->late_bind); + if (err && err !=3D -ENODEV) + return err; + err =3D xe_oa_init(xe); if (err) return err; diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_d= evice_types.h index a504b8ea6f3f..facafe2eea5c 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -16,6 +16,7 @@ #include "xe_devcoredump_types.h" #include "xe_heci_gsc.h" #include "xe_lmtt_types.h" +#include "xe_late_bind_fw_types.h" #include "xe_memirq_types.h" #include "xe_oa_types.h" #include "xe_platform_types.h" @@ -323,6 +324,8 @@ struct xe_device { u8 has_heci_cscfi:1; /** @info.has_heci_gscfi: device has heci gscfi */ u8 has_heci_gscfi:1; + /** @info.has_late_bind: Device has firmware late binding support */ + u8 has_late_bind:1; /** @info.has_llc: Device has a shared CPU+GPU last level cache */ u8 has_llc:1; /** @info.has_mbx_power_limits: Device has support to manage power limit= s using @@ -552,6 +555,9 @@ struct xe_device { /** @heci_gsc: graphics security controller */ struct xe_heci_gsc heci_gsc; =20 + /** @late_bind: xe mei late bind interface */ + struct xe_late_bind late_bind; + /** @oa: oa observation subsystem */ struct xe_oa oa; =20 diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.c b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.c new file mode 100644 index 000000000000..52cb295b7df6 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright =C2=A9 2025 Intel Corporation + */ + +#include +#include + +#include +#include +#include +#include + +#include "xe_device.h" +#include "xe_late_bind_fw.h" + +static struct xe_device * +late_bind_to_xe(struct xe_late_bind *late_bind) +{ + return container_of(late_bind, struct xe_device, late_bind); +} + +static int xe_late_bind_component_bind(struct device *xe_kdev, + struct device *mei_kdev, void *data) +{ + struct xe_device *xe =3D kdev_to_xe_device(xe_kdev); + struct xe_late_bind *late_bind =3D &xe->late_bind; + + mutex_lock(&late_bind->mutex); + late_bind->component.ops =3D data; + late_bind->component.mei_dev =3D mei_kdev; + mutex_unlock(&late_bind->mutex); + + return 0; +} + +static void xe_late_bind_component_unbind(struct device *xe_kdev, + struct device *mei_kdev, void *data) +{ + struct xe_device *xe =3D kdev_to_xe_device(xe_kdev); + struct xe_late_bind *late_bind =3D &xe->late_bind; + + mutex_lock(&late_bind->mutex); + late_bind->component.ops =3D NULL; + mutex_unlock(&late_bind->mutex); +} + +static const struct component_ops xe_late_bind_component_ops =3D { + .bind =3D xe_late_bind_component_bind, + .unbind =3D xe_late_bind_component_unbind, +}; + +static void xe_late_bind_remove(void *arg) +{ + struct xe_late_bind *late_bind =3D arg; + struct xe_device *xe =3D late_bind_to_xe(late_bind); + + component_del(xe->drm.dev, &xe_late_bind_component_ops); + late_bind->component_added =3D false; + mutex_destroy(&late_bind->mutex); +} + +/** + * xe_late_bind_init() - add xe mei late binding component + * + * Return: 0 if the initialization was successful, a negative errno otherw= ise. + */ +int xe_late_bind_init(struct xe_late_bind *late_bind) +{ + struct xe_device *xe =3D late_bind_to_xe(late_bind); + int err; + + if (!xe->info.has_late_bind) + return 0; + + mutex_init(&late_bind->mutex); + + if (!IS_ENABLED(CONFIG_INTEL_MEI_LATE_BIND) || !IS_ENABLED(CONFIG_INTEL_M= EI_GSC)) { + drm_info(&xe->drm, "Can't init xe mei late bind missing mei component\n"= ); + return -ENODEV; + } + + err =3D component_add_typed(xe->drm.dev, &xe_late_bind_component_ops, + I915_COMPONENT_LATE_BIND); + if (err < 0) { + drm_info(&xe->drm, "Failed to add mei late bind component (%pe)\n", ERR_= PTR(err)); + return err; + } + + late_bind->component_added =3D true; + + return devm_add_action_or_reset(xe->drm.dev, xe_late_bind_remove, late_bi= nd); +} diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.h b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.h new file mode 100644 index 000000000000..4c73571c3e62 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright =C2=A9 2025 Intel Corporation + */ + +#ifndef _XE_LATE_BIND_FW_H_ +#define _XE_LATE_BIND_FW_H_ + +#include + +struct xe_late_bind; + +int xe_late_bind_init(struct xe_late_bind *late_bind); + +#endif diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h b/drivers/gpu/drm/x= e/xe_late_bind_fw_types.h new file mode 100644 index 000000000000..ef0a9723bee4 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_late_bind_fw_types.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright =C2=A9 2025 Intel Corporation + */ + +#ifndef _XE_LATE_BIND_TYPES_H_ +#define _XE_LATE_BIND_TYPES_H_ + +#include +#include +#include + +/** + * struct xe_late_bind_component - Late Binding services component + * @mei_dev: device that provide Late Binding service. + * @ops: Ops implemented by Late Binding driver, used by Xe driver. + * + * Communication between Xe and MEI drivers for Late Binding services + */ +struct xe_late_bind_component { + /** @late_bind_component.mei_dev: mei device */ + struct device *mei_dev; + /** @late_bind_component.ops: late binding ops */ + const struct late_bind_component_ops *ops; +}; + +/** + * struct xe_late_bind + */ +struct xe_late_bind { + /** @late_bind.component: struct for communication with mei component */ + struct xe_late_bind_component component; + /** @late_bind.component_added: whether the component has been added */ + bool component_added; + /** @late_bind.mutex: protects the component binding and usage */ + struct mutex mutex; +}; + +#endif diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index 89814b32e585..d54d1d84e240 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -65,6 +65,7 @@ struct xe_device_desc { u8 has_fan_control:1; u8 has_heci_gscfi:1; u8 has_heci_cscfi:1; + u8 has_late_bind:1; u8 has_llc:1; u8 has_mbx_power_limits:1; u8 has_pxp:1; @@ -348,6 +349,7 @@ static const struct xe_device_desc bmg_desc =3D { .has_fan_control =3D true, .has_mbx_power_limits =3D true, .has_heci_cscfi =3D 1, + .has_late_bind =3D true, .needs_scratch =3D true, }; =20 @@ -592,6 +594,7 @@ static int xe_info_init_early(struct xe_device *xe, xe->info.has_mbx_power_limits =3D desc->has_mbx_power_limits; xe->info.has_heci_gscfi =3D desc->has_heci_gscfi; xe->info.has_heci_cscfi =3D desc->has_heci_cscfi; + xe->info.has_late_bind =3D desc->has_late_bind; xe->info.has_llc =3D desc->has_llc; xe->info.has_pxp =3D desc->has_pxp; xe->info.has_sriov =3D desc->has_sriov; --=20 2.34.1