From nobody Thu Oct 9 10:37:24 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86DF22F9497 for ; Wed, 18 Jun 2025 18:56:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750273000; cv=none; b=WlSY9va7Tfb2n8I/QOO8m0H3QSHT9Dm8VNH+cUxSd6fioZWmkY/jZIy3ulw/kwEr9iiKdSqYHoeHo4danLg4hGfsaA03uDv82BAj089VPCdTwuvxWz3BLjVych9Qioap2RD3z/zVNhEwSwT2QeU0dQm4Ck0vku269nlWSKLRjOI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750273000; c=relaxed/simple; bh=9K3w8vnfN4fxeur8c3NRnZDviAUw24vTKeSJ2wZZBtI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ljc+C8sLZVYc8Uh4CP1TCzgqHQtVmOiP+yzQxtiTyWDhxEI70vOMKDqpDwrQDnDjKo+oOgdSzcVxvwADU1deiaIWFxWejUyWmIkInmnnwxLOnUf40jy6el2a6/OgS8q42pEHa+BD8pzAMk2ipIAnNF6NiM6TejaBHaTL+F/GzNw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=cIb80hz4; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="cIb80hz4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750272998; x=1781808998; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9K3w8vnfN4fxeur8c3NRnZDviAUw24vTKeSJ2wZZBtI=; b=cIb80hz45d/CO/QWhVE4S707FHnWEc/qie/PeuMC6PnrMpxHlthdd5ai 7Vvo8ksKE9ZyatzVIFMzlGgYncIUOJuEtEh3k8e9W50Z1uEdNIm22usVO ALY91s8YNQCs1t5lUlTZILgavu91i4C8W53bj496yyp09xiJG/+OKteXI zI4ult5JN2pfruiGzFHaMmq6dbGG1ZFPgjReI07AnbK1BVMKZUFtINPZ7 znLB4gAS4mC/ac5OykdDys/rqLqIL0iYS/hQe7RrOsmEtjJI0ujVhf5gA N9ucTF+WhLXYa8ZYiRthOpOKSgJmy4xkmcvBJn8lk+Dfz8/yADWuU8uRz A==; X-CSE-ConnectionGUID: OyghkVHATOmWZ2EIZYPYzg== X-CSE-MsgGUID: IBcKWAlqRjeJpGc88SiXNQ== X-IronPort-AV: E=McAfee;i="6800,10657,11468"; a="52210184" X-IronPort-AV: E=Sophos;i="6.16,246,1744095600"; d="scan'208";a="52210184" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2025 11:56:37 -0700 X-CSE-ConnectionGUID: zq1vqjncQyKRu52Swa7tIg== X-CSE-MsgGUID: 4l890lChSw+yr2T/801HBg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,246,1744095600"; d="scan'208";a="153951538" Received: from unknown (HELO bnilawar-desk2.iind.intel.com) ([10.190.239.41]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2025 11:56:34 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com, jgg@nvidia.com Subject: [PATCH v3 02/10] mei: late_bind: add late binding component driver Date: Thu, 19 Jun 2025 00:29:59 +0530 Message-Id: <20250618190007.2932322-3-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618190007.2932322-1-badal.nilawar@intel.com> References: <20250618190007.2932322-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Alexander Usyskin Add late binding component driver. It allows pushing the late binding configuration from, for example, the Xe graphics driver to the Intel discrete graphics card's CSE device. Signed-off-by: Alexander Usyskin Signed-off-by: Badal Nilawar --- v2: - Use generic naming (Jani) - Drop xe_late_bind_component struct to move to xe code (Daniele/Sasha) v3: - Updated kconfig description - Move CSC late binding specific flags/defines to late_bind_mei_interface.= h (Daniele) v4: - Add match for PCI_CLASS_DISPLAY_OTHER to support headless cards (Anshuma= n) --- drivers/misc/mei/Kconfig | 1 + drivers/misc/mei/Makefile | 1 + drivers/misc/mei/late_bind/Kconfig | 13 + drivers/misc/mei/late_bind/Makefile | 9 + drivers/misc/mei/late_bind/mei_late_bind.c | 264 ++++++++++++++++++++ include/drm/intel/i915_component.h | 1 + include/drm/intel/late_bind_mei_interface.h | 50 ++++ 7 files changed, 339 insertions(+) create mode 100644 drivers/misc/mei/late_bind/Kconfig create mode 100644 drivers/misc/mei/late_bind/Makefile create mode 100644 drivers/misc/mei/late_bind/mei_late_bind.c create mode 100644 include/drm/intel/late_bind_mei_interface.h diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig index 7575fee96cc6..771becc68095 100644 --- a/drivers/misc/mei/Kconfig +++ b/drivers/misc/mei/Kconfig @@ -84,5 +84,6 @@ config INTEL_MEI_VSC source "drivers/misc/mei/hdcp/Kconfig" source "drivers/misc/mei/pxp/Kconfig" source "drivers/misc/mei/gsc_proxy/Kconfig" +source "drivers/misc/mei/late_bind/Kconfig" =20 endif diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile index 6f9fdbf1a495..84bfde888d81 100644 --- a/drivers/misc/mei/Makefile +++ b/drivers/misc/mei/Makefile @@ -31,6 +31,7 @@ CFLAGS_mei-trace.o =3D -I$(src) obj-$(CONFIG_INTEL_MEI_HDCP) +=3D hdcp/ obj-$(CONFIG_INTEL_MEI_PXP) +=3D pxp/ obj-$(CONFIG_INTEL_MEI_GSC_PROXY) +=3D gsc_proxy/ +obj-$(CONFIG_INTEL_MEI_LATE_BIND) +=3D late_bind/ =20 obj-$(CONFIG_INTEL_MEI_VSC_HW) +=3D mei-vsc-hw.o mei-vsc-hw-y :=3D vsc-tp.o diff --git a/drivers/misc/mei/late_bind/Kconfig b/drivers/misc/mei/late_bin= d/Kconfig new file mode 100644 index 000000000000..65c7180c5678 --- /dev/null +++ b/drivers/misc/mei/late_bind/Kconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright (c) 2025, Intel Corporation. All rights reserved. +# +config INTEL_MEI_LATE_BIND + tristate "Intel late binding support on ME Interface" + select INTEL_MEI_ME + depends on DRM_XE + help + MEI Support for Late Binding for Intel graphics card. + + Enables the ME FW interfaces for Late Binding feature, + allowing loading of firmware for the devices like Fan + Controller during by Intel Xe driver. diff --git a/drivers/misc/mei/late_bind/Makefile b/drivers/misc/mei/late_bi= nd/Makefile new file mode 100644 index 000000000000..a0aeda5853f0 --- /dev/null +++ b/drivers/misc/mei/late_bind/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (c) 2025, Intel Corporation. All rights reserved. +# +# Makefile - Late Binding client driver for Intel MEI Bus Driver. + +subdir-ccflags-y +=3D -I$(srctree)/drivers/misc/mei/ + +obj-$(CONFIG_INTEL_MEI_LATE_BIND) +=3D mei_late_bind.o diff --git a/drivers/misc/mei/late_bind/mei_late_bind.c b/drivers/misc/mei/= late_bind/mei_late_bind.c new file mode 100644 index 000000000000..cb985f32309e --- /dev/null +++ b/drivers/misc/mei/late_bind/mei_late_bind.c @@ -0,0 +1,264 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Intel Corporation + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mkhi.h" + +#define GFX_SRV_MKHI_LATE_BINDING_CMD 0x12 +#define GFX_SRV_MKHI_LATE_BINDING_RSP (GFX_SRV_MKHI_LATE_BINDING_CMD | 0x8= 0) + +#define LATE_BIND_SEND_TIMEOUT_MSEC 3000 +#define LATE_BIND_RECV_TIMEOUT_MSEC 3000 + +/** + * struct csc_heci_late_bind_req - late binding request + * @header: @ref mkhi_msg_hdr + * @type: type of the late binding payload + * @flags: flags to be passed to the firmware + * @reserved: reserved field + * @payload_size: size of the payload data in bytes + * @payload: data to be sent to the firmware + */ +struct csc_heci_late_bind_req { + struct mkhi_msg_hdr header; + u32 type; + u32 flags; + u32 reserved[2]; + u32 payload_size; + u8 payload[] __counted_by(payload_size); +} __packed; + +/** + * struct csc_heci_late_bind_rsp - late binding response + * @header: @ref mkhi_msg_hdr + * @type: type of the late binding payload + * @reserved: reserved field + * @status: status of the late binding command execution by firmware + */ +struct csc_heci_late_bind_rsp { + struct mkhi_msg_hdr header; + u32 type; + u32 reserved[2]; + u32 status; +} __packed; + +static int mei_late_bind_check_response(const struct device *dev, const st= ruct mkhi_msg_hdr *hdr) +{ + if (hdr->group_id !=3D MKHI_GROUP_ID_GFX) { + dev_err(dev, "Mismatch group id: 0x%x instead of 0x%x\n", + hdr->group_id, MKHI_GROUP_ID_GFX); + return -EINVAL; + } + + if (hdr->command !=3D GFX_SRV_MKHI_LATE_BINDING_RSP) { + dev_err(dev, "Mismatch command: 0x%x instead of 0x%x\n", + hdr->command, GFX_SRV_MKHI_LATE_BINDING_RSP); + return -EINVAL; + } + + return 0; +} + +/** + * mei_late_bind_push_config - Sends a config to the firmware. + * @dev: device struct corresponding to the mei device + * @type: payload type + * @flags: payload flags + * @payload: payload buffer + * @payload_size: payload buffer size + * + * Return: 0 success, negative errno value on transport failure, + * positive status returned by FW + */ +static int mei_late_bind_push_config(struct device *dev, u32 type, u32 fla= gs, + const void *payload, size_t payload_size) +{ + struct mei_cl_device *cldev; + struct csc_heci_late_bind_req *req =3D NULL; + struct csc_heci_late_bind_rsp rsp; + size_t req_size; + int ret; + + if (!dev || !payload || !payload_size) + return -EINVAL; + + cldev =3D to_mei_cl_device(dev); + + ret =3D mei_cldev_enable(cldev); + if (ret < 0) { + dev_dbg(dev, "mei_cldev_enable failed. %d\n", ret); + return ret; + } + + req_size =3D struct_size(req, payload, payload_size); + if (req_size > mei_cldev_mtu(cldev)) { + dev_err(dev, "Payload is too big %zu\n", payload_size); + ret =3D -EMSGSIZE; + goto end; + } + + req =3D kmalloc(req_size, GFP_KERNEL); + if (!req) { + ret =3D -ENOMEM; + goto end; + } + + req->header.group_id =3D MKHI_GROUP_ID_GFX; + req->header.command =3D GFX_SRV_MKHI_LATE_BINDING_CMD; + req->type =3D type; + req->flags =3D flags; + req->reserved[0] =3D 0; + req->reserved[1] =3D 0; + req->payload_size =3D payload_size; + memcpy(req->payload, payload, payload_size); + + ret =3D mei_cldev_send_timeout(cldev, (void *)req, req_size, LATE_BIND_SE= ND_TIMEOUT_MSEC); + if (ret < 0) { + dev_err(dev, "mei_cldev_send failed. %d\n", ret); + goto end; + } + ret =3D mei_cldev_recv_timeout(cldev, (void *)&rsp, sizeof(rsp), LATE_BIN= D_RECV_TIMEOUT_MSEC); + if (ret < 0) { + dev_err(dev, "mei_cldev_recv failed. %d\n", ret); + goto end; + } + ret =3D mei_late_bind_check_response(dev, &rsp.header); + if (ret) { + dev_err(dev, "bad result response from the firmware: 0x%x\n", + *(uint32_t *)&rsp.header); + goto end; + } + ret =3D (int)rsp.status; + dev_dbg(dev, "%s status =3D %d\n", __func__, ret); + +end: + mei_cldev_disable(cldev); + kfree(req); + return ret; +} + +static const struct late_bind_component_ops mei_late_bind_ops =3D { + .owner =3D THIS_MODULE, + .push_config =3D mei_late_bind_push_config, +}; + +static int mei_component_master_bind(struct device *dev) +{ + return component_bind_all(dev, (void *)&mei_late_bind_ops); +} + +static void mei_component_master_unbind(struct device *dev) +{ + component_unbind_all(dev, (void *)&mei_late_bind_ops); +} + +static const struct component_master_ops mei_component_master_ops =3D { + .bind =3D mei_component_master_bind, + .unbind =3D mei_component_master_unbind, +}; + +/** + * mei_late_bind_component_match - compare function for matching mei late = bind. + * + * The function checks if requested is Intel VGA device + * and the parent of requester and the grand parent of mei_if are the s= ame + * device. + * + * @dev: master device + * @subcomponent: subcomponent to match (I915_COMPONENT_LATE_BIND) + * @data: compare data (mei late-bind bus device) + * + * Return: + * * 1 - if components match + * * 0 - otherwise + */ +static int mei_late_bind_component_match(struct device *dev, int subcompon= ent, + void *data) +{ + struct device *base =3D data; + struct pci_dev *pdev; + + if (!dev) + return 0; + + if (!dev_is_pci(dev)) + return 0; + + pdev =3D to_pci_dev(dev); + + if (pdev->vendor !=3D PCI_VENDOR_ID_INTEL) + return 0; + + if (pdev->class !=3D (PCI_CLASS_DISPLAY_VGA << 8) || + pdev->class !=3D (PCI_CLASS_DISPLAY_OTHER << 8)) + return 0; + + if (subcomponent !=3D I915_COMPONENT_LATE_BIND) + return 0; + + base =3D base->parent; + if (!base) /* mei device */ + return 0; + + base =3D base->parent; /* pci device */ + + return !!base && dev =3D=3D base; +} + +static int mei_late_bind_probe(struct mei_cl_device *cldev, + const struct mei_cl_device_id *id) +{ + struct component_match *master_match =3D NULL; + int ret; + + component_match_add_typed(&cldev->dev, &master_match, + mei_late_bind_component_match, &cldev->dev); + if (IS_ERR_OR_NULL(master_match)) + return -ENOMEM; + + ret =3D component_master_add_with_match(&cldev->dev, + &mei_component_master_ops, + master_match); + if (ret < 0) + dev_err(&cldev->dev, "Master comp add failed %d\n", ret); + + return ret; +} + +static void mei_late_bind_remove(struct mei_cl_device *cldev) +{ + component_master_del(&cldev->dev, &mei_component_master_ops); +} + +#define MEI_GUID_MKHI UUID_LE(0xe2c2afa2, 0x3817, 0x4d19, \ + 0x9d, 0x95, 0x6, 0xb1, 0x6b, 0x58, 0x8a, 0x5d) + +static struct mei_cl_device_id mei_late_bind_tbl[] =3D { + { .uuid =3D MEI_GUID_MKHI, .version =3D MEI_CL_VERSION_ANY }, + { } +}; +MODULE_DEVICE_TABLE(mei, mei_late_bind_tbl); + +static struct mei_cl_driver mei_late_bind_driver =3D { + .id_table =3D mei_late_bind_tbl, + .name =3D KBUILD_MODNAME, + .probe =3D mei_late_bind_probe, + .remove =3D mei_late_bind_remove, +}; + +module_mei_cl_driver(mei_late_bind_driver); + +MODULE_AUTHOR("Intel Corporation"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("MEI Late Binding"); diff --git a/include/drm/intel/i915_component.h b/include/drm/intel/i915_co= mponent.h index 4ea3b17aa143..4945044d41e6 100644 --- a/include/drm/intel/i915_component.h +++ b/include/drm/intel/i915_component.h @@ -31,6 +31,7 @@ enum i915_component_type { I915_COMPONENT_HDCP, I915_COMPONENT_PXP, I915_COMPONENT_GSC_PROXY, + I915_COMPONENT_LATE_BIND, }; =20 /* MAX_PORT is the number of port diff --git a/include/drm/intel/late_bind_mei_interface.h b/include/drm/inte= l/late_bind_mei_interface.h new file mode 100644 index 000000000000..2c53657ce91b --- /dev/null +++ b/include/drm/intel/late_bind_mei_interface.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (c) 2025 Intel Corporation + */ + +#ifndef _LATE_BIND_MEI_INTERFACE_H_ +#define _LATE_BIND_MEI_INTERFACE_H_ + +#include + +struct device; +struct module; + +/** + * Late Binding flags + * Persistent across warm reset + */ +#define CSC_LATE_BINDING_FLAGS_IS_PERSISTENT BIT(0) + +/** + * xe_late_bind_fw_type - enum to determine late binding fw type + */ +enum late_bind_type { + CSC_LATE_BINDING_TYPE_FAN_CONTROL =3D 1, +}; + +/** + * struct late_bind_component_ops - ops for Late Binding services. + * @owner: Module providing the ops + * @push_config: Sends a config to FW. + */ +struct late_bind_component_ops { + struct module *owner; + + /** + * @push_config: Sends a config to FW. + * @dev: device struct corresponding to the mei device + * @type: payload type + * @flags: payload flags + * @payload: payload buffer + * @payload_size: payload buffer size + * + * Return: 0 success, negative errno value on transport failure, + * positive status returned by FW + */ + int (*push_config)(struct device *dev, u32 type, u32 flags, + const void *payload, size_t payload_size); +}; + +#endif /* _LATE_BIND_MEI_INTERFACE_H_ */ --=20 2.34.1