From nobody Thu Oct 9 08:49:41 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1247F2F4314 for ; Wed, 18 Jun 2025 18:56:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750272996; cv=none; b=fFMlbF8YE0xGDFmWGUJkEKGPU8c+tF73O9MPWxXMcklU3+KYjgprKCrx/oE+UT/vkNeEdRjaBQfgosTVZ1zaHehzAdaHRZnlYONsSzUtASrcBYrwccDH7WNGpsbhh2+sf+olsxS1RFX9q1VKqiCYQxcxGGtr1XVWlgmyz5Nu11E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750272996; c=relaxed/simple; bh=u16CpbdUihPkyI+FiM2IX3TbeuU1zDLWDn5AwsQR/6k=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=EyEyPJ1uEknL/4b12VQhCW1pxDN3VZMS86OIrTIdCxnVfmRlEbUZLglhubmKlTfUzlntuoRst8e0UijvF3zwptnwR4SCsB1bixwlLiEZQopQQjmR/7qyd+bTVWv5YQkmTy7dZc/pVseEUMycXrpHsdcpNGkYHb6G1leRKU4hgpA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=hZ3D7c+o; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="hZ3D7c+o" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750272995; x=1781808995; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=u16CpbdUihPkyI+FiM2IX3TbeuU1zDLWDn5AwsQR/6k=; b=hZ3D7c+ob4cfFBexFyla9MwMjThUzzoSr/TJrD/71/KwiMOVcqU4MwLU f1L0KUFxuoNw0ey4qGozywDIzVRXirQ2E2V5ym8qHOGlTEkJY2A06zR3Y Dvzvg5cbFkJfCjFo5T/UlPPUW/y613EY9iJ47fvmoybESCgqNIlAS8/q9 ai3iRlcIH7trv7BnO9ARGWgRKMoWkk1JBhBLO7Ki0F702clumICnW7xxV Mn5eh6M2z4OcN4FnSFDQZ/HmnEfsBUovqx45N6wDjL++8T7tNuH6a3rqE HumOW3UfllSDBRElh0MQYGSw/twEQ9oEArMI9i7ajN0/BYuKZIA/5HoVp A==; X-CSE-ConnectionGUID: GaBEwAeITeWbdquyWEGUvw== X-CSE-MsgGUID: 3Y2CbsEfTtK0FCta5tgRvA== X-IronPort-AV: E=McAfee;i="6800,10657,11468"; a="52210178" X-IronPort-AV: E=Sophos;i="6.16,246,1744095600"; d="scan'208";a="52210178" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2025 11:56:34 -0700 X-CSE-ConnectionGUID: ZUW7eUecT9SOJ6zvb+6VbQ== X-CSE-MsgGUID: qWtzsz77ROiLCoditM3w/Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,246,1744095600"; d="scan'208";a="153951464" Received: from unknown (HELO bnilawar-desk2.iind.intel.com) ([10.190.239.41]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2025 11:56:32 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com, jgg@nvidia.com Subject: [PATCH v3 01/10] mei: bus: add mei_cldev_mtu interface Date: Thu, 19 Jun 2025 00:29:58 +0530 Message-Id: <20250618190007.2932322-2-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618190007.2932322-1-badal.nilawar@intel.com> References: <20250618190007.2932322-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Alexander Usyskin Allow to bus client to obtain client mtu. Signed-off-by: Alexander Usyskin Signed-off-by: Badal Nilawar Reviewed-by: Umesh Nerlige Ramappa --- drivers/misc/mei/bus.c | 13 +++++++++++++ include/linux/mei_cl_bus.h | 1 + 2 files changed, 14 insertions(+) diff --git a/drivers/misc/mei/bus.c b/drivers/misc/mei/bus.c index 67176caf5416..f860b1b6eda0 100644 --- a/drivers/misc/mei/bus.c +++ b/drivers/misc/mei/bus.c @@ -614,6 +614,19 @@ u8 mei_cldev_ver(const struct mei_cl_device *cldev) } EXPORT_SYMBOL_GPL(mei_cldev_ver); =20 +/** + * mei_cldev_mtu - max message that client can send and receive + * + * @cldev: mei client device + * + * Return: mtu or 0 if client is not connected + */ +size_t mei_cldev_mtu(const struct mei_cl_device *cldev) +{ + return mei_cl_mtu(cldev->cl); +} +EXPORT_SYMBOL_GPL(mei_cldev_mtu); + /** * mei_cldev_enabled - check whether the device is enabled * diff --git a/include/linux/mei_cl_bus.h b/include/linux/mei_cl_bus.h index 725fd7727422..a82755e1fc40 100644 --- a/include/linux/mei_cl_bus.h +++ b/include/linux/mei_cl_bus.h @@ -113,6 +113,7 @@ int mei_cldev_register_notif_cb(struct mei_cl_device *c= ldev, mei_cldev_cb_t notif_cb); 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d="scan'208";a="153951538" Received: from unknown (HELO bnilawar-desk2.iind.intel.com) ([10.190.239.41]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2025 11:56:34 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com, jgg@nvidia.com Subject: [PATCH v3 02/10] mei: late_bind: add late binding component driver Date: Thu, 19 Jun 2025 00:29:59 +0530 Message-Id: <20250618190007.2932322-3-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618190007.2932322-1-badal.nilawar@intel.com> References: <20250618190007.2932322-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Alexander Usyskin Add late binding component driver. It allows pushing the late binding configuration from, for example, the Xe graphics driver to the Intel discrete graphics card's CSE device. Signed-off-by: Alexander Usyskin Signed-off-by: Badal Nilawar --- v2: - Use generic naming (Jani) - Drop xe_late_bind_component struct to move to xe code (Daniele/Sasha) v3: - Updated kconfig description - Move CSC late binding specific flags/defines to late_bind_mei_interface.= h (Daniele) v4: - Add match for PCI_CLASS_DISPLAY_OTHER to support headless cards (Anshuma= n) --- drivers/misc/mei/Kconfig | 1 + drivers/misc/mei/Makefile | 1 + drivers/misc/mei/late_bind/Kconfig | 13 + drivers/misc/mei/late_bind/Makefile | 9 + drivers/misc/mei/late_bind/mei_late_bind.c | 264 ++++++++++++++++++++ include/drm/intel/i915_component.h | 1 + include/drm/intel/late_bind_mei_interface.h | 50 ++++ 7 files changed, 339 insertions(+) create mode 100644 drivers/misc/mei/late_bind/Kconfig create mode 100644 drivers/misc/mei/late_bind/Makefile create mode 100644 drivers/misc/mei/late_bind/mei_late_bind.c create mode 100644 include/drm/intel/late_bind_mei_interface.h diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig index 7575fee96cc6..771becc68095 100644 --- a/drivers/misc/mei/Kconfig +++ b/drivers/misc/mei/Kconfig @@ -84,5 +84,6 @@ config INTEL_MEI_VSC source "drivers/misc/mei/hdcp/Kconfig" source "drivers/misc/mei/pxp/Kconfig" source "drivers/misc/mei/gsc_proxy/Kconfig" +source "drivers/misc/mei/late_bind/Kconfig" =20 endif diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile index 6f9fdbf1a495..84bfde888d81 100644 --- a/drivers/misc/mei/Makefile +++ b/drivers/misc/mei/Makefile @@ -31,6 +31,7 @@ CFLAGS_mei-trace.o =3D -I$(src) obj-$(CONFIG_INTEL_MEI_HDCP) +=3D hdcp/ obj-$(CONFIG_INTEL_MEI_PXP) +=3D pxp/ obj-$(CONFIG_INTEL_MEI_GSC_PROXY) +=3D gsc_proxy/ +obj-$(CONFIG_INTEL_MEI_LATE_BIND) +=3D late_bind/ =20 obj-$(CONFIG_INTEL_MEI_VSC_HW) +=3D mei-vsc-hw.o mei-vsc-hw-y :=3D vsc-tp.o diff --git a/drivers/misc/mei/late_bind/Kconfig b/drivers/misc/mei/late_bin= d/Kconfig new file mode 100644 index 000000000000..65c7180c5678 --- /dev/null +++ b/drivers/misc/mei/late_bind/Kconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright (c) 2025, Intel Corporation. All rights reserved. +# +config INTEL_MEI_LATE_BIND + tristate "Intel late binding support on ME Interface" + select INTEL_MEI_ME + depends on DRM_XE + help + MEI Support for Late Binding for Intel graphics card. + + Enables the ME FW interfaces for Late Binding feature, + allowing loading of firmware for the devices like Fan + Controller during by Intel Xe driver. diff --git a/drivers/misc/mei/late_bind/Makefile b/drivers/misc/mei/late_bi= nd/Makefile new file mode 100644 index 000000000000..a0aeda5853f0 --- /dev/null +++ b/drivers/misc/mei/late_bind/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (c) 2025, Intel Corporation. All rights reserved. +# +# Makefile - Late Binding client driver for Intel MEI Bus Driver. + +subdir-ccflags-y +=3D -I$(srctree)/drivers/misc/mei/ + +obj-$(CONFIG_INTEL_MEI_LATE_BIND) +=3D mei_late_bind.o diff --git a/drivers/misc/mei/late_bind/mei_late_bind.c b/drivers/misc/mei/= late_bind/mei_late_bind.c new file mode 100644 index 000000000000..cb985f32309e --- /dev/null +++ b/drivers/misc/mei/late_bind/mei_late_bind.c @@ -0,0 +1,264 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Intel Corporation + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mkhi.h" + +#define GFX_SRV_MKHI_LATE_BINDING_CMD 0x12 +#define GFX_SRV_MKHI_LATE_BINDING_RSP (GFX_SRV_MKHI_LATE_BINDING_CMD | 0x8= 0) + +#define LATE_BIND_SEND_TIMEOUT_MSEC 3000 +#define LATE_BIND_RECV_TIMEOUT_MSEC 3000 + +/** + * struct csc_heci_late_bind_req - late binding request + * @header: @ref mkhi_msg_hdr + * @type: type of the late binding payload + * @flags: flags to be passed to the firmware + * @reserved: reserved field + * @payload_size: size of the payload data in bytes + * @payload: data to be sent to the firmware + */ +struct csc_heci_late_bind_req { + struct mkhi_msg_hdr header; + u32 type; + u32 flags; + u32 reserved[2]; + u32 payload_size; + u8 payload[] __counted_by(payload_size); +} __packed; + +/** + * struct csc_heci_late_bind_rsp - late binding response + * @header: @ref mkhi_msg_hdr + * @type: type of the late binding payload + * @reserved: reserved field + * @status: status of the late binding command execution by firmware + */ +struct csc_heci_late_bind_rsp { + struct mkhi_msg_hdr header; + u32 type; + u32 reserved[2]; + u32 status; +} __packed; + +static int mei_late_bind_check_response(const struct device *dev, const st= ruct mkhi_msg_hdr *hdr) +{ + if (hdr->group_id !=3D MKHI_GROUP_ID_GFX) { + dev_err(dev, "Mismatch group id: 0x%x instead of 0x%x\n", + hdr->group_id, MKHI_GROUP_ID_GFX); + return -EINVAL; + } + + if (hdr->command !=3D GFX_SRV_MKHI_LATE_BINDING_RSP) { + dev_err(dev, "Mismatch command: 0x%x instead of 0x%x\n", + hdr->command, GFX_SRV_MKHI_LATE_BINDING_RSP); + return -EINVAL; + } + + return 0; +} + +/** + * mei_late_bind_push_config - Sends a config to the firmware. + * @dev: device struct corresponding to the mei device + * @type: payload type + * @flags: payload flags + * @payload: payload buffer + * @payload_size: payload buffer size + * + * Return: 0 success, negative errno value on transport failure, + * positive status returned by FW + */ +static int mei_late_bind_push_config(struct device *dev, u32 type, u32 fla= gs, + const void *payload, size_t payload_size) +{ + struct mei_cl_device *cldev; + struct csc_heci_late_bind_req *req =3D NULL; + struct csc_heci_late_bind_rsp rsp; + size_t req_size; + int ret; + + if (!dev || !payload || !payload_size) + return -EINVAL; + + cldev =3D to_mei_cl_device(dev); + + ret =3D mei_cldev_enable(cldev); + if (ret < 0) { + dev_dbg(dev, "mei_cldev_enable failed. %d\n", ret); + return ret; + } + + req_size =3D struct_size(req, payload, payload_size); + if (req_size > mei_cldev_mtu(cldev)) { + dev_err(dev, "Payload is too big %zu\n", payload_size); + ret =3D -EMSGSIZE; + goto end; + } + + req =3D kmalloc(req_size, GFP_KERNEL); + if (!req) { + ret =3D -ENOMEM; + goto end; + } + + req->header.group_id =3D MKHI_GROUP_ID_GFX; + req->header.command =3D GFX_SRV_MKHI_LATE_BINDING_CMD; + req->type =3D type; + req->flags =3D flags; + req->reserved[0] =3D 0; + req->reserved[1] =3D 0; + req->payload_size =3D payload_size; + memcpy(req->payload, payload, payload_size); + + ret =3D mei_cldev_send_timeout(cldev, (void *)req, req_size, LATE_BIND_SE= ND_TIMEOUT_MSEC); + if (ret < 0) { + dev_err(dev, "mei_cldev_send failed. %d\n", ret); + goto end; + } + ret =3D mei_cldev_recv_timeout(cldev, (void *)&rsp, sizeof(rsp), LATE_BIN= D_RECV_TIMEOUT_MSEC); + if (ret < 0) { + dev_err(dev, "mei_cldev_recv failed. %d\n", ret); + goto end; + } + ret =3D mei_late_bind_check_response(dev, &rsp.header); + if (ret) { + dev_err(dev, "bad result response from the firmware: 0x%x\n", + *(uint32_t *)&rsp.header); + goto end; + } + ret =3D (int)rsp.status; + dev_dbg(dev, "%s status =3D %d\n", __func__, ret); + +end: + mei_cldev_disable(cldev); + kfree(req); + return ret; +} + +static const struct late_bind_component_ops mei_late_bind_ops =3D { + .owner =3D THIS_MODULE, + .push_config =3D mei_late_bind_push_config, +}; + +static int mei_component_master_bind(struct device *dev) +{ + return component_bind_all(dev, (void *)&mei_late_bind_ops); +} + +static void mei_component_master_unbind(struct device *dev) +{ + component_unbind_all(dev, (void *)&mei_late_bind_ops); +} + +static const struct component_master_ops mei_component_master_ops =3D { + .bind =3D mei_component_master_bind, + .unbind =3D mei_component_master_unbind, +}; + +/** + * mei_late_bind_component_match - compare function for matching mei late = bind. + * + * The function checks if requested is Intel VGA device + * and the parent of requester and the grand parent of mei_if are the s= ame + * device. + * + * @dev: master device + * @subcomponent: subcomponent to match (I915_COMPONENT_LATE_BIND) + * @data: compare data (mei late-bind bus device) + * + * Return: + * * 1 - if components match + * * 0 - otherwise + */ +static int mei_late_bind_component_match(struct device *dev, int subcompon= ent, + void *data) +{ + struct device *base =3D data; + struct pci_dev *pdev; + + if (!dev) + return 0; + + if (!dev_is_pci(dev)) + return 0; + + pdev =3D to_pci_dev(dev); + + if (pdev->vendor !=3D PCI_VENDOR_ID_INTEL) + return 0; + + if (pdev->class !=3D (PCI_CLASS_DISPLAY_VGA << 8) || + pdev->class !=3D (PCI_CLASS_DISPLAY_OTHER << 8)) + return 0; + + if (subcomponent !=3D I915_COMPONENT_LATE_BIND) + return 0; + + base =3D base->parent; + if (!base) /* mei device */ + return 0; + + base =3D base->parent; /* pci device */ + + return !!base && dev =3D=3D base; +} + +static int mei_late_bind_probe(struct mei_cl_device *cldev, + const struct mei_cl_device_id *id) +{ + struct component_match *master_match =3D NULL; + int ret; + + component_match_add_typed(&cldev->dev, &master_match, + mei_late_bind_component_match, &cldev->dev); + if (IS_ERR_OR_NULL(master_match)) + return -ENOMEM; + + ret =3D component_master_add_with_match(&cldev->dev, + &mei_component_master_ops, + master_match); + if (ret < 0) + dev_err(&cldev->dev, "Master comp add failed %d\n", ret); + + return ret; +} + +static void mei_late_bind_remove(struct mei_cl_device *cldev) +{ + component_master_del(&cldev->dev, &mei_component_master_ops); +} + +#define MEI_GUID_MKHI UUID_LE(0xe2c2afa2, 0x3817, 0x4d19, \ + 0x9d, 0x95, 0x6, 0xb1, 0x6b, 0x58, 0x8a, 0x5d) + +static struct mei_cl_device_id mei_late_bind_tbl[] =3D { + { .uuid =3D MEI_GUID_MKHI, .version =3D MEI_CL_VERSION_ANY }, + { } +}; +MODULE_DEVICE_TABLE(mei, mei_late_bind_tbl); + +static struct mei_cl_driver mei_late_bind_driver =3D { + .id_table =3D mei_late_bind_tbl, + .name =3D KBUILD_MODNAME, + .probe =3D mei_late_bind_probe, + .remove =3D mei_late_bind_remove, +}; + +module_mei_cl_driver(mei_late_bind_driver); + +MODULE_AUTHOR("Intel Corporation"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("MEI Late Binding"); diff --git a/include/drm/intel/i915_component.h b/include/drm/intel/i915_co= mponent.h index 4ea3b17aa143..4945044d41e6 100644 --- a/include/drm/intel/i915_component.h +++ b/include/drm/intel/i915_component.h @@ -31,6 +31,7 @@ enum i915_component_type { I915_COMPONENT_HDCP, I915_COMPONENT_PXP, I915_COMPONENT_GSC_PROXY, + I915_COMPONENT_LATE_BIND, }; =20 /* MAX_PORT is the number of port diff --git a/include/drm/intel/late_bind_mei_interface.h b/include/drm/inte= l/late_bind_mei_interface.h new file mode 100644 index 000000000000..2c53657ce91b --- /dev/null +++ b/include/drm/intel/late_bind_mei_interface.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (c) 2025 Intel Corporation + */ + +#ifndef _LATE_BIND_MEI_INTERFACE_H_ +#define _LATE_BIND_MEI_INTERFACE_H_ + +#include + +struct device; +struct module; + +/** + * Late Binding flags + * Persistent across warm reset + */ +#define CSC_LATE_BINDING_FLAGS_IS_PERSISTENT BIT(0) + +/** + * xe_late_bind_fw_type - enum to determine late binding fw type + */ +enum late_bind_type { + CSC_LATE_BINDING_TYPE_FAN_CONTROL =3D 1, +}; + +/** + * struct late_bind_component_ops - ops for Late Binding services. + * @owner: Module providing the ops + * @push_config: Sends a config to FW. + */ +struct late_bind_component_ops { + struct module *owner; + + /** + * @push_config: Sends a config to FW. + * @dev: device struct corresponding to the mei device + * @type: payload type + * @flags: payload flags + * @payload: payload buffer + * @payload_size: payload buffer size + * + * Return: 0 success, negative errno value on transport failure, + * positive status returned by FW + */ + int (*push_config)(struct device *dev, u32 type, u32 flags, + const void *payload, size_t payload_size); +}; + +#endif /* _LATE_BIND_MEI_INTERFACE_H_ */ --=20 2.34.1 From nobody Thu Oct 9 08:49:41 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3EE62F547D for ; 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a="52210190" X-IronPort-AV: E=Sophos;i="6.16,246,1744095600"; d="scan'208";a="52210190" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2025 11:56:40 -0700 X-CSE-ConnectionGUID: APcRPjIAT1qOtugCp9WE8A== X-CSE-MsgGUID: PwQXHnqMRBq44Mmzoo4hdQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,246,1744095600"; d="scan'208";a="153951622" Received: from unknown (HELO bnilawar-desk2.iind.intel.com) ([10.190.239.41]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2025 11:56:37 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com, jgg@nvidia.com Subject: [PATCH v3 03/10] drm/xe/xe_late_bind_fw: Introducing xe_late_bind_fw Date: Thu, 19 Jun 2025 00:30:00 +0530 Message-Id: <20250618190007.2932322-4-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618190007.2932322-1-badal.nilawar@intel.com> References: <20250618190007.2932322-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Introducing xe_late_bind_fw to enable firmware loading for the devices, such as the fan controller, during the driver probe. Typically, firmware for such devices are part of IFWI flash image but can be replaced at probe after OEM tuning. This patch binds mei late binding component to enable firmware loading. v2: - Add devm_add_action_or_reset to remove the component (Daniele) - Add INTEL_MEI_GSC check in xe_late_bind_init() (Daniele) v3: - Fail driver probe if late bind initialization fails, add has_late_bind flag (Daniele) Signed-off-by: Badal Nilawar Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/xe/Makefile | 1 + drivers/gpu/drm/xe/xe_device.c | 5 ++ drivers/gpu/drm/xe/xe_device_types.h | 6 ++ drivers/gpu/drm/xe/xe_late_bind_fw.c | 93 ++++++++++++++++++++++ drivers/gpu/drm/xe/xe_late_bind_fw.h | 15 ++++ drivers/gpu/drm/xe/xe_late_bind_fw_types.h | 39 +++++++++ drivers/gpu/drm/xe/xe_pci.c | 3 + 7 files changed, 162 insertions(+) create mode 100644 drivers/gpu/drm/xe/xe_late_bind_fw.c create mode 100644 drivers/gpu/drm/xe/xe_late_bind_fw.h create mode 100644 drivers/gpu/drm/xe/xe_late_bind_fw_types.h diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index f5f5775acdc0..001384ca7357 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -76,6 +76,7 @@ xe-y +=3D xe_bb.o \ xe_hw_fence.o \ xe_irq.o \ xe_lrc.o \ + xe_late_bind_fw.o \ xe_migrate.o \ xe_mmio.o \ xe_mocs.o \ diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c index 7d9a31868ea9..13cf5f90d09e 100644 --- a/drivers/gpu/drm/xe/xe_device.c +++ b/drivers/gpu/drm/xe/xe_device.c @@ -43,6 +43,7 @@ #include "xe_hw_engine_group.h" #include "xe_hwmon.h" #include "xe_irq.h" +#include "xe_late_bind_fw.h" #include "xe_memirq.h" #include "xe_mmio.h" #include "xe_module.h" @@ -889,6 +890,10 @@ int xe_device_probe(struct xe_device *xe) if (err) return err; =20 + err =3D xe_late_bind_init(&xe->late_bind); + if (err && err !=3D -ENODEV) + return err; + err =3D xe_oa_init(xe); if (err) return err; diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_d= evice_types.h index a504b8ea6f3f..facafe2eea5c 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -16,6 +16,7 @@ #include "xe_devcoredump_types.h" #include "xe_heci_gsc.h" #include "xe_lmtt_types.h" +#include "xe_late_bind_fw_types.h" #include "xe_memirq_types.h" #include "xe_oa_types.h" #include "xe_platform_types.h" @@ -323,6 +324,8 @@ struct xe_device { u8 has_heci_cscfi:1; /** @info.has_heci_gscfi: device has heci gscfi */ u8 has_heci_gscfi:1; + /** @info.has_late_bind: Device has firmware late binding support */ + u8 has_late_bind:1; /** @info.has_llc: Device has a shared CPU+GPU last level cache */ u8 has_llc:1; /** @info.has_mbx_power_limits: Device has support to manage power limit= s using @@ -552,6 +555,9 @@ struct xe_device { /** @heci_gsc: graphics security controller */ struct xe_heci_gsc heci_gsc; =20 + /** @late_bind: xe mei late bind interface */ + struct xe_late_bind late_bind; + /** @oa: oa observation subsystem */ struct xe_oa oa; =20 diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.c b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.c new file mode 100644 index 000000000000..52cb295b7df6 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright =C2=A9 2025 Intel Corporation + */ + +#include +#include + +#include +#include +#include +#include + +#include "xe_device.h" +#include "xe_late_bind_fw.h" + +static struct xe_device * +late_bind_to_xe(struct xe_late_bind *late_bind) +{ + return container_of(late_bind, struct xe_device, late_bind); +} + +static int xe_late_bind_component_bind(struct device *xe_kdev, + struct device *mei_kdev, void *data) +{ + struct xe_device *xe =3D kdev_to_xe_device(xe_kdev); + struct xe_late_bind *late_bind =3D &xe->late_bind; + + mutex_lock(&late_bind->mutex); + late_bind->component.ops =3D data; + late_bind->component.mei_dev =3D mei_kdev; + mutex_unlock(&late_bind->mutex); + + return 0; +} + +static void xe_late_bind_component_unbind(struct device *xe_kdev, + struct device *mei_kdev, void *data) +{ + struct xe_device *xe =3D kdev_to_xe_device(xe_kdev); + struct xe_late_bind *late_bind =3D &xe->late_bind; + + mutex_lock(&late_bind->mutex); + late_bind->component.ops =3D NULL; + mutex_unlock(&late_bind->mutex); +} + +static const struct component_ops xe_late_bind_component_ops =3D { + .bind =3D xe_late_bind_component_bind, + .unbind =3D xe_late_bind_component_unbind, +}; + +static void xe_late_bind_remove(void *arg) +{ + struct xe_late_bind *late_bind =3D arg; + struct xe_device *xe =3D late_bind_to_xe(late_bind); + + component_del(xe->drm.dev, &xe_late_bind_component_ops); + late_bind->component_added =3D false; + mutex_destroy(&late_bind->mutex); +} + +/** + * xe_late_bind_init() - add xe mei late binding component + * + * Return: 0 if the initialization was successful, a negative errno otherw= ise. + */ +int xe_late_bind_init(struct xe_late_bind *late_bind) +{ + struct xe_device *xe =3D late_bind_to_xe(late_bind); + int err; + + if (!xe->info.has_late_bind) + return 0; + + mutex_init(&late_bind->mutex); + + if (!IS_ENABLED(CONFIG_INTEL_MEI_LATE_BIND) || !IS_ENABLED(CONFIG_INTEL_M= EI_GSC)) { + drm_info(&xe->drm, "Can't init xe mei late bind missing mei component\n"= ); + return -ENODEV; + } + + err =3D component_add_typed(xe->drm.dev, &xe_late_bind_component_ops, + I915_COMPONENT_LATE_BIND); + if (err < 0) { + drm_info(&xe->drm, "Failed to add mei late bind component (%pe)\n", ERR_= PTR(err)); + return err; + } + + late_bind->component_added =3D true; + + return devm_add_action_or_reset(xe->drm.dev, xe_late_bind_remove, late_bi= nd); +} diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.h b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.h new file mode 100644 index 000000000000..4c73571c3e62 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright =C2=A9 2025 Intel Corporation + */ + +#ifndef _XE_LATE_BIND_FW_H_ +#define _XE_LATE_BIND_FW_H_ + +#include + +struct xe_late_bind; + +int xe_late_bind_init(struct xe_late_bind *late_bind); + +#endif diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h b/drivers/gpu/drm/x= e/xe_late_bind_fw_types.h new file mode 100644 index 000000000000..ef0a9723bee4 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_late_bind_fw_types.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright =C2=A9 2025 Intel Corporation + */ + +#ifndef _XE_LATE_BIND_TYPES_H_ +#define _XE_LATE_BIND_TYPES_H_ + +#include +#include +#include + +/** + * struct xe_late_bind_component - Late Binding services component + * @mei_dev: device that provide Late Binding service. + * @ops: Ops implemented by Late Binding driver, used by Xe driver. + * + * Communication between Xe and MEI drivers for Late Binding services + */ +struct xe_late_bind_component { + /** @late_bind_component.mei_dev: mei device */ + struct device *mei_dev; + /** @late_bind_component.ops: late binding ops */ + const struct late_bind_component_ops *ops; +}; + +/** + * struct xe_late_bind + */ +struct xe_late_bind { + /** @late_bind.component: struct for communication with mei component */ + struct xe_late_bind_component component; + /** @late_bind.component_added: whether the component has been added */ + bool component_added; + /** @late_bind.mutex: protects the component binding and usage */ + struct mutex mutex; +}; + +#endif diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index 89814b32e585..d54d1d84e240 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -65,6 +65,7 @@ struct xe_device_desc { u8 has_fan_control:1; u8 has_heci_gscfi:1; u8 has_heci_cscfi:1; + u8 has_late_bind:1; u8 has_llc:1; u8 has_mbx_power_limits:1; u8 has_pxp:1; @@ -348,6 +349,7 @@ static const struct xe_device_desc bmg_desc =3D { .has_fan_control =3D true, .has_mbx_power_limits =3D true, .has_heci_cscfi =3D 1, + .has_late_bind =3D true, .needs_scratch =3D true, }; =20 @@ -592,6 +594,7 @@ static int xe_info_init_early(struct xe_device *xe, xe->info.has_mbx_power_limits =3D desc->has_mbx_power_limits; xe->info.has_heci_gscfi =3D desc->has_heci_gscfi; xe->info.has_heci_cscfi =3D desc->has_heci_cscfi; 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18 Jun 2025 11:56:40 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com, jgg@nvidia.com Subject: [PATCH v3 04/10] drm/xe/xe_late_bind_fw: Initialize late binding firmware Date: Thu, 19 Jun 2025 00:30:01 +0530 Message-Id: <20250618190007.2932322-5-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618190007.2932322-1-badal.nilawar@intel.com> References: <20250618190007.2932322-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Search for late binding firmware binaries and populate the meta data of firmware structures. v2 (Daniele): - drm_err if firmware size is more than max pay load size - s/request_firmware/firmware_request_nowarn/ as firmware will not be available for all possible cards v3 (Daniele): - init firmware from within xe_late_bind_init, propagate error - switch late_bind_fw to array to handle multiple firmware types Signed-off-by: Badal Nilawar --- drivers/gpu/drm/xe/xe_late_bind_fw.c | 97 +++++++++++++++++++++- drivers/gpu/drm/xe/xe_late_bind_fw_types.h | 32 +++++++ drivers/misc/mei/late_bind/mei_late_bind.c | 1 - 3 files changed, 128 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.c b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.c index 52cb295b7df6..d416d6cc1fa2 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw.c +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.c @@ -5,6 +5,7 @@ =20 #include #include +#include =20 #include #include @@ -13,6 +14,16 @@ =20 #include "xe_device.h" #include "xe_late_bind_fw.h" +#include "xe_pcode.h" +#include "xe_pcode_api.h" + +static const u32 fw_id_to_type[] =3D { + [FAN_CONTROL_FW_ID] =3D CSC_LATE_BINDING_TYPE_FAN_CONTROL, + }; + +static const char * const fw_id_to_name[] =3D { + [FAN_CONTROL_FW_ID] =3D "fan_control", + }; =20 static struct xe_device * late_bind_to_xe(struct xe_late_bind *late_bind) @@ -20,6 +31,86 @@ late_bind_to_xe(struct xe_late_bind *late_bind) return container_of(late_bind, struct xe_device, late_bind); } =20 +static int xe_late_bind_fw_num_fans(struct xe_late_bind *late_bind) +{ + struct xe_device *xe =3D late_bind_to_xe(late_bind); + struct xe_tile *root_tile =3D xe_device_get_root_tile(xe); + u32 uval; + + if (!xe_pcode_read(root_tile, + PCODE_MBOX(FAN_SPEED_CONTROL, FSC_READ_NUM_FANS, 0), &uval, NULL)) + return uval; + else + return 0; +} + +static int __xe_late_bind_fw_init(struct xe_late_bind *late_bind, u32 fw_i= d) +{ + struct xe_device *xe =3D late_bind_to_xe(late_bind); + struct pci_dev *pdev =3D to_pci_dev(xe->drm.dev); + struct xe_late_bind_fw *lb_fw; + const struct firmware *fw; + u32 num_fans; + int ret; + + if (fw_id >=3D MAX_FW_ID) + return -EINVAL; + + lb_fw =3D &late_bind->late_bind_fw[fw_id]; + + lb_fw->valid =3D false; + lb_fw->id =3D fw_id; + lb_fw->type =3D fw_id_to_type[lb_fw->id]; + lb_fw->flags &=3D ~CSC_LATE_BINDING_FLAGS_IS_PERSISTENT; + + if (lb_fw->type =3D=3D CSC_LATE_BINDING_TYPE_FAN_CONTROL) { + num_fans =3D xe_late_bind_fw_num_fans(late_bind); + drm_dbg(&xe->drm, "Number of Fans: %d\n", num_fans); + if (!num_fans) + return 0; + } + + snprintf(lb_fw->blob_path, sizeof(lb_fw->blob_path), "xe/%s_8086_%04x_%04= x_%04x.bin", + fw_id_to_name[lb_fw->id], pdev->device, + pdev->subsystem_vendor, pdev->subsystem_device); + + drm_dbg(&xe->drm, "Request late binding firmware %s\n", lb_fw->blob_path); + ret =3D firmware_request_nowarn(&fw, lb_fw->blob_path, xe->drm.dev); + if (ret) { + drm_dbg(&xe->drm, "%s late binding fw not available for current device", + fw_id_to_name[lb_fw->id]); + return 0; + } + + if (fw->size > MAX_PAYLOAD_SIZE) { + drm_err(&xe->drm, "Firmware %s size %zu is larger than max pay load size= %u\n", + lb_fw->blob_path, fw->size, MAX_PAYLOAD_SIZE); + release_firmware(fw); + return -ENODATA; + } + + lb_fw->payload_size =3D fw->size; + + memcpy(lb_fw->payload, fw->data, lb_fw->payload_size); + release_firmware(fw); + lb_fw->valid =3D true; + + return 0; +} + +static int xe_late_bind_fw_init(struct xe_late_bind *late_bind) +{ + int ret; + int fw_id; + + for (fw_id =3D 0; fw_id < MAX_FW_ID; fw_id++) { + ret =3D __xe_late_bind_fw_init(late_bind, fw_id); + if (ret) + return ret; + } + return ret; +} + static int xe_late_bind_component_bind(struct device *xe_kdev, struct device *mei_kdev, void *data) { @@ -89,5 +180,9 @@ int xe_late_bind_init(struct xe_late_bind *late_bind) =20 late_bind->component_added =3D true; =20 - return devm_add_action_or_reset(xe->drm.dev, xe_late_bind_remove, late_bi= nd); + err =3D devm_add_action_or_reset(xe->drm.dev, xe_late_bind_remove, late_b= ind); + if (err) + return err; + + return xe_late_bind_fw_init(late_bind); } diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h b/drivers/gpu/drm/x= e/xe_late_bind_fw_types.h index ef0a9723bee4..c6fd33fd5484 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h +++ b/drivers/gpu/drm/xe/xe_late_bind_fw_types.h @@ -10,6 +10,36 @@ #include #include =20 +#define MAX_PAYLOAD_SIZE (1024 * 4) + +/** + * xe_late_bind_fw_id - enum to determine late binding fw index + */ +enum xe_late_bind_fw_id { + FAN_CONTROL_FW_ID =3D 0, + MAX_FW_ID +}; + +/** + * struct xe_late_bind_fw + */ +struct xe_late_bind_fw { + /** @late_bind_fw.valid: to check if fw is valid */ + bool valid; + /** @late_bind_fw.id: firmware index */ + u32 id; + /** @late_bind_fw.blob_path: firmware binary path */ + char blob_path[PATH_MAX]; + /** @late_bind_fw.type: firmware type */ + u32 type; + /** @late_bind_fw.flags: firmware flags */ + u32 flags; + /** @late_bind_fw.payload: to store the late binding blob */ + u8 payload[MAX_PAYLOAD_SIZE]; + /** @late_bind_fw.payload_size: late binding blob payload_size */ + size_t payload_size; +}; + /** * struct xe_late_bind_component - Late Binding services component * @mei_dev: device that provide Late Binding service. @@ -34,6 +64,8 @@ struct xe_late_bind { bool component_added; /** @late_bind.mutex: protects the component binding and usage */ struct mutex mutex; + /** @late_bind.late_bind_fw: late binding firmware array */ + struct xe_late_bind_fw late_bind_fw[MAX_FW_ID]; }; =20 #endif diff --git a/drivers/misc/mei/late_bind/mei_late_bind.c b/drivers/misc/mei/= late_bind/mei_late_bind.c index cb985f32309e..6ea64c44bb94 100644 --- a/drivers/misc/mei/late_bind/mei_late_bind.c +++ b/drivers/misc/mei/late_bind/mei_late_bind.c @@ -2,7 +2,6 @@ /* * Copyright (C) 2025 Intel Corporation */ -#include #include #include #include --=20 2.34.1 From nobody Thu Oct 9 08:49:41 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 674132FA645 for ; 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a="52210202" X-IronPort-AV: E=Sophos;i="6.16,246,1744095600"; d="scan'208";a="52210202" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2025 11:56:46 -0700 X-CSE-ConnectionGUID: had5b1EOS7CvJRa/c8xbYA== X-CSE-MsgGUID: P161PHf/S/6b4PGi/EWtQA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,246,1744095600"; d="scan'208";a="153951774" Received: from unknown (HELO bnilawar-desk2.iind.intel.com) ([10.190.239.41]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2025 11:56:43 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com, jgg@nvidia.com Subject: [PATCH v3 05/10] drm/xe/xe_late_bind_fw: Load late binding firmware Date: Thu, 19 Jun 2025 00:30:02 +0530 Message-Id: <20250618190007.2932322-6-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618190007.2932322-1-badal.nilawar@intel.com> References: <20250618190007.2932322-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Load late binding firmware v2: - s/EAGAIN/EBUSY/ - Flush worker in suspend and driver unload (Daniele) v3: - Use retry interval of 6s, in steps of 200ms, to allow other OS components release MEI CL handle (Sasha) Signed-off-by: Badal Nilawar --- drivers/gpu/drm/xe/xe_late_bind_fw.c | 113 ++++++++++++++++++++- drivers/gpu/drm/xe/xe_late_bind_fw.h | 1 + drivers/gpu/drm/xe/xe_late_bind_fw_types.h | 5 + 3 files changed, 118 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.c b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.c index d416d6cc1fa2..54aa08c6bdfd 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw.c +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.c @@ -16,6 +16,20 @@ #include "xe_late_bind_fw.h" #include "xe_pcode.h" #include "xe_pcode_api.h" +#include "xe_pm.h" + +/* + * The component should load quite quickly in most cases, but it could take + * a bit. Using a very big timeout just to cover the worst case scenario + */ +#define LB_INIT_TIMEOUT_MS 20000 + +/* + * Retry interval set to 6 seconds, in steps of 200 ms, to allow time for + * other OS components to release the MEI CL handle + */ +#define LB_FW_LOAD_RETRY_MAXCOUNT 30 +#define LB_FW_LOAD_RETRY_PAUSE_MS 200 =20 static const u32 fw_id_to_type[] =3D { [FAN_CONTROL_FW_ID] =3D CSC_LATE_BINDING_TYPE_FAN_CONTROL, @@ -44,6 +58,85 @@ static int xe_late_bind_fw_num_fans(struct xe_late_bind = *late_bind) return 0; } =20 +static void xe_late_bind_wait_for_worker_completion(struct xe_late_bind *l= ate_bind) +{ + struct xe_device *xe =3D late_bind_to_xe(late_bind); + struct xe_late_bind_fw *lbfw; + int fw_id; + + for (fw_id =3D 0; fw_id < MAX_FW_ID; fw_id++) { + lbfw =3D &late_bind->late_bind_fw[fw_id]; + if (lbfw->valid && late_bind->wq) { + drm_dbg(&xe->drm, "Flush work: load %s firmware\n", + fw_id_to_name[lbfw->id]); + flush_work(&lbfw->work); + } + } +} + +static void late_bind_work(struct work_struct *work) +{ + struct xe_late_bind_fw *lbfw =3D container_of(work, struct xe_late_bind_f= w, work); + struct xe_late_bind *late_bind =3D container_of(lbfw, struct xe_late_bind, + late_bind_fw[lbfw->id]); + struct xe_device *xe =3D late_bind_to_xe(late_bind); + int retry =3D LB_FW_LOAD_RETRY_MAXCOUNT; + int ret; + int slept; + + /* we can queue this before the component is bound */ + for (slept =3D 0; slept < LB_INIT_TIMEOUT_MS; slept +=3D 100) { + if (late_bind->component.ops) + break; + msleep(100); + } + + xe_pm_runtime_get(xe); + mutex_lock(&late_bind->mutex); + + if (!late_bind->component.ops) { + drm_err(&xe->drm, "Late bind component not bound\n"); + goto out; + } + + drm_dbg(&xe->drm, "Load %s firmware\n", fw_id_to_name[lbfw->id]); + + do { + ret =3D late_bind->component.ops->push_config(late_bind->component.mei_d= ev, + lbfw->type, lbfw->flags, + lbfw->payload, lbfw->payload_size); + if (!ret) + break; + msleep(LB_FW_LOAD_RETRY_PAUSE_MS); + } while (--retry && ret =3D=3D -EBUSY); + + if (ret) + drm_err(&xe->drm, "Load %s firmware failed with err %d\n", + fw_id_to_name[lbfw->id], ret); + else + drm_dbg(&xe->drm, "Load %s firmware successful\n", + fw_id_to_name[lbfw->id]); +out: + mutex_unlock(&late_bind->mutex); + xe_pm_runtime_put(xe); +} + +int xe_late_bind_fw_load(struct xe_late_bind *late_bind) +{ + struct xe_late_bind_fw *lbfw; + int fw_id; + + if (!late_bind->component_added) + return -EINVAL; + + for (fw_id =3D 0; fw_id < MAX_FW_ID; fw_id++) { + lbfw =3D &late_bind->late_bind_fw[fw_id]; + if (lbfw->valid) + queue_work(late_bind->wq, &lbfw->work); + } + return 0; +} + static int __xe_late_bind_fw_init(struct xe_late_bind *late_bind, u32 fw_i= d) { struct xe_device *xe =3D late_bind_to_xe(late_bind); @@ -93,6 +186,7 @@ static int __xe_late_bind_fw_init(struct xe_late_bind *l= ate_bind, u32 fw_id) =20 memcpy(lb_fw->payload, fw->data, lb_fw->payload_size); release_firmware(fw); + INIT_WORK(&lb_fw->work, late_bind_work); lb_fw->valid =3D true; =20 return 0; @@ -103,11 +197,16 @@ static int xe_late_bind_fw_init(struct xe_late_bind *= late_bind) int ret; int fw_id; =20 + late_bind->wq =3D alloc_ordered_workqueue("late-bind-ordered-wq", 0); + if (!late_bind->wq) + return -ENOMEM; + for (fw_id =3D 0; fw_id < MAX_FW_ID; fw_id++) { ret =3D __xe_late_bind_fw_init(late_bind, fw_id); if (ret) return ret; } + return ret; } =20 @@ -131,6 +230,8 @@ static void xe_late_bind_component_unbind(struct device= *xe_kdev, struct xe_device *xe =3D kdev_to_xe_device(xe_kdev); struct xe_late_bind *late_bind =3D &xe->late_bind; =20 + xe_late_bind_wait_for_worker_completion(late_bind); + mutex_lock(&late_bind->mutex); late_bind->component.ops =3D NULL; mutex_unlock(&late_bind->mutex); @@ -146,8 +247,14 @@ static void xe_late_bind_remove(void *arg) struct xe_late_bind *late_bind =3D arg; struct xe_device *xe =3D late_bind_to_xe(late_bind); =20 + xe_late_bind_wait_for_worker_completion(late_bind); + component_del(xe->drm.dev, &xe_late_bind_component_ops); late_bind->component_added =3D false; + if (late_bind->wq) { + destroy_workqueue(late_bind->wq); + late_bind->wq =3D NULL; + } mutex_destroy(&late_bind->mutex); } =20 @@ -184,5 +291,9 @@ int xe_late_bind_init(struct xe_late_bind *late_bind) if (err) return err; =20 - return xe_late_bind_fw_init(late_bind); + err =3D xe_late_bind_fw_init(late_bind); + if (err) + return err; + + return xe_late_bind_fw_load(late_bind); } diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.h b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.h index 4c73571c3e62..28d56ed2bfdc 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw.h +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.h @@ -11,5 +11,6 @@ struct xe_late_bind; =20 int xe_late_bind_init(struct xe_late_bind *late_bind); +int xe_late_bind_fw_load(struct xe_late_bind *late_bind); =20 #endif diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h b/drivers/gpu/drm/x= e/xe_late_bind_fw_types.h index c6fd33fd5484..d256f53d59e6 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h +++ b/drivers/gpu/drm/xe/xe_late_bind_fw_types.h @@ -9,6 +9,7 @@ #include #include #include +#include =20 #define MAX_PAYLOAD_SIZE (1024 * 4) =20 @@ -38,6 +39,8 @@ struct xe_late_bind_fw { u8 payload[MAX_PAYLOAD_SIZE]; /** @late_bind_fw.payload_size: late binding blob payload_size */ size_t payload_size; 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charset="utf-8" Reload late binding fw during runtime resume. v2: Flush worker during runtime suspend Signed-off-by: Badal Nilawar --- drivers/gpu/drm/xe/xe_late_bind_fw.c | 2 +- drivers/gpu/drm/xe/xe_late_bind_fw.h | 1 + drivers/gpu/drm/xe/xe_pm.c | 6 ++++++ 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.c b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.c index 54aa08c6bdfd..c0be9611c73b 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw.c +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.c @@ -58,7 +58,7 @@ static int xe_late_bind_fw_num_fans(struct xe_late_bind *= late_bind) return 0; } =20 -static void xe_late_bind_wait_for_worker_completion(struct xe_late_bind *l= ate_bind) +void xe_late_bind_wait_for_worker_completion(struct xe_late_bind *late_bin= d) { struct xe_device *xe =3D late_bind_to_xe(late_bind); struct xe_late_bind_fw *lbfw; diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.h b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.h index 28d56ed2bfdc..07e437390539 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw.h +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.h @@ -12,5 +12,6 @@ struct xe_late_bind; =20 int xe_late_bind_init(struct xe_late_bind *late_bind); int xe_late_bind_fw_load(struct xe_late_bind *late_bind); +void xe_late_bind_wait_for_worker_completion(struct xe_late_bind *late_bin= d); =20 #endif diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c index ff749edc005b..91923fd4af80 100644 --- a/drivers/gpu/drm/xe/xe_pm.c +++ b/drivers/gpu/drm/xe/xe_pm.c @@ -20,6 +20,7 @@ #include "xe_gt.h" #include "xe_guc.h" #include "xe_irq.h" +#include "xe_late_bind_fw.h" #include "xe_pcode.h" #include "xe_pxp.h" #include "xe_trace.h" @@ -460,6 +461,8 @@ int xe_pm_runtime_suspend(struct xe_device *xe) if (err) goto out; =20 + xe_late_bind_wait_for_worker_completion(&xe->late_bind); + /* * Applying lock for entire list op as xe_ttm_bo_destroy and xe_bo_move_n= otify * also checks and deletes bo entry from user fault list. @@ -550,6 +553,9 @@ int xe_pm_runtime_resume(struct xe_device *xe) =20 xe_pxp_pm_resume(xe->pxp); =20 + if (xe->d3cold.allowed) + xe_late_bind_fw_load(&xe->late_bind); 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charset="utf-8" Reload late binding fw during S2Idle/S3 resume. Signed-off-by: Badal Nilawar --- drivers/gpu/drm/xe/xe_pm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c index 91923fd4af80..6c44a075a6ab 100644 --- a/drivers/gpu/drm/xe/xe_pm.c +++ b/drivers/gpu/drm/xe/xe_pm.c @@ -205,6 +205,9 @@ int xe_pm_resume(struct xe_device *xe) =20 xe_pxp_pm_resume(xe->pxp); =20 + if (xe->d3cold.allowed) + xe_late_bind_fw_load(&xe->late_bind); + drm_dbg(&xe->drm, "Device resumed\n"); return 0; err: --=20 2.34.1 From nobody Thu Oct 9 08:49:41 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A06E12FC013 for ; Wed, 18 Jun 2025 18:56:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750273016; cv=none; b=LYbOXyuMJTqAtLW6Tw3RNEgu//1I6wvLHWB6qnYsk+trlbNW0gLRuWuh/ScuN0nDEiZhkBgV2dLWgbuc7+5ylWNXCbuHkDJWJRWDC8HP81j/W72CUBAxpi4oEQ5+uIq23CWd1Cx3iRPN9Vt49fi2obpA069pLyyDW7DDOR1TynI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750273016; c=relaxed/simple; bh=XMM1yKoIiyyN1UDllJwOGlHcwGO+CC28Rl+/jttM528=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fYFCcEcu5VIuZAB4UpYOU24gFT1REKWRgSOtyj+zKFnwpI/VtKWpV+VRWrJ56eXdyxMoO65Ei4M18860lcTEuaeriJCuBFIW4Get8gLV4c1AF4Bq/WCGGFJZYMy992zk4trBzQsZP+Vz/xIxPK4S4t93R5oA8GRb/w+lN1z4PEw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ZFFDcIUu; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ZFFDcIUu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750273014; x=1781809014; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XMM1yKoIiyyN1UDllJwOGlHcwGO+CC28Rl+/jttM528=; b=ZFFDcIUugPUq5jatK38Ss38vbaAOAXtj5R4OL/O4qSh8PuoIP2D6MlSu rMhDz2nFDHwWq5XxzEVNlEEtSM61vphDe2lMWN4XSktdd3iKqGsYdBRtn Or4WAySVhOEG4Br9KxEn1kDQ5wmShPt/Tb2RejAEmyjLhe/AuIxQHSh8a E4FfJ3ytpxEbyxDK0U7dnXaVDnZTNNx4p6ovjerXMj57T8r7VyERfJTqB 3165zU7u5Ovc7i8btd4kQ6gyHZboaBGLovyRDO1ON8zS8FJeUARcV2KMH hw/CC56MKaqdpjRg0h8OyAjmR107XA8Lkm3Y84jWA2Y6rbE3vWWe91Em1 w==; X-CSE-ConnectionGUID: e8y2+Jk2QGmbYezWrQO24A== X-CSE-MsgGUID: l4IHdKosRmGSvgXBhirLNQ== X-IronPort-AV: E=McAfee;i="6800,10657,11468"; a="52210220" X-IronPort-AV: E=Sophos;i="6.16,246,1744095600"; d="scan'208";a="52210220" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2025 11:56:54 -0700 X-CSE-ConnectionGUID: P2E8190STyeeS/0HQ4vdYg== X-CSE-MsgGUID: 0cVIvXc6RpqWTHIaHYisBg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,246,1744095600"; d="scan'208";a="153952004" Received: from unknown (HELO bnilawar-desk2.iind.intel.com) ([10.190.239.41]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2025 11:56:51 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com, jgg@nvidia.com Subject: [PATCH v3 08/10] drm/xe/xe_late_bind_fw: Introduce debug fs node to disable late binding Date: Thu, 19 Jun 2025 00:30:05 +0530 Message-Id: <20250618190007.2932322-9-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618190007.2932322-1-badal.nilawar@intel.com> References: <20250618190007.2932322-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce a debug filesystem node to disable late binding fw reload during the system or runtime resume. This is intended for situations where the late binding fw needs to be loaded from user mode. v2: -s/(uval =3D=3D 1) ? true : false/!!uval/ (Daniele) Signed-off-by: Badal Nilawar Acked-by: Rodrigo Vivi --- drivers/gpu/drm/xe/xe_debugfs.c | 41 ++++++++++++++++++++++ drivers/gpu/drm/xe/xe_late_bind_fw.c | 3 ++ drivers/gpu/drm/xe/xe_late_bind_fw_types.h | 3 ++ 3 files changed, 47 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_debugfs.c b/drivers/gpu/drm/xe/xe_debugf= s.c index d83cd6ed3fa8..d1f6f556efa2 100644 --- a/drivers/gpu/drm/xe/xe_debugfs.c +++ b/drivers/gpu/drm/xe/xe_debugfs.c @@ -226,6 +226,44 @@ static const struct file_operations atomic_svm_timesli= ce_ms_fops =3D { .write =3D atomic_svm_timeslice_ms_set, }; =20 +static ssize_t disable_late_binding_show(struct file *f, char __user *ubuf, + size_t size, loff_t *pos) +{ + struct xe_device *xe =3D file_inode(f)->i_private; + struct xe_late_bind *late_bind =3D &xe->late_bind; + char buf[32]; + int len; + + len =3D scnprintf(buf, sizeof(buf), "%d\n", late_bind->disable); + + return simple_read_from_buffer(ubuf, size, pos, buf, len); +} + +static ssize_t disable_late_binding_set(struct file *f, const char __user = *ubuf, + size_t size, loff_t *pos) +{ + struct xe_device *xe =3D file_inode(f)->i_private; + struct xe_late_bind *late_bind =3D &xe->late_bind; + u32 uval; + ssize_t ret; + + ret =3D kstrtouint_from_user(ubuf, size, sizeof(uval), &uval); + if (ret) + return ret; + + if (uval > 1) + return -EINVAL; + + late_bind->disable =3D !!uval; + return size; +} + +static const struct file_operations disable_late_binding_fops =3D { + .owner =3D THIS_MODULE, + .read =3D disable_late_binding_show, + .write =3D disable_late_binding_set, +}; + void xe_debugfs_register(struct xe_device *xe) { struct ttm_device *bdev =3D &xe->ttm; @@ -249,6 +287,9 @@ void xe_debugfs_register(struct xe_device *xe) debugfs_create_file("atomic_svm_timeslice_ms", 0600, root, xe, &atomic_svm_timeslice_ms_fops); =20 + debugfs_create_file("disable_late_binding", 0600, root, xe, + &disable_late_binding_fops); + for (mem_type =3D XE_PL_VRAM0; mem_type <=3D XE_PL_VRAM1; ++mem_type) { man =3D ttm_manager_type(bdev, mem_type); =20 diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.c b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.c index c0be9611c73b..001e526e569a 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw.c +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.c @@ -129,6 +129,9 @@ int xe_late_bind_fw_load(struct xe_late_bind *late_bind) if (!late_bind->component_added) return -EINVAL; =20 + if (late_bind->disable) + return 0; + for (fw_id =3D 0; fw_id < MAX_FW_ID; fw_id++) { lbfw =3D &late_bind->late_bind_fw[fw_id]; if (lbfw->valid) diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h b/drivers/gpu/drm/x= e/xe_late_bind_fw_types.h index d256f53d59e6..f79f0c0b2c4a 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h +++ b/drivers/gpu/drm/xe/xe_late_bind_fw_types.h @@ -71,6 +71,9 @@ struct xe_late_bind { struct xe_late_bind_fw late_bind_fw[MAX_FW_ID]; /** @late_bind.wq: workqueue to submit request to download late bind blob= */ struct workqueue_struct *wq; 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18 Jun 2025 11:56:54 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com, jgg@nvidia.com Subject: [PATCH v3 09/10] drm/xe/xe_late_bind_fw: Extract and print version info Date: Thu, 19 Jun 2025 00:30:06 +0530 Message-Id: <20250618190007.2932322-10-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618190007.2932322-1-badal.nilawar@intel.com> References: <20250618190007.2932322-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extract and print version info of the late binding binary. Signed-off-by: Badal Nilawar --- drivers/gpu/drm/xe/xe_late_bind_fw.c | 132 ++++++++++++++++++++- drivers/gpu/drm/xe/xe_late_bind_fw_types.h | 3 + drivers/gpu/drm/xe/xe_uc_fw_abi.h | 69 +++++++++++ 3 files changed, 203 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw.c b/drivers/gpu/drm/xe/xe_l= ate_bind_fw.c index 001e526e569a..f71d5825ac5b 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw.c +++ b/drivers/gpu/drm/xe/xe_late_bind_fw.c @@ -45,6 +45,129 @@ late_bind_to_xe(struct xe_late_bind *late_bind) return container_of(late_bind, struct xe_device, late_bind); } =20 +/* Refer to the "Late Bind based Firmware Layout" documentation entry for = details */ +static int parse_cpd_header(struct xe_late_bind *late_bind, u32 fw_id, + const void *data, size_t size, const char *manifest_entry) +{ + struct xe_device *xe =3D late_bind_to_xe(late_bind); + const struct gsc_cpd_header_v2 *header =3D data; + const struct gsc_manifest_header *manifest; + const struct gsc_cpd_entry *entry; + size_t min_size =3D sizeof(*header); + struct xe_late_bind_fw *lb_fw; + u32 offset; + int i; + + if (fw_id >=3D MAX_FW_ID) + return -EINVAL; + lb_fw =3D &late_bind->late_bind_fw[fw_id]; + + /* manifest_entry is mandatory */ + xe_assert(xe, manifest_entry); + + if (size < min_size || header->header_marker !=3D GSC_CPD_HEADER_MARKER) + return -ENOENT; + + if (header->header_length < sizeof(struct gsc_cpd_header_v2)) { + drm_err(&xe->drm, "%s late binding fw: Invalid CPD header length %u!\n", + fw_id_to_name[lb_fw->id], header->header_length); + return -EINVAL; + } + + min_size =3D header->header_length + sizeof(struct gsc_cpd_entry) * heade= r->num_of_entries; + if (size < min_size) { + drm_err(&xe->drm, "%s late binding fw: too small! %zu < %zu\n", + fw_id_to_name[lb_fw->id], size, min_size); + return -ENODATA; + } + + /* Look for the manifest first */ + entry =3D (void *)header + header->header_length; + for (i =3D 0; i < header->num_of_entries; i++, entry++) + if (strcmp(entry->name, manifest_entry) =3D=3D 0) + offset =3D entry->offset & GSC_CPD_ENTRY_OFFSET_MASK; + + if (!offset) { + drm_err(&xe->drm, "%s late binding fw: Failed to find manifest_entry\n", + fw_id_to_name[lb_fw->id]); + return -ENODATA; + } + + min_size =3D offset + sizeof(struct gsc_manifest_header); + if (size < min_size) { + drm_err(&xe->drm, "%s late binding fw: too small! %zu < %zu\n", + fw_id_to_name[lb_fw->id], size, min_size); + return -ENODATA; + } + + manifest =3D data + offset; + + lb_fw->version.major =3D manifest->fw_version.major; + lb_fw->version.minor =3D manifest->fw_version.minor; + lb_fw->version.hotfix =3D manifest->fw_version.hotfix; + lb_fw->version.build =3D manifest->fw_version.build; + + return 0; +} + +/* Refer to the "Late Bind based Firmware Layout" documentation entry for = details */ +static int parse_lb_layout(struct xe_late_bind *late_bind, u32 fw_id, + const void *data, size_t size, const char *fpt_entry) +{ + struct xe_device *xe =3D late_bind_to_xe(late_bind); + const struct csc_fpt_header *header =3D data; + const struct csc_fpt_entry *entry; + size_t min_size =3D sizeof(*header); + struct xe_late_bind_fw *lb_fw; + u32 offset; + int i; + + if (fw_id >=3D MAX_FW_ID) + return -EINVAL; + + lb_fw =3D &late_bind->late_bind_fw[fw_id]; + + /* fpt_entry is mandatory */ + xe_assert(xe, fpt_entry); + + if (size < min_size || header->header_marker !=3D CSC_FPT_HEADER_MARKER) + return -ENOENT; + + if (header->header_length < sizeof(struct csc_fpt_header)) { + drm_err(&xe->drm, "%s late binding fw: Invalid FPT header length %u!\n", + fw_id_to_name[lb_fw->id], header->header_length); + return -EINVAL; + } + + min_size =3D header->header_length + sizeof(struct csc_fpt_entry) * heade= r->num_of_entries; + if (size < min_size) { + drm_err(&xe->drm, "%s late binding fw: too small! %zu < %zu\n", + fw_id_to_name[lb_fw->id], size, min_size); + return -ENODATA; + } + + /* Look for the manifest first */ + entry =3D (void *)header + header->header_length; + for (i =3D 0; i < header->num_of_entries; i++, entry++) + if (strcmp(entry->name, fpt_entry) =3D=3D 0) + offset =3D entry->offset; + + if (!offset) { + drm_err(&xe->drm, "%s late binding fw: Failed to find fpt_entry\n", + fw_id_to_name[lb_fw->id]); + return -ENODATA; + } + + min_size =3D offset + sizeof(struct gsc_cpd_header_v2); + if (size < min_size) { + drm_err(&xe->drm, "%s late binding fw: too small! %zu < %zu\n", + fw_id_to_name[lb_fw->id], size, min_size); + return -ENODATA; + } + + return parse_cpd_header(late_bind, fw_id, data + offset, size - offset, "= LTES.man"); +} + static int xe_late_bind_fw_num_fans(struct xe_late_bind *late_bind) { struct xe_device *xe =3D late_bind_to_xe(late_bind); @@ -185,8 +308,15 @@ static int __xe_late_bind_fw_init(struct xe_late_bind = *late_bind, u32 fw_id) return -ENODATA; } =20 - lb_fw->payload_size =3D fw->size; + ret =3D parse_lb_layout(late_bind, fw_id, fw->data, fw->size, "LTES"); + if (ret) + return ret; + + drm_info(&xe->drm, "Using %s firmware from %s version %d.%d.%d\n", + fw_id_to_name[lb_fw->id], lb_fw->blob_path, + lb_fw->version.major, lb_fw->version.minor, lb_fw->version.hotfix); =20 + lb_fw->payload_size =3D fw->size; memcpy(lb_fw->payload, fw->data, lb_fw->payload_size); release_firmware(fw); INIT_WORK(&lb_fw->work, late_bind_work); diff --git a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h b/drivers/gpu/drm/x= e/xe_late_bind_fw_types.h index f79f0c0b2c4a..3fc4f350c81f 100644 --- a/drivers/gpu/drm/xe/xe_late_bind_fw_types.h +++ b/drivers/gpu/drm/xe/xe_late_bind_fw_types.h @@ -10,6 +10,7 @@ #include #include #include +#include "xe_uc_fw_abi.h" =20 #define MAX_PAYLOAD_SIZE (1024 * 4) =20 @@ -41,6 +42,8 @@ struct xe_late_bind_fw { size_t payload_size; /** @late_bind_fw.work: worker to upload latebind blob */ struct work_struct work; + /** @late_bind_fw.version: late binding blob manifest version */ + struct gsc_version version; }; =20 /** diff --git a/drivers/gpu/drm/xe/xe_uc_fw_abi.h b/drivers/gpu/drm/xe/xe_uc_f= w_abi.h index 87ade41209d0..13da2ca96817 100644 --- a/drivers/gpu/drm/xe/xe_uc_fw_abi.h +++ b/drivers/gpu/drm/xe/xe_uc_fw_abi.h @@ -318,4 +318,73 @@ struct gsc_manifest_header { u32 exponent_size; /* in dwords */ } __packed; =20 +/** + * DOC: Late binding Firmware Layout + * + * The Late binding binary starts with FPT header, which contains locations + * of various partitions of the binary. Here we're interested in finding o= ut + * manifest version. To the manifest version, we need to locate CPD header + * one of the entry in CPD header points to manifest header. Manifest head= er + * contains the version. + * + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ + * | FPT Header | + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ + * | FPT entries[] | + * | entry1 | + * | ... | + * | entryX | + * | "LTES" | + * | ... | + * | offset >-----------------------------|------o + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ | + * | + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ | + * | CPD Header |<-----o + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ + * | CPD entries[] | + * | entry1 | + * | ... | + * | entryX | + * | "LTES.man" | + * | ... | + * | offset >----------------------------|------o + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ | + * | + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ | + * | Manifest Header |<-----o + * | ... | + * | FW version | + * | ... | + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D+ + */ + +/* FPT Headers */ +struct csc_fpt_header { + u32 header_marker; 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18 Jun 2025 11:57:00 -0700 X-CSE-ConnectionGUID: YA/pEJfJSCm3aBMB9JG+MQ== X-CSE-MsgGUID: y8jRlaalRlyeXScKPUB1Zg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,246,1744095600"; d="scan'208";a="153952160" Received: from unknown (HELO bnilawar-desk2.iind.intel.com) ([10.190.239.41]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2025 11:56:57 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: anshuman.gupta@intel.com, rodrigo.vivi@intel.com, alexander.usyskin@intel.com, gregkh@linuxfoundation.org, daniele.ceraolospurio@intel.com, jgg@nvidia.com Subject: [PATCH v3 10/10] [CI]drm/xe/xe_late_bind_fw: Select INTEL_MEI_LATE_BIND for CI Date: Thu, 19 Jun 2025 00:30:07 +0530 Message-Id: <20250618190007.2932322-11-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618190007.2932322-1-badal.nilawar@intel.com> References: <20250618190007.2932322-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Do not review Signed-off-by: Badal Nilawar --- drivers/gpu/drm/xe/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/xe/Kconfig b/drivers/gpu/drm/xe/Kconfig index 30ed74ad29ab..b161e1156c73 100644 --- a/drivers/gpu/drm/xe/Kconfig +++ b/drivers/gpu/drm/xe/Kconfig @@ -44,6 +44,7 @@ config DRM_XE select WANT_DEV_COREDUMP select AUXILIARY_BUS select HMM_MIRROR + select INTEL_MEI_LATE_BIND help Driver for Intel Xe2 series GPUs and later. Experimental support for Xe series is also available. --=20 2.34.1