From nobody Wed Dec 17 12:18:35 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.4]) by smtp.subspace.kernel.org (Postfix) with ESMTP id F11F52EE99C; Wed, 18 Jun 2025 15:21:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750260122; cv=none; b=aOryQvqdyR+04r/kEMNCafanuNWQ8c6yhn6sn7VTm+Zc/7+oIukQQpQBwPz2hUgUM8pNcGtNu+386DqiEmsU2X1TQGV+phE+ojcWlMPX4vPTfJvob/0wtTQTirTFuQdE+OpgRbaoYWAdrsdzgYibZvECfRS6+IkaecHU5NLMDXY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750260122; c=relaxed/simple; bh=nE6bKO5dP5cXC6LWtFFk7yFnzldnKqo5QJozk1Lv45Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=pIC6DeskFrRsbXyopSEclsEksmfWSaCzob/wi4T5ltLEfr2mp5qKLBL3zQCM/zLYczwNPWqUcRmF+hJ3eboRJYe8DWunV3peTZAp8LWeqUcetC3h8E/sLOUzcN6eCk+e1Y8y/b07BNgsKpLzll+t5zMSXf3m0ah+38lpkyZ1wlk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=MBwaSglD; arc=none smtp.client-ip=117.135.210.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="MBwaSglD" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=Ae 9kCteaIREimUk/syr6kEJ201xf2z63OTJWk7zi+T4=; b=MBwaSglDG2ZYQmcuIh T3vytxpUaVjQtMemTU1ysmICA8ncB2t1b1lzlBos+Vnzxp6RIZktLhSX5kLeK8Ah cRT/ioiHuJ5r2gPlQihey+FzVQM0UX2K3HCgirEPUBBiAKX5B+Ga/H5HPXFI49M6 X8PbvnSMovmjmOiZGbqt7OUU4= Received: from localhost.localdomain (unknown []) by gzsmtp5 (Coremail) with SMTP id QCgvCgBnr96E2VJo_+eqAA--.17078S4; Wed, 18 Jun 2025 23:21:42 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, mani@kernel.org, kwilczynski@kernel.org Cc: robh@kernel.org, jingoohan1@gmail.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 12/13] PCI: rcar-gen4: Refactor code by using dw_pcie_clear_and_set_dword() Date: Wed, 18 Jun 2025 23:21:11 +0800 Message-Id: <20250618152112.1010147-13-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250618152112.1010147-1-18255117159@163.com> References: <20250618152112.1010147-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: QCgvCgBnr96E2VJo_+eqAA--.17078S4 X-Coremail-Antispam: 1Uf129KBjvJXoWxWFy3GF4Dtw48tF4DXr17GFg_yoW5Cry5pa y7CFySkF1jyws09F4UXaykur15uan3Ca1jg3Z7Gw1I9ay7ArZxWay0y3y7tFWxGFZ2qr45 Cw1UtFWUWF15ZFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0z_db1nUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWxVwo2hS1QJtrwAAsy Content-Type: text/plain; charset="utf-8" R-Car Gen4 PCIe driver contains multiple read-modify-write sequences for speed change control and lane configuration. The driver manually handles speed change initiation through bit set/clear operations and configures lane skew with explicit bit masking. Refactor speed change handling and lane skew configuration using dw_pcie_clear_and_set_dword(). For speed change operations, replace manual bit toggling with clear-and-set sequences. For lane skew, use the helper to conditionally set bits based on lane count. Adopting the standard interface simplifies link training logic and reduces code complexity. The change also ensures consistent handling of control register bits and provides better documentation of intent through declarative bit masks. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-rcar-gen4.c | 23 ++++++++------------- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/cont= roller/dwc/pcie-rcar-gen4.c index 18055807a4f5..20a6c88252d6 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -107,13 +107,11 @@ static int rcar_gen4_pcie_speed_change(struct dw_pcie= *dw) u32 val; int i; =20 - val =3D dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL); - val &=3D ~PORT_LOGIC_SPEED_CHANGE; - dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val); + dw_pcie_clear_and_set_dword(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, + PORT_LOGIC_SPEED_CHANGE, 0); =20 - val =3D dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL); - val |=3D PORT_LOGIC_SPEED_CHANGE; - dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val); + dw_pcie_clear_and_set_dword(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, + 0, PORT_LOGIC_SPEED_CHANGE); =20 for (i =3D 0; i < RCAR_NUM_SPEED_CHANGE_RETRIES; i++) { val =3D dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL); @@ -565,11 +563,9 @@ static void rcar_gen4_pcie_additional_common_init(stru= ct rcar_gen4_pcie *rcar) struct dw_pcie *dw =3D &rcar->dw; u32 val; =20 - val =3D dw_pcie_readl_dbi(dw, PCIE_PORT_LANE_SKEW); - val &=3D ~PORT_LANE_SKEW_INSERT_MASK; - if (dw->num_lanes < 4) - val |=3D BIT(6); - dw_pcie_writel_dbi(dw, PCIE_PORT_LANE_SKEW, val); + dw_pcie_clear_and_set_dword(dw, PCIE_PORT_LANE_SKEW, + PORT_LANE_SKEW_INSERT_MASK, + (dw->num_lanes < 4) ? BIT(6) : 0); =20 val =3D readl(rcar->base + PCIEPWRMNGCTRL); val |=3D APP_CLK_REQ_N | APP_CLK_PM_EN; @@ -680,9 +676,8 @@ static int rcar_gen4_pcie_ltssm_control(struct rcar_gen= 4_pcie *rcar, bool enable return 0; } =20 - val =3D dw_pcie_readl_dbi(dw, PCIE_PORT_FORCE); - val |=3D PORT_FORCE_DO_DESKEW_FOR_SRIS; - dw_pcie_writel_dbi(dw, PCIE_PORT_FORCE, val); + dw_pcie_clear_and_set_dword(dw, PCIE_PORT_FORCE, + 0, PORT_FORCE_DO_DESKEW_FOR_SRIS); =20 val =3D readl(rcar->base + PCIEMSR0); val |=3D APP_SRIS_MODE; --=20 2.25.1