From nobody Wed Dec 17 10:45:09 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0EE992EF672; Wed, 18 Jun 2025 15:21:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750260095; cv=none; b=gVG+jjb7zMybBhQIBajAQEOuaAZNONuM+5pyQkC+trP2Md4P2Nl2ja7t7B0B/e2a8AzbOeStcxYTgRL3kszZ2mz+eZRXjefy86MDa35wOX5Y66tzdbx2/OxKF0hfaKrqQpO3fl59fURV2uq1trWGRyVNqnWU9HmJhbLRv/Tg/Es= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750260095; c=relaxed/simple; bh=JvVori+RjvHe3Ol6doOrMn5EP3oQaMsrZHnK2AFmnfE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HWeuBaonJEPg0fJbedPge1Mc72CvY6lXtObDefZcZht1JeuenOpz4mB2T94O09d4JzTZ+LqCWHFq65gz6l/CbKbCBbPvf9Mabpwa5bSxgC3LgIMNcWmxXESBdA+uxN8X6fh0qdrwwdauHUB98xxet6GwpRPIgDJ9yWUObpIzRFk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=e5FBv7Dg; arc=none smtp.client-ip=117.135.210.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="e5FBv7Dg" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=IS tFwGQpYrL7Cj3+R2jV60PlExYzDBLd2Wp6pOgZwFc=; b=e5FBv7Dg5zM6fHIXC6 inxXU2xnKhxqRBcp2fPUgVwLYqnppL7sPPq8p0Yl4UlqkOmq1piEwQkNqOYVW3hM ZDbADlRmD69QJDZ6ipYWeS8s5KCeuiF6+74fedasBE0NzRGfHEjs2UFY4T3Synns mFsXi5SnkdWY+ADu4LdCwAh3I= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g0-3 (Coremail) with SMTP id _____wDHoedq2VJo3qQFAQ--.15407S3; Wed, 18 Jun 2025 23:21:15 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, mani@kernel.org, kwilczynski@kernel.org Cc: robh@kernel.org, jingoohan1@gmail.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 01/13] PCI: dwc: Add dw_pcie_clear_and_set_dword() for register bit manipulation Date: Wed, 18 Jun 2025 23:21:00 +0800 Message-Id: <20250618152112.1010147-2-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250618152112.1010147-1-18255117159@163.com> References: <20250618152112.1010147-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDHoedq2VJo3qQFAQ--.15407S3 X-Coremail-Antispam: 1Uf129KBjvJXoW7Zr18uF1DGw4UGFy3KFW3Jrb_yoW8Aryrpa y5K3y3CF47Aa13uan8Aan3ZFyYy3ZayrW7CrZxC3Wa9F13ZryqqFy8tFy5tr93GrWIqr1a gr4DtayxWa15AFDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0z_4EE5UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiQxdwo2hS1CZ5SwACs- Content-Type: text/plain; charset="utf-8" DesignWare PCIe controller drivers implement register bit manipulation through explicit read-modify-write sequences. These patterns appear repeatedly across multiple drivers with minor variations, creating code duplication and maintenance overhead. Implement dw_pcie_clear_and_set_dword() helper to encapsulate atomic register modification. The function reads the current register value, clears specified bits, sets new bits, and writes back the result in a single operation. This abstraction hides bitwise manipulation details while ensuring consistent behavior across all usage sites. Centralizing this logic reduces future maintenance effort when modifying register access patterns and minimizes the risk of implementation divergence between drivers. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-designware.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index ce9e18554e42..f401c144df0f 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -707,6 +707,17 @@ static inline void dw_pcie_ep_writel_dbi2(struct dw_pc= ie_ep *ep, u8 func_no, dw_pcie_ep_write_dbi2(ep, func_no, reg, 0x4, val); } =20 +static inline void dw_pcie_clear_and_set_dword(struct dw_pcie *pci, int po= s, + u32 clear, u32 set) +{ + u32 val; + + val =3D dw_pcie_readl_dbi(pci, pos); + val &=3D ~clear; + val |=3D set; + dw_pcie_writel_dbi(pci, pos, val); +} + static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci) { u32 reg; --=20 2.25.1 From nobody Wed Dec 17 10:45:09 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.2]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 46FBD2EF9B8; Wed, 18 Jun 2025 15:21:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750260098; cv=none; b=cIi6SKb82F+/3EAR8AFaK/PQGKNFC5pPL+LIjG4/5qkETxXrBbwGmzzcbNyQmyj4ydKFdVe4eQFtXMTuC3hiBCuR8reThBD0NmJuD9ZeYGBrZ4OVc8gDzpaU2gSajum+ta+reMUImnvnmhfwb7BCiNYMFCV3YKaGKJUqevRznjQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750260098; c=relaxed/simple; bh=KkEtIl9pSDj7Ecj4Ygq5Punv9Uapnu6CBuJsAB8goXo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=atoi9WF2pZKS54bBLE+RLsPaI9dmSedMAXtKNxK5Ts0bYXAqyDa5gHFz06YEICWx3iDsoQUZdbEMF+0f7hw8G05+KSHDea0FBXLrjWJIZHVlcAKoKMBwTE6Iwv2wv9YbMS3MNZAUBDHeop2h5Yk+P/DeYy8LF3lFyPfCn/hMax4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=VxKZ/b2J; arc=none smtp.client-ip=117.135.210.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="VxKZ/b2J" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=o9 F2j93DS6wXY+fSTUor4J2EnXnuHVvpWbh0ck9+hgs=; b=VxKZ/b2JhfgZNgxP62 6xRlVkA4uoKImUwhfK81CvLxCp4Y9CkjjxFGNPYnfm4EyCWzH+KD7fer55QMexGP v/gV2R9zzNQ4L4u5+xIvruXpsKxvixEE/oyRewMCuGpe0IJcgZN4K6kh5RWq6GuE bY5fPIR51/QUUTJUTNz1DgygA= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g0-3 (Coremail) with SMTP id _____wDHoedq2VJo3qQFAQ--.15407S4; Wed, 18 Jun 2025 23:21:16 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, mani@kernel.org, kwilczynski@kernel.org Cc: robh@kernel.org, jingoohan1@gmail.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 02/13] PCI: dwc: Refactor code by using dw_pcie_clear_and_set_dword() Date: Wed, 18 Jun 2025 23:21:01 +0800 Message-Id: <20250618152112.1010147-3-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250618152112.1010147-1-18255117159@163.com> References: <20250618152112.1010147-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDHoedq2VJo3qQFAQ--.15407S4 X-Coremail-Antispam: 1Uf129KBjvAXoWfJrW8GFy8Ww4DZw47JF4kCrg_yoW8Ww43Go Z3XF1UZa17tF10qFyUtas3KryUZrnFvFyFvFs2kr4j9ay3A3W5A393KF13Zw1Y9w4fC34r Xa1kG3Z8ArW7Xr1Un29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UbIYCTnIWIevJa73UjIFyTuYvj4RrcTQUUUUU X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiQxBwo2hS1CaCCAAAsC Content-Type: text/plain; charset="utf-8" DesignWare core modules contain multiple instances of manual read-modify-write operations for register bit manipulation. These patterns duplicate functionality now provided by dw_pcie_clear_and_set_dword(), particularly in debugfs, endpoint, host, and core initialization paths. Replace open-coded bit manipulation sequences with calls to dw_pcie_clear_and_set_dword(). Affected areas include debugfs register control, endpoint capability configuration, host setup routines, and core link initialization logic. The changes simplify power management handling, capability masking, and feature configuration. Standardizing on the helper function reduces code duplication by ~140 lines across core modules while improving readability. The refactoring also ensures consistent error handling for register operations and provides a single point of control for future bit manipulation logi updates. Signed-off-by: Hans Zhang <18255117159@163.com> --- .../controller/dwc/pcie-designware-debugfs.c | 67 +++++++---------- .../pci/controller/dwc/pcie-designware-ep.c | 20 +++-- .../pci/controller/dwc/pcie-designware-host.c | 27 +++---- drivers/pci/controller/dwc/pcie-designware.c | 74 +++++++------------ drivers/pci/controller/dwc/pcie-designware.h | 18 +---- 5 files changed, 76 insertions(+), 130 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-debugfs.c b/drivers= /pci/controller/dwc/pcie-designware-debugfs.c index c67601096c48..7e01d4575d0b 100644 --- a/drivers/pci/controller/dwc/pcie-designware-debugfs.c +++ b/drivers/pci/controller/dwc/pcie-designware-debugfs.c @@ -213,10 +213,8 @@ static ssize_t lane_detect_write(struct file *file, co= nst char __user *buf, if (val) return val; =20 - val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_R= EG); - val &=3D ~(LANE_SELECT); - val |=3D FIELD_PREP(LANE_SELECT, lane); - dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG, val= ); + dw_pcie_clear_and_set_dword(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE= _REG, + LANE_SELECT, FIELD_PREP(LANE_SELECT, lane)); =20 return count; } @@ -307,14 +305,13 @@ static ssize_t err_inj_write(struct file *file, const= char __user *buf, static void set_event_number(struct dwc_pcie_rasdes_priv *pdata, struct dw_pcie *pci, struct dwc_pcie_rasdes_info *rinfo) { - u32 val; + u32 val =3D 0; =20 - val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUN= TER_CTRL_REG); - val &=3D ~EVENT_COUNTER_ENABLE; - val &=3D ~(EVENT_COUNTER_GROUP_SELECT | EVENT_COUNTER_EVENT_SELECT); val |=3D FIELD_PREP(EVENT_COUNTER_GROUP_SELECT, event_list[pdata->idx].gr= oup_no); val |=3D FIELD_PREP(EVENT_COUNTER_EVENT_SELECT, event_list[pdata->idx].ev= ent_no); - dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTR= L_REG, val); + dw_pcie_clear_and_set_dword(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_CO= UNTER_CTRL_REG, + EVENT_COUNTER_ENABLE | EVENT_COUNTER_GROUP_SELECT | + EVENT_COUNTER_EVENT_SELECT, val); } =20 static ssize_t counter_enable_read(struct file *file, char __user *buf, @@ -354,13 +351,9 @@ static ssize_t counter_enable_write(struct file *file,= const char __user *buf, =20 mutex_lock(&rinfo->reg_event_lock); set_event_number(pdata, pci, rinfo); - val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUN= TER_CTRL_REG); - if (enable) - val |=3D FIELD_PREP(EVENT_COUNTER_ENABLE, PER_EVENT_ON); - else - val |=3D FIELD_PREP(EVENT_COUNTER_ENABLE, PER_EVENT_OFF); - - dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTR= L_REG, val); + val |=3D FIELD_PREP(EVENT_COUNTER_ENABLE, enable ? PER_EVENT_ON : PER_EVE= NT_OFF); + dw_pcie_clear_and_set_dword(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_CO= UNTER_CTRL_REG, + 0, val); =20 /* * While enabling the counter, always read the status back to check if @@ -415,10 +408,9 @@ static ssize_t counter_lane_write(struct file *file, c= onst char __user *buf, =20 mutex_lock(&rinfo->reg_event_lock); set_event_number(pdata, pci, rinfo); - val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUN= TER_CTRL_REG); - val &=3D ~(EVENT_COUNTER_LANE_SELECT); - val |=3D FIELD_PREP(EVENT_COUNTER_LANE_SELECT, lane); - dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTR= L_REG, val); + dw_pcie_clear_and_set_dword(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_CO= UNTER_CTRL_REG, + EVENT_COUNTER_LANE_SELECT, + FIELD_PREP(EVENT_COUNTER_LANE_SELECT, lane)); mutex_unlock(&rinfo->reg_event_lock); =20 return count; @@ -654,20 +646,15 @@ static int dw_pcie_ptm_check_capability(void *drvdata) static int dw_pcie_ptm_context_update_write(void *drvdata, u8 mode) { struct dw_pcie *pci =3D drvdata; - u32 val; =20 - if (mode =3D=3D PCIE_PTM_CONTEXT_UPDATE_AUTO) { - val =3D dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL); - val |=3D PTM_REQ_AUTO_UPDATE_ENABLED; - dw_pcie_writel_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, val); - } else if (mode =3D=3D PCIE_PTM_CONTEXT_UPDATE_MANUAL) { - val =3D dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL); - val &=3D ~PTM_REQ_AUTO_UPDATE_ENABLED; - val |=3D PTM_REQ_START_UPDATE; - dw_pcie_writel_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, val); - } else { + if (mode =3D=3D PCIE_PTM_CONTEXT_UPDATE_AUTO) + dw_pcie_clear_and_set_dword(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, + 0, PTM_REQ_AUTO_UPDATE_ENABLED); + else if (mode =3D=3D PCIE_PTM_CONTEXT_UPDATE_MANUAL) + dw_pcie_clear_and_set_dword(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, + PTM_REQ_AUTO_UPDATE_ENABLED, PTM_REQ_START_UPDATE); + else return -EINVAL; - } =20 return 0; } @@ -694,17 +681,13 @@ static int dw_pcie_ptm_context_update_read(void *drvd= ata, u8 *mode) static int dw_pcie_ptm_context_valid_write(void *drvdata, bool valid) { struct dw_pcie *pci =3D drvdata; - u32 val; =20 - if (valid) { - val =3D dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL); - val |=3D PTM_RES_CCONTEXT_VALID; - dw_pcie_writel_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, val); - } else { - val =3D dw_pcie_readl_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL); - val &=3D ~PTM_RES_CCONTEXT_VALID; - dw_pcie_writel_dbi(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, val); - } + if (valid) + dw_pcie_clear_and_set_dword(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, + 0, PTM_RES_CCONTEXT_VALID); + else + dw_pcie_clear_and_set_dword(pci, pci->ptm_vsec_offset + PTM_RES_REQ_CTRL, + PTM_RES_CCONTEXT_VALID, 0); =20 return 0; } diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/= controller/dwc/pcie-designware-ep.c index 0ae54a94809b..7e52892f632b 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -277,7 +277,7 @@ static int dw_pcie_ep_set_bar_resizable(struct dw_pcie_= ep *ep, u8 func_no, int flags =3D epf_bar->flags; u32 reg =3D PCI_BASE_ADDRESS_0 + (4 * bar); unsigned int rebar_offset; - u32 rebar_cap, rebar_ctrl; + u32 rebar_cap; int ret; =20 rebar_offset =3D dw_pcie_ep_get_rebar_offset(pci, bar); @@ -310,9 +310,8 @@ static int dw_pcie_ep_set_bar_resizable(struct dw_pcie_= ep *ep, u8 func_no, * 1 MB to 128 TB. Bits 31:16 in PCI_REBAR_CTRL define "supported sizes" * bits for sizes 256 TB to 8 EB. Disallow sizes 256 TB to 8 EB. */ - rebar_ctrl =3D dw_pcie_readl_dbi(pci, rebar_offset + PCI_REBAR_CTRL); - rebar_ctrl &=3D ~GENMASK(31, 16); - dw_pcie_writel_dbi(pci, rebar_offset + PCI_REBAR_CTRL, rebar_ctrl); + dw_pcie_clear_and_set_dword(pci, rebar_offset + PCI_REBAR_CTRL, + GENMASK(31, 16), 0); =20 /* * The "selected size" (bits 13:8) in PCI_REBAR_CTRL are automatically @@ -925,7 +924,7 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep) struct dw_pcie_ep_func *ep_func; struct device *dev =3D pci->dev; struct pci_epc *epc =3D ep->epc; - u32 ptm_cap_base, reg; + u32 ptm_cap_base; u8 hdr_type; u8 func_no; void *addr; @@ -1001,13 +1000,12 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep) */ if (ptm_cap_base) { dw_pcie_dbi_ro_wr_en(pci); - reg =3D dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP); - reg &=3D ~PCI_PTM_CAP_ROOT; - dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg); + dw_pcie_clear_and_set_dword(pci, ptm_cap_base + PCI_PTM_CAP, + PCI_PTM_CAP_ROOT, 0); =20 - reg =3D dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP); - reg &=3D ~(PCI_PTM_CAP_RES | PCI_PTM_GRANULARITY_MASK); - dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg); + dw_pcie_clear_and_set_dword(pci, ptm_cap_base + PCI_PTM_CAP, + PCI_PTM_CAP_RES | + PCI_PTM_GRANULARITY_MASK, 0); dw_pcie_dbi_ro_wr_dis(pci); } =20 diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 906277f9ffaf..e43d66d48439 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -909,7 +909,7 @@ static void dw_pcie_config_presets(struct dw_pcie_rp *p= p) int dw_pcie_setup_rc(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); - u32 val, ctrl, num_ctrls; + u32 ctrl, num_ctrls; int ret; =20 /* @@ -941,23 +941,17 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000); =20 /* Setup interrupt pins */ - val =3D dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE); - val &=3D 0xffff00ff; - val |=3D 0x00000100; - dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val); + dw_pcie_clear_and_set_dword(pci, PCI_INTERRUPT_LINE, + 0x0000ff00, 0x00000100); =20 /* Setup bus numbers */ - val =3D dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); - val &=3D 0xff000000; - val |=3D 0x00ff0100; - dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val); + dw_pcie_clear_and_set_dword(pci, PCI_PRIMARY_BUS, + 0x00ffffff, 0x00ff0100); =20 /* Setup command register */ - val =3D dw_pcie_readl_dbi(pci, PCI_COMMAND); - val &=3D 0xffff0000; - val |=3D PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER | PCI_COMMAND_SERR; - dw_pcie_writel_dbi(pci, PCI_COMMAND, val); + dw_pcie_clear_and_set_dword(pci, PCI_COMMAND, 0x0000ffff, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER | PCI_COMMAND_SERR); =20 dw_pcie_config_presets(pp); /* @@ -976,9 +970,8 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) /* Program correct class for RC */ dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); =20 - val =3D dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); - val |=3D PORT_LOGIC_SPEED_CHANGE; - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); + dw_pcie_clear_and_set_dword(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, + 0, PORT_LOGIC_SPEED_CHANGE); =20 dw_pcie_dbi_ro_wr_dis(pci); =20 diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index 4d794964fa0f..d424e5e55c9f 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -740,11 +740,8 @@ EXPORT_SYMBOL_GPL(dw_pcie_link_up); =20 void dw_pcie_upconfig_setup(struct dw_pcie *pci) { - u32 val; - - val =3D dw_pcie_readl_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL); - val |=3D PORT_MLTI_UPCFG_SUPPORT; - dw_pcie_writel_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL, val); + dw_pcie_clear_and_set_dword(pci, PCIE_PORT_MULTI_LANE_CTRL, + 0, PORT_MLTI_UPCFG_SUPPORT); } EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup); =20 @@ -805,21 +802,12 @@ int dw_pcie_link_get_max_link_width(struct dw_pcie *p= ci) =20 static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_l= anes) { - u32 lnkcap, lwsc, plc; + u32 plc =3D 0; u8 cap; =20 if (!num_lanes) return; =20 - /* Set the number of lanes */ - plc =3D dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); - plc &=3D ~PORT_LINK_FAST_LINK_MODE; - plc &=3D ~PORT_LINK_MODE_MASK; - - /* Set link width speed control register */ - lwsc =3D dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); - lwsc &=3D ~PORT_LOGIC_LINK_WIDTH_MASK; - lwsc |=3D PORT_LOGIC_LINK_WIDTH_1_LANES; switch (num_lanes) { case 1: plc |=3D PORT_LINK_MODE_1_LANES; @@ -837,14 +825,19 @@ static void dw_pcie_link_set_max_link_width(struct dw= _pcie *pci, u32 num_lanes) dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes); return; } - dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc); - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc); + /* Set the number of lanes */ + dw_pcie_clear_and_set_dword(pci, PCIE_PORT_LINK_CONTROL, + PORT_LINK_FAST_LINK_MODE | PORT_LINK_MODE_MASK, + plc); + /* Set link width speed control register */ + dw_pcie_clear_and_set_dword(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, + PORT_LOGIC_LINK_WIDTH_MASK, + PORT_LOGIC_LINK_WIDTH_1_LANES); =20 cap =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - lnkcap =3D dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); - lnkcap &=3D ~PCI_EXP_LNKCAP_MLW; - lnkcap |=3D FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes); - dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap); + dw_pcie_clear_and_set_dword(pci, cap + PCI_EXP_LNKCAP, + PCI_EXP_LNKCAP_MLW, + FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes)); } =20 void dw_pcie_iatu_detect(struct dw_pcie *pci) @@ -1133,38 +1126,27 @@ void dw_pcie_edma_remove(struct dw_pcie *pci) =20 void dw_pcie_setup(struct dw_pcie *pci) { - u32 val; - dw_pcie_link_set_max_speed(pci); =20 /* Configure Gen1 N_FTS */ - if (pci->n_fts[0]) { - val =3D dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); - val &=3D ~(PORT_AFR_N_FTS_MASK | PORT_AFR_CC_N_FTS_MASK); - val |=3D PORT_AFR_N_FTS(pci->n_fts[0]); - val |=3D PORT_AFR_CC_N_FTS(pci->n_fts[0]); - dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); - } + if (pci->n_fts[0]) + dw_pcie_clear_and_set_dword(pci, PCIE_PORT_AFR, + PORT_AFR_N_FTS_MASK | PORT_AFR_CC_N_FTS_MASK, + PORT_AFR_N_FTS(pci->n_fts[0]) | + PORT_AFR_CC_N_FTS(pci->n_fts[0])); =20 /* Configure Gen2+ N_FTS */ - if (pci->n_fts[1]) { - val =3D dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); - val &=3D ~PORT_LOGIC_N_FTS_MASK; - val |=3D pci->n_fts[1]; - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); - } + if (pci->n_fts[1]) + dw_pcie_clear_and_set_dword(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, + PORT_LOGIC_N_FTS_MASK, pci->n_fts[1]); =20 - if (dw_pcie_cap_is(pci, CDM_CHECK)) { - val =3D dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); - val |=3D PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS | - PCIE_PL_CHK_REG_CHK_REG_START; - dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); - } + if (dw_pcie_cap_is(pci, CDM_CHECK)) + dw_pcie_clear_and_set_dword(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, 0, + PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS | + PCIE_PL_CHK_REG_CHK_REG_START); =20 - val =3D dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); - val &=3D ~PORT_LINK_FAST_LINK_MODE; - val |=3D PORT_LINK_DLL_LINK_EN; - dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); + dw_pcie_clear_and_set_dword(pci, PCIE_PORT_LINK_CONTROL, + PORT_LINK_FAST_LINK_MODE, PORT_LINK_DLL_LINK_EN); =20 dw_pcie_link_set_max_link_width(pci, pci->num_lanes); } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index f401c144df0f..5a0aa154eb2a 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -720,24 +720,14 @@ static inline void dw_pcie_clear_and_set_dword(struct= dw_pcie *pci, int pos, =20 static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci) { - u32 reg; - u32 val; - - reg =3D PCIE_MISC_CONTROL_1_OFF; - val =3D dw_pcie_readl_dbi(pci, reg); - val |=3D PCIE_DBI_RO_WR_EN; - dw_pcie_writel_dbi(pci, reg, val); + dw_pcie_clear_and_set_dword(pci, PCIE_MISC_CONTROL_1_OFF, + 0, PCIE_DBI_RO_WR_EN); } =20 static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci) { - u32 reg; - u32 val; - - reg =3D PCIE_MISC_CONTROL_1_OFF; - val =3D dw_pcie_readl_dbi(pci, reg); - val &=3D ~PCIE_DBI_RO_WR_EN; - dw_pcie_writel_dbi(pci, reg, val); + dw_pcie_clear_and_set_dword(pci, PCIE_MISC_CONTROL_1_OFF, + PCIE_DBI_RO_WR_EN, 0); } =20 static inline int dw_pcie_start_link(struct dw_pcie *pci) --=20 2.25.1 From nobody Wed Dec 17 10:45:09 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.5]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B293B2EF9DB; Wed, 18 Jun 2025 15:21:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750260101; cv=none; b=CoGFXMBcCKFxDWFeF3RmXnH8LERO2DVMjK9PpHNEgJoDINRI+UZMRcdJ0KzkDBIbjdBev+CGNrSaL75EYH5Dufl4JZnAPzLgRe9/4i0cracdSRctYVZFiM3cqjcb44N0EyN66P3cK8pZCsp1hyA/D5ZtlR+WOILFxv5GvfntKvY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750260101; c=relaxed/simple; bh=Aval5zk1VgFJgPoCb1Z+VYhn5vHXyVwG2wThqQn9Cg0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; 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Wed, 18 Jun 2025 23:21:17 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, mani@kernel.org, kwilczynski@kernel.org Cc: robh@kernel.org, jingoohan1@gmail.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 03/13] PCI: dra7xx: Refactor code by using dw_pcie_clear_and_set_dword() Date: Wed, 18 Jun 2025 23:21:02 +0800 Message-Id: <20250618152112.1010147-4-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250618152112.1010147-1-18255117159@163.com> References: <20250618152112.1010147-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDHoedq2VJo3qQFAQ--.15407S5 X-Coremail-Antispam: 1Uf129KBjvJXoW7KrWkGrWkKr1xuFyrXF13Jwb_yoW8uw4xp3 y3CFZIk3W7Jan5X3Wqv3Wku3WSvasavr4Utan7Kw1fZF9Fyr9rtrWFyry8tF4fuFWj9r12 ka15t347Xw4YyFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zRhSdkUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiQxBwo2hS1CaCCAABsD Content-Type: text/plain; charset="utf-8" The dra7xx PCIe driver implements suspend/resume handling through direct register manipulation. The current approach uses explicit read-modify-write sequences to control the MEMORY enable bit in the PCI_COMMAND register, declaring local variables for temporary storage. Replace manual bit manipulation with dw_pcie_clear_and_set_dword() during suspend and resume operations. This eliminates redundant variable declarations and simplifies the power management flow by handling bit operations within a single function call. Using the centralized helper improves code readability and aligns the driver with standard DesignWare register access patterns. The change also reduces the risk of bit manipulation errors in future modifications to the power management logic. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pci-dra7xx.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controll= er/dwc/pci-dra7xx.c index f97f5266d196..9cbba1b28882 100644 --- a/drivers/pci/controller/dwc/pci-dra7xx.c +++ b/drivers/pci/controller/dwc/pci-dra7xx.c @@ -867,15 +867,12 @@ static int dra7xx_pcie_suspend(struct device *dev) { struct dra7xx_pcie *dra7xx =3D dev_get_drvdata(dev); struct dw_pcie *pci =3D dra7xx->pci; - u32 val; =20 if (dra7xx->mode !=3D DW_PCIE_RC_TYPE) return 0; =20 /* clear MSE */ - val =3D dw_pcie_readl_dbi(pci, PCI_COMMAND); - val &=3D ~PCI_COMMAND_MEMORY; - dw_pcie_writel_dbi(pci, PCI_COMMAND, val); + dw_pcie_clear_and_set_dword(pci, PCI_COMMAND, PCI_COMMAND_MEMORY, 0); =20 return 0; } @@ -884,15 +881,12 @@ static int dra7xx_pcie_resume(struct device *dev) { struct dra7xx_pcie *dra7xx =3D dev_get_drvdata(dev); struct dw_pcie *pci =3D dra7xx->pci; - u32 val; =20 if (dra7xx->mode !=3D DW_PCIE_RC_TYPE) return 0; =20 /* set MSE */ - val =3D dw_pcie_readl_dbi(pci, PCI_COMMAND); - val |=3D PCI_COMMAND_MEMORY; - dw_pcie_writel_dbi(pci, PCI_COMMAND, val); + dw_pcie_clear_and_set_dword(pci, PCI_COMMAND, 0, PCI_COMMAND_MEMORY); =20 return 0; } --=20 2.25.1 From nobody Wed Dec 17 10:45:09 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.3]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 97F732EF2A8; Wed, 18 Jun 2025 15:21:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750260090; cv=none; b=O0ohUezQ11UhtMMM7+PUy+9R0prQ63Lakp/p7pVYmL2A9bCv0XpemhTMnEI/pIAIIl7IxoAuy6ICrrqRyyzRq3R5wWksdNS++XG8hOSoqT3Y2dpCu+XnXKRJaFpfxkxUgzuzyj72n3UxRJMwyx1elKybzG4ZZpZwrfaDJIqHsjY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750260090; c=relaxed/simple; bh=pI0l0YSyaG+iu/wKlfA/GQax2jc8og3id13WIdSvnbE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nAoBO81gLLenz42m5asHrsGgGA+WA/3vsbeKIoZymNimesXZNtqUJo+Lyk6hYjb6gRcQH2hQ+wkcvA0UoFEn/LL1iaN8Uth4ZoY+MLMZlJiKtV3DSCg7bYUbf982cow+szhY7U/ebPQmt4JYZTY2kSLBSWOyZByPcsUugs9Z/co= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=dyU2Y7LB; arc=none smtp.client-ip=117.135.210.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="dyU2Y7LB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=7u 2cvwu+TRfW10klrZP0lybKTwAtimvuf2CQdNrVCxs=; b=dyU2Y7LBrkjatMe1yO +t+RC+U551wyuXp2uUgZJjiR/ZJiwxbSK5+P/FrnjivduHypRF4YEyerWvABHNbC Jo+skDeK+Fopf72tgPpKWZAS/o2jWPjb4jocKi9HVc2PvQB1WNA/Cl/YUu3hmGR5 m5WKPSylYf0LEXofQGNJZ2ROk= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g0-3 (Coremail) with SMTP id _____wDHoedq2VJo3qQFAQ--.15407S6; Wed, 18 Jun 2025 23:21:17 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, mani@kernel.org, kwilczynski@kernel.org Cc: robh@kernel.org, jingoohan1@gmail.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 04/13] PCI: imx6: Refactor code by using dw_pcie_clear_and_set_dword() Date: Wed, 18 Jun 2025 23:21:03 +0800 Message-Id: <20250618152112.1010147-5-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250618152112.1010147-1-18255117159@163.com> References: <20250618152112.1010147-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDHoedq2VJo3qQFAQ--.15407S6 X-Coremail-Antispam: 1Uf129KBjvJXoWxJw4UCFyxtw18XF48Xr1fZwb_yoWrGFykpa y2vrnakF48JF4F9w4vya95XF13t3Z3CF4UGanrKwnaqFy2kr9rtayjy34ftFs7GFWjvryj 9w18tw47J3WYyF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pEfM3_UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiQxdwo2hS1CaCDAABsA Content-Type: text/plain; charset="utf-8" i.MX6 PCIe driver contains multiple read-modify-write sequences for link training and speed configuration. These operations manually handle bit masking and shifting to update specific fields in control registers, particularly for link capabilities and speed change initiation. Refactor link capability configuration and speed change handling using dw_pcie_clear_and_set_dword(). The helper simplifies LNKCAP modification by encapsulating bit clear/set operations and eliminates intermediate variables. For speed change control, replace explicit bit manipulation with direct register updates through the helper. Adopting the standard interface reduces code complexity in link training paths and ensures consistent handling of speed-related bits. The change also prepares the driver for future enhancements to Gen3 link training by centralizing bit manipulation logic. Signed-off-by: Hans Zhang <18255117159@163.com> Reviewed-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 26 ++++++++++---------------- 1 file changed, 10 insertions(+), 16 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 5a38cfaf989b..3004e432f013 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -941,7 +941,6 @@ static int imx_pcie_start_link(struct dw_pcie *pci) struct imx_pcie *imx_pcie =3D to_imx_pcie(pci); struct device *dev =3D pci->dev; u8 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - u32 tmp; int ret; =20 if (!(imx_pcie->drvdata->flags & @@ -956,10 +955,9 @@ static int imx_pcie_start_link(struct dw_pcie *pci) * bus will not be detected at all. This happens with PCIe switches. */ dw_pcie_dbi_ro_wr_en(pci); - tmp =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); - tmp &=3D ~PCI_EXP_LNKCAP_SLS; - tmp |=3D PCI_EXP_LNKCAP_SLS_2_5GB; - dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); + dw_pcie_clear_and_set_dword(pci, offset + PCI_EXP_LNKCAP, + PCI_EXP_LNKCAP_SLS, + PCI_EXP_LNKCAP_SLS_2_5GB); dw_pcie_dbi_ro_wr_dis(pci); =20 /* Start LTSSM. */ @@ -972,18 +970,16 @@ static int imx_pcie_start_link(struct dw_pcie *pci) =20 /* Allow faster modes after the link is up */ dw_pcie_dbi_ro_wr_en(pci); - tmp =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); - tmp &=3D ~PCI_EXP_LNKCAP_SLS; - tmp |=3D pci->max_link_speed; - dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); + dw_pcie_clear_and_set_dword(pci, offset + PCI_EXP_LNKCAP, + PCI_EXP_LNKCAP_SLS, + pci->max_link_speed); =20 /* * Start Directed Speed Change so the best possible * speed both link partners support can be negotiated. */ - tmp =3D dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); - tmp |=3D PORT_LOGIC_SPEED_CHANGE; - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); + dw_pcie_clear_and_set_dword(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, + 0, PORT_LOGIC_SPEED_CHANGE); dw_pcie_dbi_ro_wr_dis(pci); =20 ret =3D imx_pcie_wait_for_speed_change(imx_pcie); @@ -1295,7 +1291,6 @@ static void imx_pcie_host_post_init(struct dw_pcie_rp= *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); struct imx_pcie *imx_pcie =3D to_imx_pcie(pci); - u32 val; =20 if (imx_pcie->drvdata->flags & IMX_PCIE_FLAG_8GT_ECN_ERR051586) { /* @@ -1310,9 +1305,8 @@ static void imx_pcie_host_post_init(struct dw_pcie_rp= *pp) * to 0. */ dw_pcie_dbi_ro_wr_en(pci); - val =3D dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); - val &=3D ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); + dw_pcie_clear_and_set_dword(pci, GEN3_RELATED_OFF, + GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL, 0); dw_pcie_dbi_ro_wr_dis(pci); } } --=20 2.25.1 From nobody Wed Dec 17 10:45:09 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.2]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3BA522EFD8F; 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charset="utf-8" Meson PCIe driver implements payload size configuration through manual register manipulation. The current code reads device control registers, modifies specific bitfields for maximum payload and read request sizes, then writes back the updated values. This pattern repeats twice with similar logic but different bit masks. Replace explicit bit manipulation with dw_pcie_clear_and_set_dword() for payload and read request size configuration. The helper consolidates read-clear-set-write operations into a single call, eliminating redundant register read operations and local variable usage. This refactoring reduces code duplication in size configuration logic and improves maintainability. By using the DesignWare helper, the driver aligns with standard PCIe controller programming patterns and simplifies future updates to device capability settings. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pci-meson.c | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controlle= r/dwc/pci-meson.c index 787469d1b396..cd6280a8e619 100644 --- a/drivers/pci/controller/dwc/pci-meson.c +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -264,33 +264,27 @@ static int meson_size_to_payload(struct meson_pcie *m= p, int size) static void meson_set_max_payload(struct meson_pcie *mp, int size) { struct dw_pcie *pci =3D &mp->pci; - u32 val; u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); int max_payload_size =3D meson_size_to_payload(mp, size); =20 - val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); - val &=3D ~PCI_EXP_DEVCTL_PAYLOAD; - dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val); + dw_pcie_clear_and_set_dword(pci, offset + PCI_EXP_DEVCTL, + PCI_EXP_DEVCTL_PAYLOAD, 0); =20 - val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); - val |=3D PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size); - dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val); + dw_pcie_clear_and_set_dword(pci, offset + PCI_EXP_DEVCTL, 0, + PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size)); } =20 static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size) { struct dw_pcie *pci =3D &mp->pci; - u32 val; u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); int max_rd_req_size =3D meson_size_to_payload(mp, size); =20 - val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); - val &=3D ~PCI_EXP_DEVCTL_READRQ; - dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val); + dw_pcie_clear_and_set_dword(pci, offset + PCI_EXP_DEVCTL, + PCI_EXP_DEVCTL_READRQ, 0); =20 - val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); - val |=3D PCIE_CAP_MAX_READ_REQ_SIZE(max_rd_req_size); - dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val); + dw_pcie_clear_and_set_dword(pci, offset + PCI_EXP_DEVCTL, 0, + PCIE_CAP_MAX_READ_REQ_SIZE(max_rd_req_size)); } =20 static int meson_pcie_start_link(struct dw_pcie *pci) --=20 2.25.1 From nobody Wed Dec 17 10:45:09 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.2]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 35C932EF9C0; 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charset="utf-8" Armada8k PCIe driver uses explicit bitwise operations for global control register configuration. The driver manually handles bit masking and shifting for multiple fields including device type, domain attributes, and interrupt masking. This approach requires repetitive read-modify-write sequences and temporary variables. Refactor global control setup, domain attribute configuration, and interrupt masking using dw_pcie_clear_and_set_dword(). The helper replaces manual bit manipulation with declarative bit masks, directly specifying which bits to clear and set. This eliminates intermediate variables and reduces code complexity. Standardizing on the helper improves code clarity in initialization paths and ensures consistent handling of control register bits. The change also centralizes bit manipulation logic, reducing the risk of errors in future modifications to device configuration. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-armada8k.c | 48 ++++++++-------------- 1 file changed, 18 insertions(+), 30 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/contr= oller/dwc/pcie-armada8k.c index c2650fd0d458..67348307aa28 100644 --- a/drivers/pci/controller/dwc/pcie-armada8k.c +++ b/drivers/pci/controller/dwc/pcie-armada8k.c @@ -155,54 +155,44 @@ static bool armada8k_pcie_link_up(struct dw_pcie *pci) =20 static int armada8k_pcie_start_link(struct dw_pcie *pci) { - u32 reg; - /* Start LTSSM */ - reg =3D dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); - reg |=3D PCIE_APP_LTSSM_EN; - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); + dw_pcie_clear_and_set_dword(pci, PCIE_GLOBAL_CONTROL_REG, + 0, PCIE_APP_LTSSM_EN); =20 return 0; } =20 static int armada8k_pcie_host_init(struct dw_pcie_rp *pp) { - u32 reg; struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); =20 - if (!dw_pcie_link_up(pci)) { + if (!dw_pcie_link_up(pci)) /* Disable LTSSM state machine to enable configuration */ - reg =3D dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); - reg &=3D ~(PCIE_APP_LTSSM_EN); - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); - } + dw_pcie_clear_and_set_dword(pci, PCIE_GLOBAL_CONTROL_REG, + PCIE_APP_LTSSM_EN, 0); =20 /* Set the device to root complex mode */ - reg =3D dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); - reg &=3D ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT); - reg |=3D PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT; - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); + dw_pcie_clear_and_set_dword(pci, PCIE_GLOBAL_CONTROL_REG, + PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT, + PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT); =20 /* Set the PCIe master AxCache attributes */ dw_pcie_writel_dbi(pci, PCIE_ARCACHE_TRC_REG, ARCACHE_DEFAULT_VALUE); dw_pcie_writel_dbi(pci, PCIE_AWCACHE_TRC_REG, AWCACHE_DEFAULT_VALUE); =20 /* Set the PCIe master AxDomain attributes */ - reg =3D dw_pcie_readl_dbi(pci, PCIE_ARUSER_REG); - reg &=3D ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); - reg |=3D DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; - dw_pcie_writel_dbi(pci, PCIE_ARUSER_REG, reg); + dw_pcie_clear_and_set_dword(pci, PCIE_ARUSER_REG, + AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT, + DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT); =20 - reg =3D dw_pcie_readl_dbi(pci, PCIE_AWUSER_REG); - reg &=3D ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); - reg |=3D DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; - dw_pcie_writel_dbi(pci, PCIE_AWUSER_REG, reg); + dw_pcie_clear_and_set_dword(pci, PCIE_AWUSER_REG, + AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT, + DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT); =20 /* Enable INT A-D interrupts */ - reg =3D dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG); - reg |=3D PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK | - PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK; - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg); + dw_pcie_clear_and_set_dword(pci, PCIE_GLOBAL_INT_MASK1_REG, 0, + PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK | + PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK); =20 return 0; } @@ -211,15 +201,13 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq,= void *arg) { struct armada8k_pcie *pcie =3D arg; struct dw_pcie *pci =3D pcie->pci; - u32 val; =20 /* * Interrupts are directly handled by the device driver of the * PCI device. However, they are also latched into the PCIe * controller, so we simply discard them. */ - val =3D dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG); - dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG, val); + dw_pcie_clear_and_set_dword(pci, PCIE_GLOBAL_INT_CAUSE1_REG, 0, 0); =20 return IRQ_HANDLED; } --=20 2.25.1 From nobody Wed Dec 17 10:45:09 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.3]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4EB3E2EFD94; Wed, 18 Jun 2025 15:21:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750260103; cv=none; b=tjm+NDFVClindGPJ4VXN7dox/k/HUK9s5aAyEMO4Bn5Ie2EX41iNZ66KgviNO9oFqacyIGZCSd17iB5RPvQ/NOAlnLZkIoxXMAwbr7XrX3uVzpdrp7f2bfIBLCknD4BH9t6YF+MRICzeBbUGQK9GcNVzf9Ng0mWwPmWSBBATV/Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750260103; c=relaxed/simple; bh=QsvVTVjEukMOXgp7vsAJHkEP4QuiyFrtI+Q8YTeyeFg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=PZOkxojhIGMbDDdc1qmnU8h3k3hpMrDzSuvr0+OSYKYlD7Q0Yqp6+ugzj/+RbZujHMMBBqdXVAuontMqzr6e+aCtwSCBqHOfQzsTf7EVfAdM2thoXvbgdWpcaB0iftryEyDZyYzfju04UpaNQAU2hsZw5dp7Hgl6soGojsYiFqc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=PlpPLCAk; arc=none smtp.client-ip=220.197.31.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="PlpPLCAk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=04 fcvJHUcanUs3BderAdxY1w8bpBTNk29ppsje+kwjk=; b=PlpPLCAksLt/HRoZ5Y /EiJR5EueBtclAWbEVdnZ+JPd42M5xU/kPeH5+a32wYp0pCpZe6hz260npjMh8uO hYUkCh8pV8+VvsdA2cR322IMJrtBxDW4A43NOs3r44k/3yTTXtbCaBgoeaxz02nA SuZvH3iEELBErWrKZ+OrdHoKc= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g0-4 (Coremail) with SMTP id _____wBXvXd32VJoWFISAQ--.22704S4; Wed, 18 Jun 2025 23:21:29 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, mani@kernel.org, kwilczynski@kernel.org Cc: robh@kernel.org, jingoohan1@gmail.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 07/13] PCI: bt1: Refactor code by using dw_pcie_clear_and_set_dword() Date: Wed, 18 Jun 2025 23:21:06 +0800 Message-Id: <20250618152112.1010147-8-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250618152112.1010147-1-18255117159@163.com> References: <20250618152112.1010147-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wBXvXd32VJoWFISAQ--.22704S4 X-Coremail-Antispam: 1Uf129KBjvJXoW7Zry8Xw4xCw48Gr45uF4xXrb_yoW8ArW7pa 9IkF92kF12ya1Y9a1Ut3Z7ZFyYgan5CayjgFn7Kw1IgF9Iyr9rWFyrKFy3trZxJr4Iqr1a 9w1UtFW7uan8ArUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0z_GYLPUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiOgBwo2hS1URmDAAAso Content-Type: text/plain; charset="utf-8" Baikal-T1 PCIe driver contains a direct register write to initiate speed change during link training. The current implementation sets the PORT_LOGIC_SPEED_CHANGE bit via read-modify-write without using the standard bit manipulation helper. Replace manual bit set operation with dw_pcie_clear_and_set_dword() to enable speed change. The helper clearly expresses the intent to modify a specific bit while preserving others, eliminating the need for explicit read-before-write. Using the standardized interface improves consistency with other DesignWare drivers and reduces the risk of unintended bit modifications. The change also simplifies future updates to link training logic. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-bt1.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-bt1.c b/drivers/pci/controller= /dwc/pcie-bt1.c index 1340edc18d12..7cbaeeed033d 100644 --- a/drivers/pci/controller/dwc/pcie-bt1.c +++ b/drivers/pci/controller/dwc/pcie-bt1.c @@ -289,9 +289,8 @@ static int bt1_pcie_start_link(struct dw_pcie *pci) * attempt to reach a higher bus performance (up to Gen.3 - 8.0 GT/s). * This is required at least to get 8.0 GT/s speed. */ - val =3D dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); - val |=3D PORT_LOGIC_SPEED_CHANGE; - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); + dw_pcie_clear_and_set_dword(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, + 0, PORT_LOGIC_SPEED_CHANGE); =20 ret =3D regmap_read_poll_timeout(btpci->sys_regs, BT1_CCU_PCIE_PMSC, val, BT1_CCU_PCIE_LTSSM_LINKUP(val), --=20 2.25.1 From nobody Wed Dec 17 10:45:09 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.2]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 295622EFDB7; Wed, 18 Jun 2025 15:21:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750260105; cv=none; b=ClW7oLQyDwaDWUZwKfcbNoIZloH5ey/+7+UVd1WWU3uyPg2RuJP7l7qKUtiFZSEJvCRBY8+UMTX4pSWpj/e2a3SwK7yrJjqF0UzOve5dvaOZ49aGDZDCGeKnNKgoG3d0Gw/7gK6i6cm6bjfjTGqfav/+Drv2ekwUnFVdoilQmBw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750260105; c=relaxed/simple; bh=uHw15SEfgJhjk0plrbNOxwEmIEjDnYKRuTeithPcYq8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=cEAzuqUfUPZDVpIMWLZfcF27TB4nmbS+sYu6kc0wdnWcC5/QHj2Wl3gTMvUdlhjp9T47+TSrhEQwF5o97RF6agr+2xEmLzMbs7eqbCwqEXPsgWTeL+HxUW857F8enRhMxOf5Qs24NW1tiZT29DevXzLAWw7CiBcMGY51vMQLO3k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=Uhmj0vaq; arc=none smtp.client-ip=220.197.31.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="Uhmj0vaq" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=lz 037P2kaVzqsQ34A3LWfibKKWlS33MGjH64LQLCkDA=; b=Uhmj0vaq/FSWYCyHKK SXCv5pl1QkZldRIcz/5204acUf9cunLphDScBHvQiCD4ArzM3PAS/Ok5ztXD8LlX d/P9ZbyAXxdOwZm7MaydmZjjZgr/si62tHhjVCbp5ngzqg5UhY0E9vtc1sdu29dJ k7GAcTfEcuSFQdQCVwCV/iQ5A= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g0-4 (Coremail) with SMTP id _____wBXvXd32VJoWFISAQ--.22704S5; Wed, 18 Jun 2025 23:21:29 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, mani@kernel.org, kwilczynski@kernel.org Cc: robh@kernel.org, jingoohan1@gmail.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 08/13] PCI: dw-rockchip: Refactor code by using dw_pcie_clear_and_set_dword() Date: Wed, 18 Jun 2025 23:21:07 +0800 Message-Id: <20250618152112.1010147-9-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250618152112.1010147-1-18255117159@163.com> References: <20250618152112.1010147-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wBXvXd32VJoWFISAQ--.22704S5 X-Coremail-Antispam: 1Uf129KBjvJXoW7tw1rGr4Dtr1DJF1ruw18Grg_yoW8CrW5p3 y3Aa4akF4rJw4rua1kAa97ZF13ta9xAFW7JFZ3Gw1SqFy2k34DKF1YkFyaqF1xGr42vF1a 93yUt3yUZa13AFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zR2jg3UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiOhFwo2hS1URmFgAAsj Content-Type: text/plain; charset="utf-8" Rockchip PCIe driver implements L0s capability enablement through explicit register read-modify-write. The current approach reads the LNKCAP register, modifies the ASPM_L0S bit, then writes back the value with DBI write protection handling. Refactor ASPM capability configuration using dw_pcie_clear_and_set_dword(). The helper combines bit manipulation with DBI protection in a single call, replacing three-step manual operations. This simplifies the capability setup flow and reduces code complexity. Adopting the standard helper improves maintainability by eliminating local variables and explicit bitwise operations. The change also ensures consistent handling of DBI write protection across capability modification functions. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index 93171a392879..e6bd9c54b164 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -194,15 +194,14 @@ static bool rockchip_pcie_link_up(struct dw_pcie *pci) =20 static void rockchip_pcie_enable_l0s(struct dw_pcie *pci) { - u32 cap, lnkcap; + u32 cap; =20 /* Enable L0S capability for all SoCs */ cap =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); if (cap) { - lnkcap =3D dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); - lnkcap |=3D PCI_EXP_LNKCAP_ASPM_L0S; dw_pcie_dbi_ro_wr_en(pci); - dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap); + dw_pcie_clear_and_set_dword(pci, cap + PCI_EXP_LNKCAP, + 0, PCI_EXP_LNKCAP_ASPM_L0S); dw_pcie_dbi_ro_wr_dis(pci); } } --=20 2.25.1 From nobody Wed Dec 17 10:45:09 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.2]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AB8AE2EFDA8; Wed, 18 Jun 2025 15:21:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750260105; cv=none; b=hvAnf9CwvSNYPD6ObwirapklMLZbV+gL4p6h4AugeVaC53AfR/0lraKo3qoDagz9vdehnyHlCdZTV4xTihGMIjiSWnFs7ZPxNAP9uhJ0sMJMF8LYwY5JRnb74U+JGo4Y8pInXlgb7hGo1uSQal+ePJdtzsODVXpTChqY7M5SO5U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750260105; c=relaxed/simple; bh=ADdaQPFkRSO+VSTMlCDm3GecCwInkppbcV9rC+ipPes=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FsJFBZTKZhj0oY23TmYF/Lrd4jHcbrnngGz60LKlHFUiDIqfn1zdmz+w0ZGBmpsVYoaTEc1xvQArc8jZdojCX9z4Q1h+/HMsI42HAa2P8qpRAMcE+NgywklRWp19nuCYtE1fw+PAozvbwmNB0SgqwWzWXeLB92YDUzUzUsRNE/Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=Ceipa55a; arc=none smtp.client-ip=117.135.210.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="Ceipa55a" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=KS hWwqB6/OjriKH/vh/97toS6aO3gRr/LJ9FfGdZTCo=; b=Ceipa55aiTqlOlDnTa b3rv1qG+5RmvXX0DrsSSzWMF7EqvaYe68o+8stlW6+8lDWGyv5eNfQNiEZTY3Cr+ Vu7XMbTntmpJyva7BkgUP5AR0hLo873uIIEQggQziKuMEd5dfcmvn7VcKwoi0TrX IEUSbIYFbRBzFadlZ0GVdF4TQ= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g0-4 (Coremail) with SMTP id _____wBXvXd32VJoWFISAQ--.22704S6; Wed, 18 Jun 2025 23:21:30 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, mani@kernel.org, kwilczynski@kernel.org Cc: robh@kernel.org, jingoohan1@gmail.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 09/13] PCI: fu740: Refactor code by using dw_pcie_clear_and_set_dword() Date: Wed, 18 Jun 2025 23:21:08 +0800 Message-Id: <20250618152112.1010147-10-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250618152112.1010147-1-18255117159@163.com> References: <20250618152112.1010147-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wBXvXd32VJoWFISAQ--.22704S6 X-Coremail-Antispam: 1Uf129KBjvJXoW7tF1DGrWDuryrAw1rWryUWrg_yoW8WrWxpa y2yrWrCF1UJa1ru3WUJa4kZF1agas3CFWUWFs7Wwn29F9FyrWDWFWrta43tFyxGF4Iqr1a kw1Utay7WF1ayFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pE66wLUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiOhFwo2hS1URmFgABsi Content-Type: text/plain; charset="utf-8" SiFive FU740 PCIe driver uses direct register write to initiate link speed change after setting target link capabilities. The current implementation sets PORT_LOGIC_SPEED_CHANGE bit via explicit read-modify-write sequence. Replace manual bit manipulation with dw_pcie_clear_and_set_dword() for speed change initiation. The helper encapsulates read-modify-write operations while providing clear intent through "clear 0, set BIT" usage. This refactoring aligns the driver with standard DesignWare programming patterns and reduces code complexity. The change also ensures consistent handling of speed change initiation across all DesignWare base controllers. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-fu740.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-fu740.c b/drivers/pci/controll= er/dwc/pcie-fu740.c index 66367252032b..8210ff1fd91e 100644 --- a/drivers/pci/controller/dwc/pcie-fu740.c +++ b/drivers/pci/controller/dwc/pcie-fu740.c @@ -216,9 +216,8 @@ static int fu740_pcie_start_link(struct dw_pcie *pci) tmp |=3D orig; dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCAP, tmp); =20 - tmp =3D dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); - tmp |=3D PORT_LOGIC_SPEED_CHANGE; - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); + dw_pcie_clear_and_set_dword(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, + 0, PORT_LOGIC_SPEED_CHANGE); =20 ret =3D dw_pcie_wait_for_link(pci); if (ret) { --=20 2.25.1 From nobody Wed Dec 17 10:45:09 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.4]) by smtp.subspace.kernel.org (Postfix) with ESMTP id F09D22EF66B; Wed, 18 Jun 2025 15:21:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750260121; cv=none; b=sFCySyu/mAae6ufKDMAMOO1Sttcifk/UihYxPY/hu1SbIawWaXNwGk1eC+m78sihNSyKDE8+5OwIg2Z6x8nSh1b4A5zP5F3DwBFBSO/OEm5Z1/oB1Ghw4J1hHy3abOkjXqJJwZNR1G50N/rP81bgVIZ1PJb7FjL982ZyACTHayw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750260121; c=relaxed/simple; bh=oFApSBDY+OxxnOA0P3lT0lMEWBUJm37uUIdc7A3fBPk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HuPPgN98eMlcehCyT+7aRvWs3oz0asgyYuZojnnJQq9WMYnbg95of3NX0YuFXqNbc9mHgc8fo9HmuFQkOn5FoO0nJwN20pFWThXaIqbi4qp1zJ/LFi2EFdkQmcTXsMEuIUs5hKVLBrmttu481z0xD+GPHSqlm5aErjGEZfD0YHc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=LGO+Bbah; arc=none smtp.client-ip=117.135.210.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="LGO+Bbah" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=lN RcWaeVw9b8wcrD5zFUisNHEU5ftFol/Wu2HmY6NWU=; b=LGO+BbahFaqPgoCH+w xlRt3mQRHCekAQ6k8Ynucs5dS5YDZ4ZymTnu8JLhKgNm4CHCXvzeElsYMH8/7ZaD HPsniMhmSGflZRHKhLtsbhbIUMlGzcoDndlAbxLAiINHPX1BlKqjkQmxBEazwRtb jygu0IfYMYyapjafrur42uRzY= Received: from localhost.localdomain (unknown []) by gzsmtp5 (Coremail) with SMTP id QCgvCgBnr96E2VJo_+eqAA--.17078S2; Wed, 18 Jun 2025 23:21:41 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, mani@kernel.org, kwilczynski@kernel.org Cc: robh@kernel.org, jingoohan1@gmail.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 10/13] PCI: qcom: Refactor code by using dw_pcie_clear_and_set_dword() Date: Wed, 18 Jun 2025 23:21:09 +0800 Message-Id: <20250618152112.1010147-11-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250618152112.1010147-1-18255117159@163.com> References: <20250618152112.1010147-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: QCgvCgBnr96E2VJo_+eqAA--.17078S2 X-Coremail-Antispam: 1Uf129KBjvJXoWxKF4rAryxWr1DAw1xWr4kZwb_yoW7Ww48pw 10k3Z7JFn7AF40939Iyan7Xr1FkFZxur42k3W3tanFv3Z7AFZFgay5tasrKr1xGFW7KFy2 k34UAFW7Gr1SkrUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pigyC9UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiOhRwo2hS1URnOgAAsL Content-Type: text/plain; charset="utf-8" Qcom PCIe common code contains complex bit manipulation for 16GT/s equalization and lane margining configuration. These functions use multiple read-modify-write sequences with manual bit masking and field preparation, leading to verbose and error-prone code. Refactor equalization and lane margining setup using dw_pcie_clear_and_set_dword(). The helper simplifies multi-field configuration by combining clear and set operations in a single call. Initialize local variables to zero before field insertion to ensure unused bits are cleared appropriately. This change reduces code complexity by ~40% in affected functions while improving readability. Centralizing bit manipulation ensures consistent handling of register fields across Qcom PCIe implementations and provides a solid foundation for future 16GT/s enhancements. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-qcom-common.c | 59 +++++++++---------- 1 file changed, 29 insertions(+), 30 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.c b/drivers/pci/co= ntroller/dwc/pcie-qcom-common.c index 3aad19b56da8..8ea521147b7e 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-common.c +++ b/drivers/pci/controller/dwc/pcie-qcom-common.c @@ -10,7 +10,7 @@ =20 void qcom_pcie_common_set_16gt_equalization(struct dw_pcie *pci) { - u32 reg; + u32 reg =3D 0; =20 /* * GEN3_RELATED_OFF register is repurposed to apply equalization @@ -19,60 +19,59 @@ void qcom_pcie_common_set_16gt_equalization(struct dw_p= cie *pci) * determines the data rate for which these equalization settings are * applied. */ - reg =3D dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); - reg &=3D ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; - reg &=3D ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; reg |=3D FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, GEN3_RELATED_OFF_RATE_SHADOW_SEL_16_0GT); - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg); + dw_pcie_clear_and_set_dword(pci, GEN3_RELATED_OFF, + GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL | + GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, + reg); =20 - reg =3D dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF); - reg &=3D ~(GEN3_EQ_FMDC_T_MIN_PHASE23 | - GEN3_EQ_FMDC_N_EVALS | - GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA | - GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA); + reg =3D 0; reg |=3D FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) | FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) | FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA, 0x5) | FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA, 0x5); - dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg); + dw_pcie_clear_and_set_dword(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, + GEN3_EQ_FMDC_T_MIN_PHASE23 | + GEN3_EQ_FMDC_N_EVALS | + GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA | + GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA, + reg); =20 - reg =3D dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); - reg &=3D ~(GEN3_EQ_CONTROL_OFF_FB_MODE | - GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE | - GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL | - GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC); - dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg); + dw_pcie_clear_and_set_dword(pci, GEN3_EQ_CONTROL_OFF, + GEN3_EQ_CONTROL_OFF_FB_MODE | + GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE | + GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL | + GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC, 0); } EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_equalization); =20 void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci) { - u32 reg; + u32 reg =3D 0; =20 - reg =3D dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_1_OFF); - reg &=3D ~(MARGINING_MAX_VOLTAGE_OFFSET | - MARGINING_NUM_VOLTAGE_STEPS | - MARGINING_MAX_TIMING_OFFSET | - MARGINING_NUM_TIMING_STEPS); reg |=3D FIELD_PREP(MARGINING_MAX_VOLTAGE_OFFSET, 0x24) | FIELD_PREP(MARGINING_NUM_VOLTAGE_STEPS, 0x78) | FIELD_PREP(MARGINING_MAX_TIMING_OFFSET, 0x32) | FIELD_PREP(MARGINING_NUM_TIMING_STEPS, 0x10); - dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_1_OFF, reg); + dw_pcie_clear_and_set_dword(pci, GEN4_LANE_MARGINING_1_OFF, + MARGINING_MAX_VOLTAGE_OFFSET | + MARGINING_NUM_VOLTAGE_STEPS | + MARGINING_MAX_TIMING_OFFSET | + MARGINING_NUM_TIMING_STEPS, reg); =20 - reg =3D dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_2_OFF); + reg =3D 0; reg |=3D MARGINING_IND_ERROR_SAMPLER | MARGINING_SAMPLE_REPORTING_METHOD | MARGINING_IND_LEFT_RIGHT_TIMING | MARGINING_VOLTAGE_SUPPORTED; - reg &=3D ~(MARGINING_IND_UP_DOWN_VOLTAGE | - MARGINING_MAXLANES | - MARGINING_SAMPLE_RATE_TIMING | - MARGINING_SAMPLE_RATE_VOLTAGE); reg |=3D FIELD_PREP(MARGINING_MAXLANES, pci->num_lanes) | FIELD_PREP(MARGINING_SAMPLE_RATE_TIMING, 0x3f) | FIELD_PREP(MARGINING_SAMPLE_RATE_VOLTAGE, 0x3f); - dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_2_OFF, reg); + dw_pcie_clear_and_set_dword(pci, GEN4_LANE_MARGINING_2_OFF, + MARGINING_IND_UP_DOWN_VOLTAGE | + MARGINING_MAXLANES | + MARGINING_SAMPLE_RATE_TIMING | + MARGINING_SAMPLE_RATE_VOLTAGE, reg); } EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_lane_margining); --=20 2.25.1 From nobody Wed Dec 17 10:45:09 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.3]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 74BB42EF66B; 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arc=none smtp.client-ip=117.135.210.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="KcaorCMr" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=+B Bjrc0EVkwRmuejXLpU8+j4fD1/hPN0cQ6RirtS1XI=; b=KcaorCMrMFuRM/1zlu OHLf+evk0XJyD3HX2bQUrhNY/FuVSCPewIMGarw8vFlw+lKmqTtjZdaFPvHfMKsO YUrKUcJUsELOByva+DP0UK0H5FDDarnCs/tfujCcwIHHirmjurVMQY4auXATjVcJ uw1X/cjwX41GH65wCrcZJMNZY= Received: from localhost.localdomain (unknown []) by gzsmtp5 (Coremail) with SMTP id QCgvCgBnr96E2VJo_+eqAA--.17078S3; Wed, 18 Jun 2025 23:21:41 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, mani@kernel.org, kwilczynski@kernel.org Cc: robh@kernel.org, jingoohan1@gmail.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 11/13] PCI: qcom-ep: Refactor code by using dw_pcie_clear_and_set_dword() Date: Wed, 18 Jun 2025 23:21:10 +0800 Message-Id: <20250618152112.1010147-12-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250618152112.1010147-1-18255117159@163.com> References: <20250618152112.1010147-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: QCgvCgBnr96E2VJo_+eqAA--.17078S3 X-Coremail-Antispam: 1Uf129KBjvJXoW7WF17Kr17ZF1UGr4rtrWUArb_yoW8Kr4Upr 9xXrn0kF1xJr4rur4qka1kZF15JFnxAFy3JFWDKw1avFy7CF9rtas0ya4aqFn7GrW2qryj 934YqayrW3WYyFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0z_wZ29UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiQwxwo2hS1CaEpwAAs3 Content-Type: text/plain; charset="utf-8" Qcom PCIe endpoint driver implements L0s/L1 latency configuration through manual register manipulation. The current approach reads LNKCAP register, modifies specific latency fields, then writes back the value. This pattern repeats twice with similar logic but different bit masks. Replace explicit latency configuration with dw_pcie_clear_and_set_dword(). The helper combines field clearing and setting in a single operation, replacing three-step manual sequences. Initialize the set value with FIELD_PREP() to clearly express the intended bitfield value. This refactoring reduces code duplication in latency configuration paths and improves maintainability. Using the standard helper ensures consistent handling of capability registers and simplifies future updates to ASPM settings. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/contro= ller/dwc/pcie-qcom-ep.c index bf7c6ac0f3e3..c2b4f172385d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -475,17 +475,15 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *p= ci) =20 /* Set the L0s Exit Latency to 2us-4us =3D 0x6 */ offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); - val &=3D ~PCI_EXP_LNKCAP_L0SEL; - val |=3D FIELD_PREP(PCI_EXP_LNKCAP_L0SEL, 0x6); - dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val); + dw_pcie_clear_and_set_dword(pci, offset + PCI_EXP_LNKCAP, + PCI_EXP_LNKCAP_L0SEL, + FIELD_PREP(PCI_EXP_LNKCAP_L0SEL, 0x6)); =20 /* Set the L1 Exit Latency to be 32us-64 us =3D 0x6 */ offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); - val &=3D ~PCI_EXP_LNKCAP_L1EL; - val |=3D FIELD_PREP(PCI_EXP_LNKCAP_L1EL, 0x6); - dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val); + dw_pcie_clear_and_set_dword(pci, offset + PCI_EXP_LNKCAP, + PCI_EXP_LNKCAP_L1EL, + FIELD_PREP(PCI_EXP_LNKCAP_L1EL, 0x6)); =20 dw_pcie_dbi_ro_wr_dis(pci); =20 --=20 2.25.1 From nobody Wed Dec 17 10:45:09 2025 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.4]) by smtp.subspace.kernel.org (Postfix) with ESMTP id F11F52EE99C; Wed, 18 Jun 2025 15:21:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750260122; cv=none; b=aOryQvqdyR+04r/kEMNCafanuNWQ8c6yhn6sn7VTm+Zc/7+oIukQQpQBwPz2hUgUM8pNcGtNu+386DqiEmsU2X1TQGV+phE+ojcWlMPX4vPTfJvob/0wtTQTirTFuQdE+OpgRbaoYWAdrsdzgYibZvECfRS6+IkaecHU5NLMDXY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750260122; c=relaxed/simple; bh=nE6bKO5dP5cXC6LWtFFk7yFnzldnKqo5QJozk1Lv45Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=pIC6DeskFrRsbXyopSEclsEksmfWSaCzob/wi4T5ltLEfr2mp5qKLBL3zQCM/zLYczwNPWqUcRmF+hJ3eboRJYe8DWunV3peTZAp8LWeqUcetC3h8E/sLOUzcN6eCk+e1Y8y/b07BNgsKpLzll+t5zMSXf3m0ah+38lpkyZ1wlk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=MBwaSglD; arc=none smtp.client-ip=117.135.210.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="MBwaSglD" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=Ae 9kCteaIREimUk/syr6kEJ201xf2z63OTJWk7zi+T4=; b=MBwaSglDG2ZYQmcuIh T3vytxpUaVjQtMemTU1ysmICA8ncB2t1b1lzlBos+Vnzxp6RIZktLhSX5kLeK8Ah cRT/ioiHuJ5r2gPlQihey+FzVQM0UX2K3HCgirEPUBBiAKX5B+Ga/H5HPXFI49M6 X8PbvnSMovmjmOiZGbqt7OUU4= Received: from localhost.localdomain (unknown []) by gzsmtp5 (Coremail) with SMTP id QCgvCgBnr96E2VJo_+eqAA--.17078S4; Wed, 18 Jun 2025 23:21:42 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, mani@kernel.org, kwilczynski@kernel.org Cc: robh@kernel.org, jingoohan1@gmail.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 12/13] PCI: rcar-gen4: Refactor code by using dw_pcie_clear_and_set_dword() Date: Wed, 18 Jun 2025 23:21:11 +0800 Message-Id: <20250618152112.1010147-13-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250618152112.1010147-1-18255117159@163.com> References: <20250618152112.1010147-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: QCgvCgBnr96E2VJo_+eqAA--.17078S4 X-Coremail-Antispam: 1Uf129KBjvJXoWxWFy3GF4Dtw48tF4DXr17GFg_yoW5Cry5pa y7CFySkF1jyws09F4UXaykur15uan3Ca1jg3Z7Gw1I9ay7ArZxWay0y3y7tFWxGFZ2qr45 Cw1UtFWUWF15ZFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0z_db1nUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWxVwo2hS1QJtrwAAsy Content-Type: text/plain; charset="utf-8" R-Car Gen4 PCIe driver contains multiple read-modify-write sequences for speed change control and lane configuration. The driver manually handles speed change initiation through bit set/clear operations and configures lane skew with explicit bit masking. Refactor speed change handling and lane skew configuration using dw_pcie_clear_and_set_dword(). For speed change operations, replace manual bit toggling with clear-and-set sequences. For lane skew, use the helper to conditionally set bits based on lane count. Adopting the standard interface simplifies link training logic and reduces code complexity. The change also ensures consistent handling of control register bits and provides better documentation of intent through declarative bit masks. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-rcar-gen4.c | 23 ++++++++------------- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/cont= roller/dwc/pcie-rcar-gen4.c index 18055807a4f5..20a6c88252d6 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -107,13 +107,11 @@ static int rcar_gen4_pcie_speed_change(struct dw_pcie= *dw) u32 val; int i; =20 - val =3D dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL); - val &=3D ~PORT_LOGIC_SPEED_CHANGE; - dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val); + dw_pcie_clear_and_set_dword(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, + PORT_LOGIC_SPEED_CHANGE, 0); =20 - val =3D dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL); - val |=3D PORT_LOGIC_SPEED_CHANGE; - dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val); + dw_pcie_clear_and_set_dword(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, + 0, PORT_LOGIC_SPEED_CHANGE); =20 for (i =3D 0; i < RCAR_NUM_SPEED_CHANGE_RETRIES; i++) { val =3D dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL); @@ -565,11 +563,9 @@ static void rcar_gen4_pcie_additional_common_init(stru= ct rcar_gen4_pcie *rcar) struct dw_pcie *dw =3D &rcar->dw; u32 val; =20 - val =3D dw_pcie_readl_dbi(dw, PCIE_PORT_LANE_SKEW); - val &=3D ~PORT_LANE_SKEW_INSERT_MASK; - if (dw->num_lanes < 4) - val |=3D BIT(6); - dw_pcie_writel_dbi(dw, PCIE_PORT_LANE_SKEW, val); + dw_pcie_clear_and_set_dword(dw, PCIE_PORT_LANE_SKEW, + PORT_LANE_SKEW_INSERT_MASK, + (dw->num_lanes < 4) ? BIT(6) : 0); =20 val =3D readl(rcar->base + PCIEPWRMNGCTRL); val |=3D APP_CLK_REQ_N | APP_CLK_PM_EN; @@ -680,9 +676,8 @@ static int rcar_gen4_pcie_ltssm_control(struct rcar_gen= 4_pcie *rcar, bool enable return 0; } =20 - val =3D dw_pcie_readl_dbi(dw, PCIE_PORT_FORCE); - val |=3D PORT_FORCE_DO_DESKEW_FOR_SRIS; - dw_pcie_writel_dbi(dw, PCIE_PORT_FORCE, val); + dw_pcie_clear_and_set_dword(dw, PCIE_PORT_FORCE, + 0, PORT_FORCE_DO_DESKEW_FOR_SRIS); =20 val =3D readl(rcar->base + PCIEMSR0); val |=3D APP_SRIS_MODE; --=20 2.25.1 From nobody Wed Dec 17 10:45:09 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EF7F22EE981; Wed, 18 Jun 2025 15:22:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750260123; cv=none; b=LXneU2zpO2SQ3fmC+8F68bkV9IjVDhb08/4Y/k9bb6pBiSICwIfdrPMmLmwZPia0lMn775Z8e4PwUjbiUynxHfJ7JjFsQe0q5OQWsr4LinoKCYQXvucu3Uh83GYeP1Z14Vh1BjbbpTzz57wlw3dPqc/zNeARsUWUgtqUuAB2c5A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750260123; c=relaxed/simple; bh=faM7ArohF9ySz3He9yNCX6OKTYTs+8Y3O0FLFiCc2vc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=eePz/B9J/Ks5SB9JjIAKJM0P4cDpSXiChYdtKBMA1jvu4o4vMYf/6tGctxShch5d9uNi6krTua6+OA8U1IhPv7d81FytYobMjKuKcFVmGPr7tVtvXdaquKhM+DQqJVU++RKEMEcYkM2sAhK4PJpqvgevf+QBhtoiTm0UuoIDp+0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=AXZHDQVb; arc=none smtp.client-ip=220.197.31.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="AXZHDQVb" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=5q XqETQd2PNkfZLHj4KgigghIhxiyg3po4s7tKNm+fg=; b=AXZHDQVb7EALDQv7P1 GIzHOVUAEUEAcnDFdlCGvpzMpoQeR7e1MPi0/Hl/q+T7JhWyW0O/7hQEOcOZLms2 GZ1si6oddwGtYXONdAn0SN9zWhDSZ/ACCcgAzfME+KwPul3Wi+f6J3GeT9RH8JKV 165sZMGzP7CgfUKyMdHeT932Y= Received: from localhost.localdomain (unknown []) by gzsmtp5 (Coremail) with SMTP id QCgvCgBnr96E2VJo_+eqAA--.17078S5; Wed, 18 Jun 2025 23:21:43 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, bhelgaas@google.com, mani@kernel.org, kwilczynski@kernel.org Cc: robh@kernel.org, jingoohan1@gmail.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 13/13] PCI: tegra194: Refactor code by using dw_pcie_clear_and_set_dword() Date: Wed, 18 Jun 2025 23:21:12 +0800 Message-Id: <20250618152112.1010147-14-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250618152112.1010147-1-18255117159@163.com> References: <20250618152112.1010147-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: QCgvCgBnr96E2VJo_+eqAA--.17078S5 X-Coremail-Antispam: 1Uf129KBjvAXoW3ur47Xw15Gr1xXry3AFy5urg_yoW8JF4UZo ZrJ3WkW3W7Jr1xta4YyFn3Kry7Jr4YvayrArZ2y3yj9as7KF15A393Kas8Aw12kr4fC34f Xw4kG3W3AFW7XryUn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UbIYCTnIWIevJa73UjIFyTuYvj4RA739UUUUU X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWxVwo2hS1QJtrwABsz Content-Type: text/plain; charset="utf-8" Tegra194 PCIe driver contains extensive manual bit manipulation across interrupt handling, ASPM configuration, and controller initialization. The driver implements complex read-modify-write sequences with explicit bit masking, leading to verbose and hard-to-maintain code. Refactor interrupt handling, ASPM setup, capability configuration, and controller initialization using dw_pcie_clear_and_set_dword(). Replace multi-step register modifications with single helper calls, eliminating intermediate variables and reducing code size by ~100 lines. For CDMA error handling, initialize the value variable to zero before setting status bits. This comprehensive refactoring significantly improves code readability and maintainability. Standardizing on the helper ensures consistent register access patterns across all driver components and reduces the risk of bit manipulation errors in this complex controller driver. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-tegra194.c | 155 +++++++++------------ 1 file changed, 64 insertions(+), 91 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index 4f26086f25da..c6f5c35a4be4 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -378,9 +378,8 @@ static irqreturn_t tegra_pcie_rp_irq_handler(int irq, v= oid *arg) val |=3D APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N; appl_writel(pcie, val, APPL_CAR_RESET_OVRD); =20 - val =3D dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); - val |=3D PORT_LOGIC_SPEED_CHANGE; - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); + dw_pcie_clear_and_set_dword(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, + 0, PORT_LOGIC_SPEED_CHANGE); } } =20 @@ -412,7 +411,7 @@ static irqreturn_t tegra_pcie_rp_irq_handler(int irq, v= oid *arg) =20 if (status_l0 & APPL_INTR_STATUS_L0_CDM_REG_CHK_INT) { status_l1 =3D appl_readl(pcie, APPL_INTR_STATUS_L1_18); - val =3D dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); + val =3D 0; if (status_l1 & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT) { dev_info(pci->dev, "CDM check complete\n"); val |=3D PCIE_PL_CHK_REG_CHK_REG_COMPLETE; @@ -425,7 +424,8 @@ static irqreturn_t tegra_pcie_rp_irq_handler(int irq, v= oid *arg) dev_err(pci->dev, "CDM Logic error\n"); val |=3D PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR; } - dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); + dw_pcie_clear_and_set_dword(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, + PORT_LOGIC_SPEED_CHANGE, val); val =3D dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_ERR_ADDR); dev_err(pci->dev, "CDM Error Address Offset =3D 0x%08X\n", val); } @@ -610,34 +610,27 @@ static struct pci_ops tegra_pci_ops =3D { #if defined(CONFIG_PCIEASPM) static void disable_aspm_l11(struct tegra_pcie_dw *pcie) { - u32 val; - - val =3D dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub); - val &=3D ~PCI_L1SS_CAP_ASPM_L1_1; - dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); + dw_pcie_clear_and_set_dword(&pcie->pci, pcie->cfg_link_cap_l1sub, + PCI_L1SS_CAP_ASPM_L1_1, 0); } =20 static void disable_aspm_l12(struct tegra_pcie_dw *pcie) { - u32 val; - - val =3D dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub); - val &=3D ~PCI_L1SS_CAP_ASPM_L1_2; - dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); + dw_pcie_clear_and_set_dword(&pcie->pci, pcie->cfg_link_cap_l1sub, + PCI_L1SS_CAP_ASPM_L1_2, 0); } =20 static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event) { - u32 val; + u32 val =3D 0; =20 - val =3D dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap + - PCIE_RAS_DES_EVENT_COUNTER_CONTROL); - val &=3D ~(EVENT_COUNTER_EVENT_SEL_MASK << EVENT_COUNTER_EVENT_SEL_SHIFT); val |=3D EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT; val |=3D event << EVENT_COUNTER_EVENT_SEL_SHIFT; val |=3D EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT; - dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap + - PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val); + dw_pcie_clear_and_set_dword(&pcie->pci, pcie->ras_des_cap + + PCIE_RAS_DES_EVENT_COUNTER_CONTROL, + EVENT_COUNTER_EVENT_SEL_MASK << EVENT_COUNTER_EVENT_SEL_SHIFT, + val); val =3D dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap + PCIE_RAS_DES_EVENT_COUNTER_DATA); =20 @@ -697,18 +690,20 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie) PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val); =20 /* Program T_cmrt and T_pwr_on values */ - val =3D dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub); - val &=3D ~(PCI_L1SS_CAP_CM_RESTORE_TIME | PCI_L1SS_CAP_P_PWR_ON_VALUE); + val =3D 0; val |=3D (pcie->aspm_cmrt << 8); val |=3D (pcie->aspm_pwr_on_t << 19); - dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val); + dw_pcie_clear_and_set_dword(pci, pcie->cfg_link_cap_l1sub, + PCI_L1SS_CAP_CM_RESTORE_TIME | + PCI_L1SS_CAP_P_PWR_ON_VALUE, + val); =20 /* Program L0s and L1 entrance latencies */ - val =3D dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); - val &=3D ~PORT_AFR_L0S_ENTRANCE_LAT_MASK; + val =3D 0; val |=3D (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT); val |=3D PORT_AFR_ENTER_ASPM; - dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); + dw_pcie_clear_and_set_dword(pci, PCIE_PORT_AFR, + PORT_AFR_L0S_ENTRANCE_LAT_MASK, val); } =20 static void init_debugfs(struct tegra_pcie_dw *pcie) @@ -860,31 +855,26 @@ static void config_gen3_gen4_eq_presets(struct tegra_= pcie_dw *pcie) dw_pcie_writeb_dbi(pci, offset + i, val); } =20 - val =3D dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); - val &=3D ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); + dw_pcie_clear_and_set_dword(pci, GEN3_RELATED_OFF, + GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, 0); =20 - val =3D dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); - val &=3D ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC; - val |=3D FIELD_PREP(GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC, 0x3ff); - val &=3D ~GEN3_EQ_CONTROL_OFF_FB_MODE; - dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val); + dw_pcie_clear_and_set_dword(pci, GEN3_EQ_CONTROL_OFF, + GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC | + GEN3_EQ_CONTROL_OFF_FB_MODE, + FIELD_PREP(GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC, 0x3ff)); =20 - val =3D dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); - val &=3D ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; - val |=3D (0x1 << GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT); - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); + dw_pcie_clear_and_set_dword(pci, GEN3_RELATED_OFF, + GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, + 0x1 << GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT); =20 - val =3D dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); - val &=3D ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC; - val |=3D FIELD_PREP(GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC, - pcie->of_data->gen4_preset_vec); - val &=3D ~GEN3_EQ_CONTROL_OFF_FB_MODE; - dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val); + dw_pcie_clear_and_set_dword(pci, GEN3_EQ_CONTROL_OFF, + GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC | + GEN3_EQ_CONTROL_OFF_FB_MODE, + FIELD_PREP(GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC, + pcie->of_data->gen4_preset_vec)); =20 - val =3D dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); - val &=3D ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); + dw_pcie_clear_and_set_dword(pci, GEN3_RELATED_OFF, + GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, 0); } =20 static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp) @@ -892,7 +882,6 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *p= p) struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); struct tegra_pcie_dw *pcie =3D to_tegra_pcie(pci); u32 val; - u16 val_16; =20 pp->bridge->ops =3D &tegra_pci_ops; =20 @@ -900,32 +889,25 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp = *pp) pcie->pcie_cap_base =3D dw_pcie_find_capability(&pcie->pci, PCI_CAP_ID_EXP); =20 - val =3D dw_pcie_readl_dbi(pci, PCI_IO_BASE); - val &=3D ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8); - dw_pcie_writel_dbi(pci, PCI_IO_BASE, val); + dw_pcie_clear_and_set_dword(pci, PCI_IO_BASE, + IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8, 0); =20 - val =3D dw_pcie_readl_dbi(pci, PCI_PREF_MEMORY_BASE); - val |=3D CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE; - val |=3D CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE; - dw_pcie_writel_dbi(pci, PCI_PREF_MEMORY_BASE, val); + dw_pcie_clear_and_set_dword(pci, PCI_PREF_MEMORY_BASE, 0, + CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE | + CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE); =20 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); =20 /* Enable as 0xFFFF0001 response for RRS */ - val =3D dw_pcie_readl_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT); - val &=3D ~(AMBA_ERROR_RESPONSE_RRS_MASK << AMBA_ERROR_RESPONSE_RRS_SHIFT); - val |=3D (AMBA_ERROR_RESPONSE_RRS_OKAY_FFFF0001 << - AMBA_ERROR_RESPONSE_RRS_SHIFT); - dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val); + dw_pcie_clear_and_set_dword(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, + AMBA_ERROR_RESPONSE_RRS_MASK << AMBA_ERROR_RESPONSE_RRS_SHIFT, + AMBA_ERROR_RESPONSE_RRS_OKAY_FFFF0001 << + AMBA_ERROR_RESPONSE_RRS_SHIFT); =20 /* Clear Slot Clock Configuration bit if SRNS configuration */ - if (pcie->enable_srns) { - val_16 =3D dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + - PCI_EXP_LNKSTA); - val_16 &=3D ~PCI_EXP_LNKSTA_SLC; - dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA, - val_16); - } + if (pcie->enable_srns) + dw_pcie_clear_and_set_dword(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA, + PCI_EXP_LNKSTA_SLC, 0); =20 config_gen3_gen4_eq_presets(pcie); =20 @@ -937,17 +919,13 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp = *pp) disable_aspm_l12(pcie); } =20 - if (!pcie->of_data->has_l1ss_exit_fix) { - val =3D dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); - val &=3D ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); - } + if (!pcie->of_data->has_l1ss_exit_fix) + dw_pcie_clear_and_set_dword(pci, GEN3_RELATED_OFF, + GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL, 0); =20 - if (pcie->update_fc_fixup) { - val =3D dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF); - val |=3D 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT; - dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val); - } + if (pcie->update_fc_fixup) + dw_pcie_clear_and_set_dword(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, + 0, 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT); =20 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); =20 @@ -1018,9 +996,8 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pc= i) reset_control_deassert(pcie->core_rst); =20 offset =3D dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_DLF); - val =3D dw_pcie_readl_dbi(pci, offset + PCI_DLF_CAP); - val &=3D ~PCI_DLF_EXCHANGE_ENABLE; - dw_pcie_writel_dbi(pci, offset + PCI_DLF_CAP, val); + dw_pcie_clear_and_set_dword(pci, offset + PCI_DLF_CAP, + PCI_DLF_EXCHANGE_ENABLE, 0); =20 tegra_pcie_dw_host_init(pp); dw_pcie_setup_rc(pp); @@ -1847,11 +1824,9 @@ static void pex_ep_event_pex_rst_deassert(struct teg= ra_pcie_dw *pcie) =20 reset_control_deassert(pcie->core_rst); =20 - if (pcie->update_fc_fixup) { - val =3D dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF); - val |=3D 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT; - dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val); - } + if (pcie->update_fc_fixup) + dw_pcie_clear_and_set_dword(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, + 0, 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT); =20 config_gen3_gen4_eq_presets(pcie); =20 @@ -1863,11 +1838,9 @@ static void pex_ep_event_pex_rst_deassert(struct teg= ra_pcie_dw *pcie) disable_aspm_l12(pcie); } =20 - if (!pcie->of_data->has_l1ss_exit_fix) { - val =3D dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); - val &=3D ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); - } + if (!pcie->of_data->has_l1ss_exit_fix) + dw_pcie_clear_and_set_dword(pci, GEN3_RELATED_OFF, + GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL, 0); =20 pcie->pcie_cap_base =3D dw_pcie_find_capability(&pcie->pci, PCI_CAP_ID_EXP); --=20 2.25.1